KR100324602B1 - A manufacturing method of a semiconductor device capable of one-time package processing - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device for reducing the time required for a packaging process, wherein a plurality of chips each composed of at least one semiconductor circuit element are formed on a wafer, and then upper and lower packages are formed on both sides of the wafer. After forming each of the molding layers, a predetermined portion and a cutting line of the upper package molding layer corresponding to the cutting line for separating the chips are sequentially etched, but the chip rail is formed by etching a width larger than the cutting line, and the chip rail Forming an additional package molding layer embedded in the substrate; and cutting the additional package molding layer and the wafer along the cutting line.

Since the manufacturing method of the semiconductor device shortens the time required for the packaging process, it lowers the manufacturing cost, increases the production efficiency, and molds to the edge of the semiconductor chip, thereby preventing the penetration of moisture from the outside.

Description

A manufacturing method of a semiconductor device capable of one-time package processing

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a semiconductor manufacturing method, and more particularly, to a package manufacturing method of a semiconductor device capable of a batch process.

In the case of high-speed operation chips or chips with a large number of input / output (I / O), new package methods such as chip size package (CSP) and ball grid array (BGA) have recently been adopted for stable operation of semiconductor circuits and interfaces. .

Conventionally, in order to manufacture a semiconductor device such as a highly integrated memory chip, many circuit elements such as transistors and resistors are generally formed on a wafer through a general semiconductor process. At this time, as shown in FIG. 1, a plurality of chips are formed on one wafer, and each chip is composed of a plurality of circuit elements. Thereafter, the wafer is sawed to separate the chips. The separated chips are packaged through the CSP or BGA package process as described above. In addition, in order to package each of the separated chips, each chip must be individually mounted on the packaging equipment to proceed with the packaging process.

Therefore, as the number of chips per wafer increases, the time for mounting the chips in the package equipment increases, thereby increasing the time required for the overall package process. In addition, there is a problem that additional packaging equipment is required. In addition, when the chips are individually separated and mounted on the package equipment, the alignment is not performed on a wafer basis but on a chip basis, thereby increasing the overall time required for alignment and the like.

Accordingly, an object of the present invention is to provide a semiconductor manufacturing method that can reduce the time required for the packaging process.

Another object of the present invention is to provide a semiconductor manufacturing method that does not require additional packaging equipment even when the number of chips per wafer is large.

1 is a plan view showing a semiconductor wafer on which a plurality of chips are formed;

2A and 2B are schematic cross-sectional views and schematic plan views showing a semiconductor chip after a package process is completed;

3A and 3B are detailed cross-sectional views and detailed plan views showing a semiconductor chip after a package process is completed;

4 to 7 are diagrams illustrating one embodiment of a method for manufacturing a package of a semiconductor device according to the present invention;

8 to 11 illustrate another embodiment of a method for manufacturing a package of a semiconductor device according to the present invention.

* Explanation of symbols for the main parts of the drawings

20: wafer 30: chip

40: flat zone 50: package pin

60: pad 70: package molding layer

80: passivation layer 80a: contact hole

90: metal wiring

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method comprising: forming a plurality of chips each of at least one semiconductor circuit element on a wafer and a cutting line for separating the chips; Forming upper and lower package molding layers on the whole, and sequentially etching a predetermined portion of the upper package molding layer and the cutting line corresponding to the cutting line, and etching the chip rail by a width larger than the cutting line. Forming an additional package molding layer embedded in the chip rail; and cutting the additional package molding layer and the wafer along the cutting line and dividing the additional package molding layer into a plurality of packaged chips. A method of manufacturing a semiconductor device is provided. According to an embodiment, a fin contact for selectively patterning the upper and additional package molding layers to expose portions electrically connected to the circuit elements formed thereunder after the process of forming the additional package molding layer and before the process of cutting the wafer. Forming a hole; The method may further include forming a metal ball for pin protruding to the outside while filling the pin contact hole. The method may further include forming a passivation layer on the plurality of chips after forming the plurality of chips and before forming the upper and lower package molding layers; Selectively patterning the passivation layer to form a pad contact hole for exposing a pad for applying a signal to or reading a signal from the circuit element; The method may further include forming a metal wire connected to the pad through the pad contact hole on the passivation layer, wherein the pin contact hole may expose a portion of the metal wire.

Hereinafter, with reference to the accompanying drawings, the present invention will be described in detail.

Prior to describing the package manufacturing method of the semiconductor device according to the present invention, the configuration of the semiconductor device after the package process is completed will be described with reference to FIGS. 1 to 3.

1 illustrates a semiconductor wafer 20 in which a plurality of chips are formed. Referring to FIG. 1, a plurality of chips 30 are formed on a wafer 20, and circuit elements such as transistors and capacitors are formed on each chip through a conventional semiconductor manufacturing process. In addition, a flat zone 40 is formed on the wafer 20 for alignment.

2A shows a cross-sectional view of the chip 30 after the package process is completed, and FIG. 2B shows a plan view of the chip 30 after the package process is completed. In FIG. 2A, package molding layers 70 are formed on upper and lower portions of at least one semiconductor circuit element, for example, a transistor, a capacitor, and a resistor 30. 2A and 2B, a plurality of fins 50 are formed on the package molding layer 70, and the fins 50 are electrically connected to the circuit elements formed on the chip 30. .

3A and 3B are more detailed views of FIGS. 2A and 2B. 3A and 3B, the fins 50 formed on the package molding layer 70 are connected to the pad 60 by the metal wire 90. The pad 60 represents a contact for applying an electrical signal to or reading an electrical signal from a semiconductor circuit element formed on the chip 30. In addition, the passivation layer 80 is formed to protect the chip 30 and the contact hole 80a for exposing the pad 60 is open.

Description of the first embodiment

4 to 7 are diagrams showing a first embodiment of the method for manufacturing a semiconductor device according to the present invention.

4 is a cross-sectional view of a wafer on which a fabrication process is completed, that is, a wafer on which a plurality of chips 30 on which at least one semiconductor circuit element is formed are formed. In FIG. 4, the surface on which the semiconductor circuit elements are not formed may be polished, for example, through a backgrinding process after the fabrication process is completed.

Referring to FIG. 5, the passivation layer 80 is formed on the entire surface of the wafer 20. The passivation layer 80 may be formed of, for example, a silicon nitride layer deposited by using a polyimide layer or a Plasma Enhanced Chemical Vapor Deposition (PECVD) method. Next, the passivation layer 80 is patterned to form a pad contact hole 80a. The patterning is done through conventional photolithography processes. For example, by applying a photoresist layer on top of the passivation layer 80 and then exposing it using a predetermined mask, a photoresist pattern is created, and a passivation layer underneath using the photoresist pattern as an etching mask. Etch 80.

In addition, the pad contact hole 80a exposes the pad 60 for applying or reading the electrical signal to the semiconductor circuit element formed under the passivation layer 80. After the pad contact hole 80a is formed, metal is deposited to form a metal layer. At this time, the metal layer fills the pad contact hole 80a and is formed on the front surface. The metal layer is patterned, for example, through a photolithography process using a predetermined mask to form the metal wiring 90. Here, the metal wire 90 serves to connect the pad 60 and the portion where the pin 50 will be formed later.

Referring to FIG. 6, for example, an epoxy molding compound (EMC) (or a low modulus encapsulant) is coated on the metal wire 90 to form a package molding layer 70. Here, before forming the package molding layer 70, for example, a protective film made of a material different from the material constituting the passivation layer may be further formed. The package molding layer 70 is patterned through a conventional patterning process to form pin contact holes 70a. The pin contact hole 70a exposes the metal wire 90 to be connected to the pin 50. A conductive pin 50 is formed on the pin contact hole 70a.

After the fin 50 is formed, the wafer 20 is cut along a scribe line 100 and separated into a plurality of chips 30 to complete a semiconductor device (see FIG. 7).

Description of the second embodiment

In the semiconductor device according to the first embodiment, as shown in FIG. 7, since the package molding layer 70 is not formed at the edge of the chip, the chip 30 is exposed to the air and the chip operation reliability may be due to moisture. There is a risk of getting worse. The second embodiment of the present invention is to solve this disadvantage.

Also in the second embodiment, as described with reference to FIGS. 4 to 5, a plurality of chips 30 in which at least one semiconductor circuit element is formed are formed on the wafer on which the fabrication process is completed. The passivation layer 80 is formed on the entire surface of the wafer 20 and patterned to form a pad contact hole 80a exposing the pad 60. Subsequently, a metal layer is formed and patterned to form a metal wiring 90 connected to the pad 60.

Subsequently, as shown in FIG. 8, first package molding layers 120 and 130 are formed on the upper and lower portions of the wafer on which the metal lines 90 are formed. The first package molding layers 120 and 130 may be formed of, for example, EMC. Subsequently, as illustrated in FIGS. 8 and 9, the upper first package molding layer 120 and the chip 30 are sequentially patterned to form the chip rail 110. The chip rail 110 corresponds to a cutting line 100 for separating the chip 30 shown in FIG. 6, and is preferably wider than the cutting line 100.

Subsequently, after the chip rails 110 are formed, a second package molding layer 140 filling the chip rails 110 is formed, as shown in FIG. 10. The second package molding layer 140 fills the chip rail 110 and is integrated with the upper first package molding layer 120. Subsequently, the upper first package molding layer 120 and the second package molding layer 140 are selectively patterned to form a pin contact hole 120a. Subsequently, after forming copper or a conductive alloy (for example, Alloy-40) embedded in the pin contact hole (not shown), the fin 50 is formed.

Thereafter, the packaged wafer is cut along the cutting line and separated into chips to obtain a semiconductor device in which the edge side of the semiconductor chip as shown in FIG. 11 is completely sealed.

The present invention is not limited to the above embodiments, and many variations are possible by those skilled in the art within the spirit of the present invention.

As described above, the present invention does not cut the chip after fabricating the wafer during the CSP or BGA package process, and performs the package process on the entire wafer, thereby reducing the number of required package equipment. In addition, since a plurality of chips are collectively packaged, manufacturing time can be shortened. In addition, since the alignment is performed at the wafer level in the package, it is possible to prevent a decrease in yield that may occur in the chip-by-chip package.

Claims (3)

In the method of manufacturing a semiconductor device, Forming a plurality of chips each comprising at least one semiconductor circuit element on a wafer and a cutting line for separating the chips; Forming upper and lower package molding layers on the entire wafer; Etching a predetermined portion of the upper package molding layer corresponding to the cutting line and the cutting line sequentially, but forming a chip rail by etching a width larger than the cutting line; Forming an additional package molding layer embedded in the chip rail; Cutting the additional package molding layer and the wafer along the cutting line and dividing the package into a plurality of packaged chips Method for manufacturing a semiconductor device comprising a. The method of claim 1, wherein after the process of forming the additional package molding layer and before the process of cutting the wafer, Selectively patterning the upper and additional package molding layers to form contact holes for fins that expose portions electrically coupled to circuit elements formed thereunder; Forming a pin metal ball protruding to the outside while filling the pin contact hole The manufacturing method of the semiconductor device which further contains. The method of claim 2, wherein after the forming of the plurality of chips and before forming the upper and lower package molding layers, Forming a passivation layer on the plurality of chips; Selectively patterning the passivation layer to form a pad contact hole for exposing a pad for applying a signal to or reading a signal from the circuit element; Forming a metal wire connected to the pad through the pad contact hole on the passivation layer. Including more, The pin contact hole exposes a portion of the metal wiring. The manufacturing method of a semiconductor device.