KR200148627Y1 - Semiconductor wafer carrier - Google Patents

Semiconductor wafer carrier Download PDF

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Publication number
KR200148627Y1
KR200148627Y1 KR2019960014867U KR19960014867U KR200148627Y1 KR 200148627 Y1 KR200148627 Y1 KR 200148627Y1 KR 2019960014867 U KR2019960014867 U KR 2019960014867U KR 19960014867 U KR19960014867 U KR 19960014867U KR 200148627 Y1 KR200148627 Y1 KR 200148627Y1
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South Korea
Prior art keywords
wafer
semiconductor wafer
insertion groove
wafer carrier
carrier
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KR2019960014867U
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Korean (ko)
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KR980005422U (en
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문성렬
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구본준
엘지반도체주식회사
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Priority to KR2019960014867U priority Critical patent/KR200148627Y1/en
Publication of KR980005422U publication Critical patent/KR980005422U/en
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Publication of KR200148627Y1 publication Critical patent/KR200148627Y1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/67313—Horizontal boat type carrier whereby the substrates are vertically supported, e.g. comprising rod-shaped elements
    • H01L21/67316—Horizontal boat type carrier whereby the substrates are vertically supported, e.g. comprising rod-shaped elements characterized by a material, a roughness, a coating or the like

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

본 고안은 반도체 웨이퍼 캐리어에 관한 것으로, 종래에는 삽입홈의 하면이 평면으로 웨이퍼의 장착시 얼라인이 용이치 못하고, 측면이 면접촉을 하게 되어 이물질이 다량 발생하는 문제점이 있었다. 본 고안 반도체 웨이퍼 캐리어는 삽입홈의 하면에 오목부를 형성하여 웨이퍼 장착시 얼라인이 용이한 효과가 있고, 삽입홈의 양측면에 볼록부를 형성하여 종래와 같이 웨이퍼와 삽입홈이 면접촉을 하는 것을 방지함으로서 이물질 발생을 최소화 하는 효과가 있다.The present invention relates to a semiconductor wafer carrier, and in the related art, when the wafer has a lower surface of the insertion groove, alignment is not easy when the wafer is mounted, and the side surface is in contact with the surface. The semiconductor wafer carrier of the present invention has a concave portion formed on the lower surface of the insertion groove to facilitate alignment during wafer mounting, and convex portions are formed on both sides of the insertion groove to prevent surface contact between the wafer and the insertion groove as in the prior art. By doing so, there is an effect of minimizing foreign matters.

Description

반도체 웨이퍼 캐리어Semiconductor wafer carrier

제1도는 종래 반도체 웨이퍼 캐리어의 구조를 보인 것으로,1 shows the structure of a conventional semiconductor wafer carrier,

(a)는 사시도.(a) is a perspective view.

(b)는 정면도.(b) is a front view.

(c)는 삽입홈을 부분적으로 보인 상세도.(c) is a detailed view showing a part of the insertion groove.

제2도는 본 고안 반도체 웨이퍼 캐리어의 삽입홈의 구조를 보인 상세도.Figure 2 is a detailed view showing the structure of the insertion groove of the inventive semiconductor wafer carrier.

제3도는 본 고안의 요부인 삽입홈에 웨이퍼가 장착된 상태를 보인 상세도.3 is a detailed view showing a state in which a wafer is mounted in the insertion groove which is the main part of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 삽입홈 11 : 오목부10: insertion groove 11: recess

12,12' : 블록부12,12 ': block part

본 고안은 반도체 웨이퍼 캐리어(WAFER CARRIER)에 관한 것으로, 특히 웨이퍼가 안정적으로 얼라인(ALIGN) 되고, 웨이퍼에 이물질이 부착되는 것이 최소화되도록 하는데 적합한 반도체 웨이퍼 캐리어에 관한 것이다.The present invention relates to a semiconductor wafer carrier (WAFER CARRIER), and more particularly to a semiconductor wafer carrier suitable for minimizing the alignment of the wafer (ALIGN), the adhesion of foreign matter to the wafer.

일반적으로 반도체 제조공정 중 웨이퍼 세정공정에서는 일명 웨트 스테이션(WET STATION)이라고 하는 세정장비가 사용된다.In general, in the wafer cleaning process of the semiconductor manufacturing process, cleaning equipment called a wet station is used.

이와 같은 웨트 스테이션의 내부에서 각각의 케미컬 베스(CHEMICAL BATH)로 웨이퍼를 이동시키기 위해서는 다량의 웨이퍼 단위로 이동하는 캐리어가 필요한데, 그 캐리어가 제1도에 도시되어 있는 바, 이를 간단히 설명하먼 다음과 같다.In order to move the wafer into each chemical bath inside the wet station, a carrier moving in units of a large amount of wafers is required, and the carrier is shown in FIG. same.

제1도는 종래 반도체 웨이퍼 캐리어의 구조를 보인 것으로, (a)는 사시도이고, (b)는 정면도이며, (c)는 삽입홈을 상세하게 보인 상세도이다.1 shows a structure of a conventional semiconductor wafer carrier, (a) is a perspective view, (b) is a front view, and (c) is a detailed view showing the insertion groove in detail.

도시된 바와 같이, 종래의 반도체 웨이퍼 캐리어는 몸체(1)의 상면 양측에 웨이퍼(2)를 삽입하기 위한 다수개의 삽입홈(3)이 형성되어 있다.As shown, a conventional semiconductor wafer carrier is formed with a plurality of insertion grooves 3 for inserting the wafer 2 on both sides of the upper surface of the body (1).

그리고, (c)에 도시된 바와 같이, 상기 삽입홈(3)의 상부 양측은 웨이퍼(2)의 안착시 안내되도록 내측을 향하여 경사가 형성되어 있고, 하면은 펑면인 구조로 되어 있다.And, as shown in (c), the upper both sides of the insertion groove 3 is inclined toward the inside so as to be guided when the wafer 2 is seated, the bottom surface is a flat surface structure.

이와 같이 구성되어 있는 종래 반도체 웨이퍼 캐리어를 이용하여 웨이퍼를 세정하는 동작을 설명하면 다음과 같다.The operation of cleaning the wafer using the conventional semiconductor wafer carrier configured as described above is as follows.

웨이퍼가 수납되어 있는 캐리어를 로더(LOADER)로 이동하고, 카세트 (CASSETTE)를 하강시키면 웨이퍼(2)가 캐리어의 삽입홈(3)에 각각 삽입된다. 이와 같이 웨이퍼(2)가 캐리어에 장착되면 로봇 아암(ROBOT ARM)이 각각의 케미컬 베스를 이동하며 세정공정을 진행하게 된다. 이와 같이 세정공정을 진행하여 모든 공정이 완료되면 다시 캐리어에 장착되어 있는 웨이퍼(2)를 카세트로 이동하여 다음공정으로 반출시키게 되는 것이다.When the carrier in which the wafer is stored is moved to a loader and the cassette is lowered, the wafer 2 is inserted into the insertion groove 3 of the carrier, respectively. As such, when the wafer 2 is mounted on a carrier, a robot arm (ROBOT ARM) moves each chemical bath and performs a cleaning process. In this way, when the cleaning process is performed and all the processes are completed, the wafer 2 mounted on the carrier is moved to the cassette to be carried out to the next process.

그러나, 상기와 같은 캐리어의 삽입홈(3)은 하면이 평면인 구조로 되어 있어서, 웨이퍼(2)를 삽입시에 안정적인 얼라인이 어려운 문제점이 있었고, 상기 삽입홈(3)의 양측면에 웨이퍼(2)가 면접촉을 하기 때문에 이물질이 다량 발생하는 문제점이 있었다.However, since the insertion groove 3 of the carrier has a structure having a flat lower surface, there is a problem that it is difficult to align stable when the wafer 2 is inserted, and the wafers are formed on both sides of the insertion groove 3. There is a problem that a large amount of foreign matter occurs because 2) the surface contact.

본 고안의 주목적은 상기와 같은 여러 문제점을 갖지 않는 반도체 웨이퍼 캐리어를 제공함에 있다.An object of the present invention is to provide a semiconductor wafer carrier which does not have various problems as described above.

본 고안의 다른 목적은 웨이퍼의 얼라인이 용이한 반도체 웨이퍼 캐리어를 제공함에 있다.Another object of the present invention is to provide a semiconductor wafer carrier that can be easily aligned.

본 고안의 또다른 목적은 웨이퍼에 이물질 발생을 최소화하는 반도체 웨이퍼 캐리어를 제공함에 있다.Another object of the present invention is to provide a semiconductor wafer carrier that minimizes the generation of foreign matter on the wafer.

상기와 같은 본 고안의 목적을 달성하기 위하여 몸체의 상면 양측에 형성된 다수개의 삽입홈 하면에 웨이퍼의 얼라인이 용이하도록 하기 위한 오목부를 형성하고, 양측면에 웨이퍼의 점접촉을 이루게 하기 위한 블록부를 형성한 것을 특징으로 하는 반도체 웨이퍼 캐리어가 제공된다.In order to achieve the object of the present invention as described above, a recess is formed on the bottom of the plurality of insertion grooves formed on both sides of the upper surface of the body to facilitate alignment of the wafer. There is provided a semiconductor wafer carrier characterized by one.

이하, 상기와 같이 구성되어 있는 본 고안 반도체 웨이퍼 캐리어를 첨부된 도면의 실시예를 참고하여 보다 상세히 설명하면 다음과 같다.Hereinafter, the present invention semiconductor wafer carrier having the above-described configuration will be described in more detail with reference to embodiments of the accompanying drawings.

제2도는 본 고안 반도체 웨이퍼 캐리어의 삽입홈의 구조를 보인 상세도로서, 도시된 바와 갈이, 웨이퍼 캐리어의 상면 양측에 형성되어 있는 다수개의 삽입홈(10)의 하면에 오목부(11)를 형성하고, 상기 삽입홈 (10)의 양측면에는 블록부(12)(12')를 각각 형성하였다.2 is a detailed view showing the structure of the insertion groove of the semiconductor wafer carrier of the present invention. As shown in FIG. 2, the recess 11 is formed on the lower surface of the plurality of insertion grooves 10 formed on both sides of the upper surface of the wafer carrier. And the block portions 12 and 12 'are formed on both side surfaces of the insertion groove 10, respectively.

통상적인 웨이퍼의 두께가 0.72mm이므로, 상기 오목부(11)의 하면 양측치수(a)는 1.38mm로 하고, 상기 볼록부(12)(12')간의 간격(b)은 0.85mm 로 하는 것이 바람직하다.Since the conventional wafer has a thickness of 0.72 mm, both sides of the concave portion 11 have a dimension of 1.38 mm, and a space b between the convex portions 12, 12 'is 0.85 mm. desirable.

그리고, 상기 오목부(11)의 곡률반경은 90℃∼135℃ 로 하는 것이 바람직하고, 상기 블록부(12)(12')의 곡률반경은 30℃∼60℃로 하는 것이 바람직하다.The radius of curvature of the recess 11 is preferably 90 ° C to 135 ° C, and the radius of curvature of the block portions 12 and 12 'is preferably 30 ° C to 60 ° C.

상기와 같이 구성되어 있는 본 고안 반도체 웨이퍼 캐리어의 작용 효과를 설명하먼 다음과 같다.The following describes the operation and effect of the inventive semiconductor wafer carrier constructed as described above.

제3도에 도시되어 있는 바와 같이, 삽입홈(10)의 하면에 형성되어 있는 오목부(11)가 웨이퍼(13)의 측면과 동일한 형상을 이루고 있어서, 세정공정을 진행하기 위하여 웨이퍼(13)를 캐리어의 삽입홈(10)에 장착시 안정적으로 장착된다.As shown in FIG. 3, the recess 11 formed in the lower surface of the insertion groove 10 has the same shape as the side surface of the wafer 13, so that the wafer 13 can be cleaned in order to proceed with the cleaning process. When it is mounted in the insertion groove 10 of the carrier it is mounted stably.

그리고, 상기 삽입홈(10)의 양측면에 볼록부(12)(12')를 형성하여 웨이퍼(13)의 측면과 접촉면적을 최소화 되도록 하여 이물질이 부착되는 것을 줄이게 되고, 또한 마찰에 의한 이물질 발생도 최소화 하게 된다.In addition, convex portions 12 and 12 ′ are formed on both side surfaces of the insertion groove 10 to minimize the contact area with the side surface of the wafer 13, thereby reducing foreign matters from adhering, and also generating foreign substances due to friction. Will also be minimized.

이상에서 상세히 설명한 바와 같이, 본 고안 반도체 웨이퍼 캐리어는 삽입홈의 하면에 오목부를 형성하여 웨이퍼 장착시 얼라인이 용이한 효과가 있고, 삽입홈의 양측면에 볼록부를 형성하여 종래와 같이 웨이퍼와 삽입홈이 면접촉을 하는 것을 방지함으로서 이물질 발생을 최소화 하는 효과가 있다.As described in detail above, the semiconductor wafer carrier of the present invention has a recessed portion formed on the lower surface of the insertion groove, so that the wafer can be easily aligned when the wafer is mounted. By preventing the surface contact, there is an effect to minimize the generation of foreign matter.

Claims (2)

다수개의 삽입홈 하면에 웨이퍼의 얼라인이 용이하도록 하기 위한 오목부를 형성하고, 양측면에 웨이퍼의 점접촉을 이루게 하기 위한 볼록부를 형성한 것을 특징으로 하는 반도체 웨이퍼 캐리어.A semiconductor wafer carrier comprising a concave portion for facilitating alignment of a wafer on a lower surface of a plurality of insertion grooves, and a convex portion for forming point contact of the wafer on both sides thereof. 제1항에 있어서, 상기 오목부의 곡률반경은 90℃ ∼135℃ 로 하고, 상기 볼록부의 곡률반경은 30℃ ∼60℃ 로 하는 것을 특징으로 하는 반도체 웨이퍼 캐리어.The semiconductor wafer carrier according to claim 1, wherein the radius of curvature of the concave portion is 90 ° C to 135 ° C, and the radius of curvature of the convex portion is 30 ° C to 60 ° C.
KR2019960014867U 1996-06-04 1996-06-04 Semiconductor wafer carrier KR200148627Y1 (en)

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KR980005422U KR980005422U (en) 1998-03-30
KR200148627Y1 true KR200148627Y1 (en) 1999-06-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100487541B1 (en) * 2002-09-06 2005-05-03 삼성전자주식회사 Wafer guides used in cleaning/drying process of semiconductor substrates

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030048682A (en) * 2001-12-12 2003-06-25 삼성전자주식회사 Wafer guide and wet etching apparatus having it

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100487541B1 (en) * 2002-09-06 2005-05-03 삼성전자주식회사 Wafer guides used in cleaning/drying process of semiconductor substrates
US6959823B2 (en) 2002-09-06 2005-11-01 Samsung Electronics Co., Ltd. Wafer guides for processing semiconductor substrates

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