US20070125726A1

US20070125726A1 - Wafer guide in wafer cleaning apparatus

Info

Publication number: US20070125726A1
Application number: US11/523,042
Authority: US
Inventors: Hu-Won Seo
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2005-12-02
Filing date: 2006-09-19
Publication date: 2007-06-07
Also published as: KR100631928B1

Abstract

A wafer guide in a wafer cleaning apparatus comprises of a lower panel portion. The wafer guide also comprises of a plurality of wafer supporting panel portions, the plurality of wafer supporting panel portions being configured to protrude from at least one side of the lower panel portion and support a wafer. The wafer guide also comprises of a plurality of slot portions, the plurality of slot portions being configured to form at upper ends of the plurality of wafer supporting panel portions and hold the wafer by forming contact with at least a portion of a wafer edge area without forming contact with a wafer cell area.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates generally to semiconductor device manufacturing equipment and, more particularly, to a wafer cleaning apparatus which removes impurities on the surface of a wafer.
This application claims the benefit of Korean Patent Application No. 10-2005-0116945, filed Dec. 2, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
2. Description of the Related Art
Semiconductor devices are manufactured using various processes such as, for example, an impurity ion implantation process, a thin film deposition process, an etching process, and a chemical mechanical polishing (CMP) process. The impurity ion implantation process implants 3B or 5B group impurity ions into a semiconductor. The thin film deposition process forms one or more layers on a semiconductor substrate. The etching process patterns the one or more layers formed on the semiconductor substrate in a predetermined pattern. The CMP process levels the wafer surface by polishing the wafer surface after the deposition of a layer such as an interlayer insulating layer on the wafer.
While the above-mentioned processes may be used to fabricate semiconductor devices, these processes also generate contaminants. These contaminants may adhere to the surface of the semiconductor wafer during the manufacturing of the semiconductor device. There is therefore a need for a wafer cleaning process to clean the wafer periodically during the semiconductor manufacturing process.
Generally, during a wafer cleaning process, a wafer to be cleaned is held in a wafer vessel which is also known as a wafer guide. A wafer guide is disclosed in Korean Patent No.10-0512183 and U.S. Pat. No. 6,235,147. The wafer guide includes slots for holding the wafer. Furthermore, the wafers held in the slot portions are immersed into chemical bathes for cleaning, and are moved to a drying portion to dry the wafers.
When wafers held in a wafer guide are moved from one spot to another, the movement of the wafer guide may produce vibrations that may damage the wafers. In order to protect the wafers from vibrations, the wafers may be inserted deep into slots of the wafer guide. The deep insertion of the wafers in the slots of the wafer guide may increase the stability of the held wafers thus protecting the wafers from vibrations.
However, inserting wafers deep into the slots of the wafer guide may cause problems. For example, studies show that as the wafers are inserted deep into the slots, the amount of wafer surface coming in contact with the slots increases. This increase in the contact surface between the wafer and the slot may lead to a greater possibility of the wafer being damaged. The damage to the wafer may occur because of scratches forming on the wafer surface in contact with the slot. Furthermore, as a cleaning solution flows through the scratches, additional defects may also be formed in the wafer.
The problems due to scratches on a wafer are exacerbated when the integration density of a semiconductor device is increased. Specifically, when the integration density of semiconductors is increased, there is a tendency to position cells closer to the edge of a wafer so as to increase the number of cells per wafer. Thus, there are now more cells on a wafer surface that is directly in contact with a slot holding the wafer. This design issue coupled with the problem of an increase in the contact surface between a slot and a wafer may increase the number of scratch related defects in semiconductor wafers. These problems may decrease the production yield of the semiconductor manufacturing process.
In a conventional wafer guide, slot portions for holding wafers are formed at positions such that the slot portions may hold the wafer at the center of a wafer flat zone. Thus, for example, when wafers are loaded in a conventional wafer guide such that the wafer flat zone is oriented towards the bottom, an area that is 4.4 mm from the wafer edge area may be in contact with the slot portions of the wafer guide. On the other hand, when wafers are loaded in a conventional wafer guide such that the wafer flat zone is oriented towards the top, an area that is 6 mm from the wafer edge area may be in contact with the slot portions of the wafer guide. FIGS. 1 through 3 show exemplary intervals between a wafer edge area and a wafer cell area in currently produced wafers.
FIG. 1 illustrates a first wafer in which the distance between a wafer edge area 10 and a wafer cell area 12 is 5 mm. FIG. 2 illustrates a second wafer in which the distance between a wafer edge area 20 and a wafer cell area 22 is 4 mm. FIG. 3 illustrates a third wafer in which the distance between a wafer edge area 30 and a wafer cell area 32 is 3.5 mm.
Under certain conditions, when wafers of FIGS. 1 through 3 are loaded in the conventional wafer guide, scratches may occur in the wafer cell areas. For example, when the first wafer in which the distance between a wafer edge area 10 and a wafer cell area 12 is 5 mm, is loaded such that the wafer flat zone is oriented towards the bottom, no scratches occur in the wafer cell area 12. However, when the first wafer is loaded such that the wafer flat zone is oriented towards the top, scratches occur in the wafer cell area 12 because the length of contact between the slot portion and the wafer surface (6 mm) exceeds the distance of 5 mm between the wafer edge area 10 and the wafer cell area 12. Furthermore, in the second wafer (in which the distance between the wafer edge area 20 and the wafer cell area 22 is 4 mm) and the third wafer (in which the distance between the wafer edge area 30 and the wafer cell area 32 is 3.5 mm,) the length of contact between the slot portion and the wafer surface exceeds the distance between the wafer edge area and the wafer cell area, regardless of the direction of loading the wafers (i.e., regardless of whether the wafer flat zone is oriented towards the bottom or top.) Therefore, it is likely that scratches will occur in the wafer cell area leading to defects in the wafer and to a decrease in the production yield of the semiconductor manufacturing process.
FIGS. 4A and 4B depict wafer cell areas that include scratches. Referring to FIGS. 4A and 4B, each wafer cell area 42 is separated from other cell areas by a scribe line 40. Furthermore, each cell area 42 includes scratches 44 that are formed because of the contact between a slot portion and the wafer cell area 42.
FIGS. 5A and 5B depict a wafer cell area having defects caused by fluids flowing along the scratches 44. Specifically, when a wafer with scratches 44 in the wafer cell area (as shown in FIGS. 4A and 4B) is immersed into a chemical bath, a cleaning solution flows along the scratch tracks. As a result, a defect 46 caused by the movement of fluid along the scratches 44 occurs. Defect 46 may include, for example, the removal of a layer such as poly-silicon that functions as a storage electrode, from the wafer cell area 42. Such a defect caused by the movement of fluids through the wafer cell area may also result in a decrease in the production yield of the semiconductor manufacturing process.
The present disclosure is directed towards overcoming one or more shortcomings of the conventional wafer guide apparatus.

SUMMARY OF THE INVENTION

One aspect of the present disclosure includes a wafer guide in a wafer cleaning apparatus. The wafer guide comprises of a lower panel portion. The wafer guide also comprises of a plurality of wafer supporting panel portions, the plurality of wafer supporting panel portions being configured to protrude from at least one side of the lower panel portion and support a wafer. The wafer guide also comprises of a plurality of slot portions, the plurality of slot portions being configured to form at upper ends of the plurality of wafer supporting panel portions and hold the wafer by forming contact with at least a portion of a wafer edge area without forming contact with a wafer cell area.
Another aspect of the present disclosure includes a wafer guide in a wafer cleaning apparatus. The wafer guide comprises of a lower panel portion. The wafer guide also comprises of a pair of outer wafer supporting panel portions, formed at right and left side edges of the lower panel portion, supporting a wafer. The wafer guide also comprises of a pair of inner wafer supporting panel portions formed between the pair of outer wafer supporting panel portions and spaced apart from each other by a distance exceeding a length of a wafer flat zone, supporting the wafer. The wafer guide also comprises of a plurality of slot portions, formed at upper ends of the pair of outer wafer supporting panel portions and the pair of inner wafer supporting panel portions, holding the wafer by forming contact with at least a portion of a wafer edge area without forming contact with a wafer cell area.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail preferred embodiments thereof with reference to the attached drawings in which:
FIGS. 1 through 3 illustrate the distance between a wafer cell area and a wafer edge area in exemplary wafers, respectively;
FIGS. 4A and 4B depict a wafer cell area including scratches;
FIGS. 5A and 5B depict a wafer cell area including defects caused by the movement of fluid along the scratches;
FIG. 6 illustrates a wafer cleaning apparatus including a wafer guide according to an exemplary disclosed embodiment;
FIG. 7 is a front view of the wafer guide according to an exemplary disclosed embodiment;
FIG. 8 is a side view of the wafer guide according to an exemplary disclosed embodiment;
FIG. 9 is a perspective view of the wafer guide according to an exemplary disclosed embodiment;
FIG. 10 is a partially enlarged view of an outer wafer supporting panel portion of the wafer guide according to an exemplary disclosed embodiment;
FIG. 11 illustrates a state when a wafer is held in the outer wafer supporting panel portion of FIG. 10;
FIG. 12 is a partially enlarged view of an inner wafer supporting panel portion of the wafer guide according to an exemplary disclosed embodiment; and
FIG. 13 illustrates a state when a wafer is held in the inner wafer supporting panel portion of FIG. 12.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. However, the invention should not be construed as limited to only the embodiments set forth herein. Rather, the present invention may be embodied in many different forms, and the embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
Various unit processes such as, for example, an ion implantation process, deposition process, and etching process, are performed on a wafer during a semiconductor fabrication process. These unit processes also generate contaminants. These contaminants may include material layers such as a photosensitive layer that is not removed properly during an etching process, or reaction byproducts such as polymers. Furthermore, these polymers adhere to the surface of a semiconductor wafer and may cause various problems including chip failure. In order to reduce the chances of chip failure due to these contaminants, it is advisable to clean the wafer during the semiconductor fabrication process to remove the contaminants. It is therefore necessary to implement a wafer cleaning process in addition to the other processes used in the semiconductor fabrication process.
With the increase in density of semiconductor chips, and the consequent increase in density of cells per unit area of a wafer, the cleaning of a wafer surface assumes even greater importance because even a small amount of contamination may cause defects in the wafer. It is also advisable to implement a wafer cleaning process before and after each unit process used in the manufacturing of a semiconductor device.
The wafer cleaning process includes two types of cleaning—wet cleaning and dry cleaning. The wet cleaning process uses chemicals and the dry type cleaning uses vapor or plasma.
The wet cleaning process includes cleaning, rinsing, and drying. The cleaning process includes immersing the wafer in a cleaning solution. Specifically, an acid or alkaline solution may be used to clean the wafer. The type of cleaning solution used may depend on the type of impurities to be removed. For example, an acid such as H₂SO₄may be used to remove organic impurities whereas a hydrogen fluoride solution may be used to remove a native oxide layer. The concentration, amount, and temperature of the cleaning solution used may depend on the type of wafer to be cleaned and the cleaning conditions such as the cleaning apparatus.
After the cleaning process is completed, the cleaned wafer may be subject to a rinsing process. During the rinsing process, the cleaning solution stuck to the wafer is removed by using liquids such as, for example, DI (de-ionized) water. Specifically, DI water is sprayed onto the surface of the wafer to remove the cleaning solution from the surface of the wafer. In addition, a wafer may be subject to multiple rinse processes. For example, prior to the drying process, a final rinse process may involve the use of DI water wherein the temperature of the DI water is maintained in a desired range such as, for example, 23-25° C. Furthermore, the drying process is used to dry the wafer after it is cleaned and rinsed. The drying process may include the use of an IPA drier to remove the DI water from the wafer surface.
In addition, a wafer may be physically cleaned. Specifically, the physical cleaning method includes a rinse method and a D-sonic method. In the rinse method, a wafer is cleaned by spraying DI water onto the surface of a wafer. Furthermore, the wafer is loaded on a spinning apparatus. The spinning apparatus is configured such that the wafer is spun at a high speed as the wafer is rinsed. In the D-sonic method, contaminants are removed by spraying DI water onto the wafer surface and further applying D-sonic power onto the wafer surface.
FIG. 6 illustrates a wafer cleaning apparatus 100. Wafer cleaning apparatus 100 includes a first loading unit 102, a first counter 104, an aligning unit 106, a separating unit 108, a wafer guide 110, a second loading unit 112, a water bath 114, chemical baths 116-1 through 116-n, a drying unit 118, a second counter unit 120, and an unloading unit 122. As described above, a wet cleaning process includes cleaning, rinsing, and drying. An exemplary wet cleaning process that uses wafer cleaning apparatus 100 will now be described below.
A cassette C including a plurality of wafers W is placed in the first loading unit 102. The cassette C is then transferred by a conveyer (not shown), to the first counter 104 which checks the number of the wafers in the cassette C. The cassette C then passes through the aligning unit 106. The aligning unit 106 aligns the flat zones of the plurality of wafers W in one direction. The cassette C then moves to a separating unit 108. The separating unit 108 separates the wafers W from the cassette C. Specifically, the separating unit 108 includes the wafer guide 110. The wafers W are transferred from the cassette C to the wafer guide 110 in the separating unit 108. The wafers W in the wafer guide 110 are vertically supported by slot portions formed on the upper end of the wafer guide 110. Furthermore, the wafers W that are unloaded from the cassette C onto the wafer guide 110 are cleaned by the chemical baths 116-1 through 116-n before they are reloaded onto the cassette Cat the second loading unit 112. The cassette C, after transferring the wafers W to the wafer guide 108, moves (using the conveyor) to the second loading unit 112. The second loading unit 112 loads the clean wafers onto the cassette C. Until the second loading unit 112 loads the clean wafers onto the cassette C, the cassette C stays in a standby mode at the second loading unit 112.
After being reloaded with the clean wafers by the second loading unit 112, the cassette C is transferred by the conveyor to the second counter unit 120. The second counter unit 120 compares the number of wafers W in the cassette C at this time with the number recorded by the first counter unit 104, thereby verifying whether any wafer is missing in the section between the separating unit 108 and the second loading unit 112. Upon verification of the correct number of wafers W on the cassette C, the cassette C is transferred to the unloading unit 122. The unloading unit 122 unloads the cleaned wafers from the cassette C.
The chemical baths 116-1 through 116-n clean the wafers W in the wafer guide 110. The cleaned wafers are then dried in the drying unit 118. The cleaning and drying process will now be described in detail.
The section between the separating unit 108 and the second loading unit 112 includes a plurality of chemical bathes 116-1 through 116-n. The section also includes the ultra pure water bath 114 and the drying unit 118 that are positioned inline with the plurality of chemical baths. The plurality of chemical bathes 116-1 through 116-n include cleaning solutions having different composition ratios and different characteristics. The wafers W in the wafer guide 110 are selectively placed into the chemical bathes 116-1 through 116-n and the drying unit 118 by at least one or more transfer robots R1 through Rn. Furthermore, similar to the chemical baths, the plurality of transfer robots R1 through Rn, are positioned in the section between the separating unit 108 and the second loading unit 112.
In particular, each wafer W in the wafer guide 110 is placed into the desired chemical bath (e.g., 116-1) by the transfer robot R (e.g., R1) designated for that particular chemical bath. Upon completion of the cleaning process in the chemical bath, the wafer W may be transferred into another cleaning bath (e.g., 116-2) by the designated transfer robot R (e.g., R2) for the other cleaning bath. Alternatively, the cleaned wafer W may be transferred directly to the drying unit 118. Ultimately, all the cleaned wafers will be transferred to the drying unit 118. The number of cleaning baths in which the wafer W is immersed will depend on the type of cleaning desired for the wafer W.
The wafers W that pass through at least one of the plurality of chemical bathes 116-1, through 116-n, the ultra pure water bath 114, and the drying unit 118 are loaded by the second loading unit 112 onto the cassette C. At this time, cassette C is already on standby at the second loading unit 112. The loaded cassette C is then transferred by the conveyer to the second counter unit 120 and the unloading unit 122. As described above, the second counter unit 120 compares the number of wafers W in the cassette C at this time with the number recorded by the first counter unit 104, thereby verifying whether any wafer is missing in the section between the separating unit 108 and the second loading unit 112.
The structure of the wafer guide 110 according to an exemplary disclosed embodiment of the present invention will now be described in detail with reference to the following drawings.
FIG. 7 shows a front structure of the wafer guide 110 according to an embodiment of the present invention. FIGS. 8 and 9 show a side structure and a perspective structure respectively of the wafer guide 110.
Referring to FIGS. 7 through 9, the wafer guide 110 includes a lower panel portion 124; four wafer supporting panel portions 126 a, 126 b, 126 c, and 126 d, and four slot portions 128 a, 128 b, 128 c, and 128 d. The four wafer supporting panel portions 126 a, 126 b, 126 c, and 126 d are formed to protrude on the upper end of one side of the lower panel portion 124 and to be perpendicular to the lower panel portion 124. Furthermore, the four wafer supporting panel portions are spaced parallel to each another at a predetermined interval. The four slot portions 128 a, 128 b, 128 c, and 128 d are formed in a saw-tooth shape to form the upper end of the wafer supporting panel portions 126 a, 126 b, 126 c, and 126 d, respectively. The wafer supporting panel portions 126 a, 126 b, 126 c, and 126 d, where the slot portions 128 a, 128 b, 128 c, and 128 d are formed are made of materials that will minimize damages to the wafer. These materials include, for example, quartz, coated quartz, peek (polyetheretherketon) and teflon materials.
The wafer supporting panel portions 126 a, 126 b, 126 c, and 126 d include a pair of outer wafer supporting panel portions 126 a and 126 b, and a pair of inner wafer supporting panel portions 126 c and 126 d. The outer wafer supporting panel portions 126 a and 126 b are formed at the right and left side edges of the lower panel portion 124. Furthermore, the pair of inner wafer supporting panel portions 126 c and 126 d are formed between the pair of outer wafer supporting panel portions 126 a and 126 b, and spaced apart from the pair of outer wafer supporting panel portions at a predetermined interval. This arrangement of outer and inner wafer supporting panels allows the supporting panels to be arranged symmetrically around the center of a wafer.
FIG. 7 illustrates a length 130 and a distance 132. Length 130 represents a length of the wafer flat zone of wafer W which is loaded onto the wafer guide 110. Distance 132 represents the distance between the inner wafer supporting panel portions 126 c and 126 d. It is preferable that the distance 132 be greater than the length 130. This is because if the distance 132 is less than the length 130, the amount of wafer area coming in contact with the slot portions 128 c and 128 d will vary based on the direction of orientation of the wafer flat zone. For example, when the wafer W is loaded in the wafer guide 110 such that the wafer flat zone faces the bottom, no scratches occur in the wafer cell area. However, when the wafer W is loaded in the wafer guide 110 such that the wafer flat zone faces the top, a larger area of the wafer W is inserted into the slot portions 128 c and 128 d. Because of a larger area of the wafer W coming in contact with the slot portions, the possibility of scratches occurring in the wafer cell area increases. Therefore, in order to minimize the possibility of scratches occurring on the wafer surface when it is mounted in the wafer guide 110 regardless of the direction of orientation of the wafer flat zone, it is preferable to form the inner wafer supporting panel portions 126 c and 126 d such that the distance 132 between the inner wafer supporting panel portions 126 c and 126 d is greater than the length 130 of the wafer flat zone.
The wafer guide 110 may hold the mounted wafer W stably by using the four wafer supporting panel portions 126 a, 126 b, 126 c, and 126 d. As the number of wafer supporting panel portions increases, the wafer may be held more stably. However, as the number of supporting panel portions increase, the contact area between the wafer and the wafer guide 110 also increases, thereby increasing the possibility of scratches occurring on the wafer cell area. Thus, there is a tradeoff between the stability of support for the mounted wafer and the possibility of scratches occurring on the wafer surface. In the wafer guide 110, the use of four wafer supporting panel portions provides sufficient stable support for holding the wafer without the wafer supporting panel portions coming in contact with the wafer cell area.
FIG. 7 illustrates the four portions A, B, C, and D of the wafer W that are in contact with the wafer guide 110. Specifically, the four portions A, B, C, and D of the wafer W are in contact with the four wafer supporting panel portions 126 a, 126 c, 126 d, and 126 b, respectively. Furthermore, the four supporting panel portions 126 a, 126 c, 126 d, and 126 b, support the wafer W by imparting a stabilizing force to portions A, B, C, and D, respectively. Therefore, the stabilizing force provided by the wafer guide 110 is distributed between the four portions A, B, C, and D of the wafer W. Because the four portions A, B, C, and D of the wafer are firmly supported by the four wafer supporting panel portions 126 a, 126 c, 126 d, and 126 b respectively, it is possible to hold the wafer stably in the wafer guide 110 even though the wafer is not inserted deep into the slot portions, as is the practice in the prior art.
The shape of the slot portions formed on the upper end of the wafer guide 110 will now be described in detail with reference to FIGS. 10 through 13.
FIG. 10 is a partially enlarged side view of the slot portion 128 a or 128 b on the outer wafer supporting panel portion 126 a or 126 b of the wafer guide 110. FIG. 11 shows a side view of the slot portion of FIG. 10 when a wafer W is held in the slot portion.
Referring to FIG. 10, the slot portion 128 a is formed in a V shape on the upper end of the outer wafer supporting panel portion 126 a to hold the wafer W. FIG. 11 depicts two sections of the slot portion 128 a. Specifically, the slot portion 128 a can be divided into an upper slot E and a lower slot F. The upper slot E is the area which does not come in direct contact with the wafer W when holding the wafer W, and has an opening angle of 30 to 60 degrees. It is preferable to have the opening angle of the upper slot E to be closer to 60 degrees because the upper slot E is not intended to come in direct contact with the wafer W. The lower slot F is the area which comes in direct contact with the wafer W when holding the wafer W, and has an opening angle 60 to 30 degrees. Because the lower slot F is the area that comes in direct contact with the wafer W, it is preferable to have the opening angle of the lower slot F to be closer to 30 degrees. The total length from the upper slot E to the lower slot F is, for example, 8.5 mm. Specifically, the length of the upper slot E is 4.3 mm, and the length of the lower slot F is 4.5 mm.
When the wafer W is inserted into the slot portion 128 a of the outer wafer supporting panel portion 126 a, the wafer W is inserted into the deepest end of the lower slot F. The length of the deepest end of the lower slot F may be very small in comparison with the total length of the slot portion 128 a. For example, as shown in FIG. 11, the length of the deepest end of the lower slot F is 0.57 mm of the total length of 8.5 mm of the slot portion 128 a. Because only a small portion of the slot portion 128 a is in direct contact with the wafer W, the amount of wafer cell area in contact with the slot portion is also small, thereby leading to few or no scratches being formed in the wafer cell area.
FIG. 12 is a partially enlarged view of a slot portion 128 c or 128 d of the inner wafer supporting panel portion 126 c or 126 d in the wafer guide 110. FIG. 13 shows a side view of the slot portion of FIG. 12 when a wafer W is held in the slot portion.
Referring to FIG. 12, the slot portion 128 c is formed in a Y shape on the upper end of the inner wafer supporting panel portion 126 c for holding the wafer. As shown in FIG. 13, the slot portion 128 c includes a wide upper slot G and a narrow lower slot H. The wide upper slot G is the area which does not come in direct contact with the wafer when holding the wafer, and has an opening angle of 30 to 60 degrees. Because the wide upper slot G does not come in contact with the wafer W, it is preferable to have the opening angle of the wide upper slot G to be closer to 60 degrees. The narrow lower slot H is the area which comes in direct contact with the wafer W and is trench-shaped. The direct contact occurs because the wafer W is inserted into the narrow lower slot H so that the wafer W is tightly held in the narrow lower slot H. The total length from the upper slot G to the lower slot H is, for example, 7.71 mm. Specifically, the length of the upper slot G is 4.36 mm and the length of the lower slot H is 3.5 mm. The width of the lower slot H is generally 0.8 mm, but may vary according to the thickness of the wafer W.
When a wafer W is inserted into the slot portion 128 c of the inner wafer supporting panel portion 126 c, the wafer is held in the lower slot H. As shown in FIG. 13, the total depth of the lower slot H is 3.5 mm. However, as also shown in FIG. 13, the wafer W is inserted into the lower slot H only up to a depth of 1.75 mm. Thus, only 1.75 mm of the length of the wafer W is in direct contact with the slot portion 128 c. Generally, 1.75 mm length of the wafer W includes the wafer edge area only and does not include any portion of the wafer cell area. Thus, even though some scratches may occur within a range of 1.75 mm on the wafer surface (because of the contact with the slot portion,) the scratches do not reach the wafer cell area. Consequently, the scratches do not affect the production yield of the semiconductor manufacturing process.
FIG. 13 shows the length of the wafer W being inserted into the lower slot H as being 1.75 mm. However, one skilled in the art will appreciate that the inserted length shown is exemplary only. The length of the wafer inserted into the lower slot H may depend on the distance between the edge area and the cell area of the wafer and the amount of stability desired in holding the wafer. In the embodiment described and shown in FIG. 13, a wafer may be inserted up to a length of 3.5 mm. Because the distance between the edge area and the cell area in most currently produced wafers is more than 3.5 mm, an insertion up to a length of 3.5 mm may not produce any scratches in the wafer cell area.
The disclosed wafer guide may be used in any system that holds wafers regardless of the orientation of the flat surface of the held wafer. Because the distance between the inner wafer supporting panel portions 126 c and 126 d exceeds the length of the wafer flat zone, the depth of the wafer inserted into the lower slot H may always be the same, regardless of the orientation of the flat surface of the wafer. Specifically, when a wafer is loaded in the disclosed wafer guide, the wafer is inserted into the slot portion at a depth equal to or less than 3.5 mm of the entire wafer area including the wafer flat zone area. Therefore, for wafers whose distance between the wafer edge area and the wafer cell area is greater than 3.5 mm, no scratches may be formed in the wafer cell area. Therefore there may be no decrease in the production yield because of scratches formed on the wafer surface.
As described above, in an exemplary embodiment, the wafer guide includes four supporting panel portions—a pair of inner supporting panel portions and a pair of outer supporting panel portions. Because of the use of four supporting panel portions, it may be possible to insert the wafer up to a lower depth into the slot portions formed at the upper end of the supporting panel portions as compared to an insertion depth in a prior art wafer guide. With the lower insertion depth in the disclosed wafer guide, the contact area between the slot portion and the wafer is reduced compared to a prior art wafer guide. Because of the reduction in the contact area between the slot portion and the wafer, the possibility of scratches being formed in the wafer cell area reduces. Therefore, use of the disclosed wafer guide may prevent a chip failure resulting from the scratches.
The structure of the disclosed wafer guide has been described in accordance with an exemplary embodiment of the present invention. However, one skilled in the art will appreciate that various other embodiments of the wafer guide are also possible without departing from the scope of the invention. For example, the wafer guide in the disclosed embodiment includes four wafer supporting panel portions at one side of the lower panel portion. However, in an alternative exemplary embodiment, the wafer guide may include any number of wafer supporting panel portions.
Furthermore, the wafer guide in the disclosed embodiment includes a flat shaped lower panel portion. Alternatively, the wafer guide may include a lower panel portion that is curve shaped such as, for example, U shaped or V shaped. In addition, in the disclosed embodiment, the wafer supporting panel portions are formed perpendicular to the lower panel portion. However, in an alternative embodiment, the wafer supporting panel portions may be formed at a different angle with respect to the lower panel portion.
In addition, the wafer supporting panel portions in the disclosed wafer guide can be formed of quartz, coated quartz, peek (polyetheretherketon) or teflon materials. However, in an alternative exemplary embodiment, the wafer panel supporting portions can be formed of any other material capable of securing a wafer stably while minimizing damage to the wafer.
The invention has been described using preferred exemplary embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, the scope of the invention is intended to include various modifications and alternative arrangements within the capabilities of persons skilled in the art using presently known or future technologies and equivalents. The scope of the following claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims

1. A wafer guide in a wafer cleaning apparatus, the wafer guide comprising:

a lower panel portion;

a plurality of wafer supporting panel portions, the plurality of wafer supporting panel portions being configured to protrude from at least one side of the lower panel portion and support a wafer; and

a plurality of slot portions, the plurality of slot portions being configured to form at upper ends of the plurality of wafer supporting panel portions and hold the wafer by forming contact with at least a portion of a wafer edge area without forming contact with a wafer cell area.

2. The wafer guide according to claim 1, wherein the wafer supporting panel portions comprise:

a pair of outer wafer supporting panel portions formed at right and left side edges of the lower panel portion; and

a pair of inner wafer supporting panel portions, spaced apart from the pair of outer wafer supporting panel portions by a predetermined distance, and formed between the pair of outer wafer supporting panel portions.

3. The wafer guide according to claim 2, wherein the pair of inner wafer supporting panel portions are spaced apart from each other by a distance exceeding a length of a wafer flat zone.

4. The wafer guide according to claim 3, wherein a length of the wafer inserted into the slot portion of the outer wafer supporting panel portion is 0.1 to 0.6 mm from a wafer edge.

5. The wafer guide according to claim 4, wherein the length of the wafer inserted into the slot portion of the outer wafer supporting panel portion is 0.57 mm from the wafer edge.

6. The wafer guide according to claim 3, wherein a length of the wafer inserted into the slot portion of the inner wafer supporting panel portion is less than or equal to 3.5 mm from the wafer edge.

7. The wafer guide according to claim 6, wherein the length of the wafer inserted into the slot portion of the inner wafer supporting panel portion is 1.75 mm from the wafer edge.

8. A wafer guide in a wafer cleaning apparatus, the wafer guide comprising:

a lower panel portion;

a pair of outer wafer supporting panel portions, formed at right and left side edges of the lower panel portion, supporting a wafer;

a pair of inner wafer supporting panel portions formed between the pair of outer wafer supporting panel portions and spaced apart from each other by a distance exceeding a length of a wafer flat zone, supporting the wafer; and

a plurality of slot portions, formed at upper ends of the pair of outer wafer supporting panel portions and the pair of inner wafer supporting panel portions, holding the wafer by forming contact with at least a portion of a wafer edge area without forming contact with a wafer cell area.

9. The wafer guide according to claim 8, wherein the slot portion formed at the upper end of the outer wafer supporting panel portion comprises:

an outer upper slot which does not form contact with the wafer when holding the wafer; and

an outer lower slot which forms a lower area of the outer upper slot and forms contact with the wafer when holding the wafer.

10. The wafer guide according to claim 9, wherein the outer upper slot and the outer lower slot have an opening angle within a range of 30 to 60 degrees.

11. The wafer guide according to claim 10, wherein the opening angle of the outer upper slot is 60 degrees, and the opening angle of the outer lower slot is 30 degrees.

12. The wafer guide according to claim 9, wherein a length of the wafer inserted into the outer lower slot is 0.1 to 0.6 mm from a wafer edge.

13. The wafer guide according to claim 12, wherein the length of the wafer inserted into the outer lower slot is 0.57 mm from the wafer edge.

14. The wafer guide according to claim 8, wherein the slot portion formed at the upper end of the inner wafer supporting panel portion comprises:

an inner upper slot which does not form contact with the wafer when holding the wafer; and

an inner lower slot which forms the lower area of the inner upper slot and which forms contact when holding the wafer.

15. The wafer guide according to claim 14, wherein an opening angle of the inner upper slot is within a range of 30 to 60 degrees.

16. The wafer guide according to claim 15, wherein the opening angle of the inner upper slot is 60 degrees.

17. The wafer guide according to claim 16, wherein the inner lower slot has a vertically long trench shape.

18. The wafer guide according to claim 17, wherein a length of the wafer inserted into the inner lower slot is less than or equal to 3.5 mm from a wafer edge.

19. The wafer guide according to claim 18, wherein the length of the wafer inserted into the inner lower slot is 1.75 mm from the wafer edge.

20. The wafer guide according to claim 8, wherein the pair of outer wafer supporting panel portions and the pair of inner wafer supporting panel portions are symmetrical around a wafer center area.