KR200147421Y1 - Lead on package - Google Patents

Lead on package Download PDF

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Publication number
KR200147421Y1
KR200147421Y1 KR2019930015493U KR930015493U KR200147421Y1 KR 200147421 Y1 KR200147421 Y1 KR 200147421Y1 KR 2019930015493 U KR2019930015493 U KR 2019930015493U KR 930015493 U KR930015493 U KR 930015493U KR 200147421 Y1 KR200147421 Y1 KR 200147421Y1
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KR
South Korea
Prior art keywords
lead
package
chip
adhesive layer
bonded
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KR2019930015493U
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Korean (ko)
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KR950007352U (en
Inventor
정관호
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김영환
현대전자산업주식회사
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Priority to KR2019930015493U priority Critical patent/KR200147421Y1/en
Publication of KR950007352U publication Critical patent/KR950007352U/en
Application granted granted Critical
Publication of KR200147421Y1 publication Critical patent/KR200147421Y1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 고안은 패키지 제작시 웨이퍼 상태에서 리드가 접착될 부위에 절연성 필름 코팅을 실시하고, 이 필름과 리드가 접착이 용이하도록 표면에 접착층을 제작한 리드 온 칩 패키지에 관한 것으로, 종래의 리드 온 칩 패키지는 패키지 제작시, 칩과 리드를 접착하기 위해 절연 테이프를 사용함으로써 제작 공정이 증가되고, 제작 공정의 증가로 다이 본더가 복잡하게 되어 패키지의 가격 상승및 생산성 저하의 원인이 되며, 또한 절연 테이프를 칩에 접착시 발생되는 내부 진공에 의해 신뢰성이 저하되는 문제점이 있었다.The present invention relates to a lead-on chip package in which an insulating film coating is applied to a portion to which a lead is bonded in a wafer state during fabrication of a package, and an adhesive layer is formed on the surface so that the film and the lead are easily bonded. In the case of the package, the manufacturing process is increased by using insulating tape to bond the chip and the lead to the package, and the increase of the manufacturing process increases the complexity of the die bonder, which leads to the increase in the price of the package and the decrease in productivity. There was a problem that the reliability is lowered by the internal vacuum generated when bonding to the chip.

본 고안은 이와같은 종래의 문제점을 감안하여, 리드 온 칩 패키지 제작시 웨이퍼 상태에서 리드가 접착될 부위에 절연성 필름 코팅을 실시하고, 이 필름과 리드가 접착이 용이하도록 표면에 접착층을 제작하여, 칩과 리드가 동시에 접착되도록 절연층 및 접착층을 제작함으로써 제작 공정을 단축시키고, 절연 테이프 접착에 의한 진공 발생을 방지하도록 한 것이다.In consideration of such a conventional problem, the present invention applies an insulating film coating to a portion to which a lead is bonded in a wafer state when manufacturing a lead-on chip package, and prepares an adhesive layer on the surface so that the film and the lead are easily bonded. By manufacturing the insulating layer and the adhesive layer to bond the chip and the lead at the same time to shorten the manufacturing process, it is to prevent the generation of vacuum by the adhesive tape.

Description

리드 온 칩 패키지Lead-on chip package

제1도는 종래 리드 온 칩 패키지의 단면도.1 is a cross-sectional view of a conventional lead-on chip package.

제2도는 제1도에 대한 요부 확대 단면도.2 is an enlarged cross-sectional view of the main portion of FIG.

제3도는 본 고안 리드 온 칩 패키지의 단면도.3 is a cross-sectional view of the lead-on chip package of the present invention.

제4도는 제3도에 대한 평면도.4 is a plan view of FIG.

제5도의 (a) 내지 (c)는 제3도에 대한 제작 공정도이다.(A)-(c) of FIG. 5 is a manufacturing process drawing about FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 웨이퍼 20 : 절연층10 wafer 20 insulation layer

30 : 본딩 패드 40 : 접착층30: bonding pad 40: adhesive layer

본 고안은 리드 온 칩 패키지에 관한 것으로, 특히 패키지 제작시 웨이퍼 상태에서 리드가 접착될 부위에 절연성 필름 코팅을 실시하고, 이 필름과 리드가 접착이 용이하도록 표면에 접착층을 제작한 리드 온 칩 패키지에 관한 것이다.The present invention relates to a lead-on chip package, and in particular, a lead-on chip package in which an insulating film is coated on a portion where a lead is to be bonded in a wafer state when the package is manufactured, and an adhesive layer is formed on the surface so that the film and the lead are easily bonded. It is about.

일반적으로 리드 온 칩 패키지(Lead On Chip Pakage 이하 LOC Package 라 칭함)는 칩에 리드를 절연 테이프를 사용하여 다이 어태치(Die Attach)하고, 칩의 패드와 내부 리드는 와이어로 와이어 본딩(Wire Bonding) 시킨 다음 몰딩 수지로 몰딩(Molding)하여 제작된다.In general, a lead on chip package (hereinafter referred to as LOC Package) is die attach to a chip using insulating tape, and the pad and the inner lead of the chip are wire bonded by wire. And then molded by molding resin (Molding).

이는 제1도와 같이 예시될 수 있는바, 칩(1)과 내부 리드(2)는 다이에 표현되는 절연 테이프(3)로 부착시킨 다음, 칩(1)의 패드(4)와 내부 리드(2)는 와이어(5)로 본딩하고 몰딩 수지(6)로 몰딩하여 제작된 것이다.This can be illustrated as shown in FIG. 1, in which the chip 1 and the inner lead 2 are attached with an insulating tape 3 represented on a die, and then the pad 4 and the inner lead 2 of the chip 1 are attached. ) Is manufactured by bonding with a wire (5) and molding with a molding resin (6).

이때 (7)은 칩(1)내의 각 회로에 전원을 직접 공급토록 공통적으로 사용되는 버스바로써, 내부 리드(2)와 칩(1)의 패드(4) 사이에 위치된다.At this time, (7) is a bus bar commonly used to directly supply power to each circuit in the chip (1), it is located between the internal lead (2) and the pad (4) of the chip (1).

상기 절연 테이프(3)는 제2도에 도시된 바와같이, 절연층(3-2)의 양면에 접착층(3-1,3-3)이 위치한 절연 테이프(3)를 다이싱(Dicing) 공정을 거친 칩(1)에 알맞게 커팅(Cutting)하여 접착층(3-1)을 이용하여 칩(1)과 1차 접착후, 절연층(3-2)위의 접착층(3-3)을 이용하여 2차로 내부 리드(2)와 접착시킨다.As shown in FIG. 2, the insulating tape 3 is subjected to a dicing process of the insulating tape 3 having the adhesive layers 3-1 and 3-3 on both sides of the insulating layer 3-2. After cutting to suit the chip 1 roughly, the first bonding with the chip 1 using the adhesive layer (3-1), using the adhesive layer (3-3) on the insulating layer (3-2) Secondly, it adheres to the inner lead 2.

이러한 구조의 리드 온 칩(LOC)패키지는 패키지를 소형화 할 수 있다는 장점때문에 그 사용이 급격히 증가되고 있다.The lead-on-chip (LOC) package of such a structure is rapidly increasing its use because of the small size of the package.

그러나 이와같은 종래의 리드 온 칩 패키지는, 패키지 제작시 칩과 리드를 접착하기 위해 절연 테이프를 사용함으로써 제작 공정이 증가되고, 제작 공정의 증가로 다이 본더가 복잡하게 되어 패키지의 가격 상승 및 생산성 저하의 원인이 되며, 또한 절연 테이프를 칩에 접착시 발생되는 내부 진공에 의해 신뢰성이 저하되는 문제점이 있었다.However, such a conventional lead-on-chip package has increased the manufacturing process by using insulating tape to bond the chip and the lead in the package fabrication, and the die bonder is complicated by the increase in the manufacturing process, which increases the price of the package and decreases productivity. In addition, there is a problem that the reliability is lowered by the internal vacuum generated when the insulating tape is bonded to the chip.

본 고안은 이와같은 종래의 문제점을 감안하여, 리드 온 칩 패키지 제작시 웨이퍼 상태에서 절연층 및 접착층을 제작함으로써 제작 공정을 단축시키고, 절연 테이프 접착에 의한 진공 발생을 방지함을 특징으로 한다.The present invention is characterized in that the manufacturing process is shortened by manufacturing the insulating layer and the adhesive layer in the wafer state in the manufacture of the lead-on chip package in order to prevent the generation of vacuum by the insulating tape adhesion.

즉, 웨이퍼 상태에서 리드가 접착될 부위에 절연성 필름 코팅을 실시하고, 이 필름과 리드가 접착이 용이하도록 표면에 접착층을 제작하여 칩과 리드가 동시에 접착되도록 한 것이다.That is, an insulating film coating is applied to a portion where the lead is to be bonded in the wafer state, and an adhesive layer is formed on the surface so that the film and the lead can be easily bonded so that the chip and the lead are simultaneously bonded.

이하 도면을 참조하여 상세히 설명하면 다음과 같다.When described in detail with reference to the drawings as follows.

본 고안 리드 온 칩 패키지는 제3도에 도시한 바와같이, 웨이퍼(10) 상의 본딩 패드(30)를 제외한 부위에 절연층(20)을 형성하고, 이 절연층(20) 상의 리드(도시하지 않음)가 부착될 부위에 접착층(40)을 형성하여 제작한 것으로, 이를 평면도로 도시하면 제4도와 같다.In the lead-on chip package of the present invention, as shown in FIG. 3, an insulating layer 20 is formed on a portion of the wafer 10 except for the bonding pads 30, and the lead on the insulating layer 20 (not shown). It is produced by forming an adhesive layer 40 on the portion to be attached), shown in Figure 4 as a plan view.

이와같은 구조의 본 고안 리드 온 칩 패키지를 제작하는 방법은 제5도에 도시한 바와같이, 회로가 완성된 웨이퍼(10)의 표면에 제5도의 (a)와 같이 코팅을 실시하여 절연층(20)을 제작 한 후, 와이어 본딩이 될 본딩 패드(30)는 제5도의 (b)와 같이 에칭(Ething)을 하여 본딩 패드(30)를 제작한다.The method for manufacturing the present invention lead-on-chip package having such a structure is as shown in FIG. 5, by coating the surface of the wafer 10 where the circuit is completed as shown in FIG. After fabricating 20), the bonding pad 30 to be wire bonded is etched as shown in FIG. 5 (b) to manufacture the bonding pad 30.

상기 절연층(20) 위에 제5도의 (c)와 같이 열경화성(Thermosetting) 또는 열가소성(Thermoplastic)계통의 접착층(40)을 형성한다.An adhesive layer 40 of a thermosetting or thermoplastic system is formed on the insulating layer 20 as shown in FIG. 5C.

이때 접착층(40)은 마스크(Mask)에 의한 방법이나 프린트(Print)에 의한 방법으로 형성할 수 있다.In this case, the adhesive layer 40 may be formed by a method using a mask or a method by printing.

이와같이 제작한 웨이퍼(10)를 정상적으로 다이싱하고, 픽-업(Pick-Up)장치를 사용하여 다이싱한 칩을 접착 위치에 이동하여 내부 리드와 일치시킨 후, 접착 위치에는 열이 작용하여 칩위의 접착층(40)이 내부 리드와 접착이 용이하도록 한다.The wafer 10 thus fabricated is normally diced, and the diced chip is moved to a bonding position using a pick-up device to match the internal lead, and then heat is applied to the bonding position. The adhesive layer 40 is to facilitate the adhesion with the inner lead.

따라서, 내부 리드와의 1차 접착만으로 접착이 완료된 칩을 와이어 본딩한 후 몰딩하여 패키지를 제작한다.Accordingly, the package is manufactured by wire-bonding and then molding a chip in which bonding is completed by only primary bonding with an inner lead.

이상에서 상세히 설명한 바와같이 본 고안은, 웨이퍼 상태에서 절연층 및 접착층을 형성함으로써, 절연 테이프 사용시 요구되는 테이프 커팅 및 테이프접착 공정을 생략하여 제작 공정을 단축 시킬 수 있고, 제작 공정의 단축으로 장비 및 시간 소모를 방지하여 생산성을 향상 시킬 수 있으며, 접착 테이프 배치 또는 칩의 배치에 의한 손실을 방지할 수 있어 수율을 향상 시킬 수 있는 효과가 있다.As described in detail above, the present invention, by forming the insulating layer and the adhesive layer in the wafer state, it is possible to shorten the manufacturing process by eliminating the tape cutting and tape bonding process required when using the insulating tape, equipment and by shortening the manufacturing process Productivity can be improved by preventing time wastage, and loss by adhesive tape arrangement or chip placement can be prevented, thereby improving yield.

Claims (3)

웨이퍼(10) 상의 본딩 패드(30)를 제외한 부위에 절연층(20)을 형성하고, 이 절연층(20) 상의 리드(도시하지 않음)가 부착될 부위에 접착층(40)을 형성하여 제작함을 특징으로 하는 리드 온 칩 패키지.Insulating layer 20 is formed on a portion of the wafer 10 except for the bonding pads 30, and an adhesive layer 40 is formed on a portion to which a lead (not shown) on the insulating layer 20 is to be attached. Lead-on chip package, characterized in that. 제1항에 있어서, 상기 절연층(20)은 회로가 완성된 웨이퍼(10)의 표면에 코팅을 실시하여 제작 한 후, 에칭(Ething)을 하여 와이어 본딩이 될 본딩 패드(30)를 형성하여 제작함을 특징으로 하는 리드 온 칩 패키지.The method of claim 1, wherein the insulating layer 20 is formed by coating a surface of the wafer 10 on which a circuit is completed and then etching to form a bonding pad 30 to be wire bonded. Lead-on chip package characterized by fabrication. 제1항에 있어서, 상기 접착층(40)은 절연층(20) 위에 마스크(Mask)에 의한 방법이나 프린트(Print)에 의한 방법으로 열경화성(Thermosetting) 또는 열가소성(Thermoplastic) 계통의 접착층(40)을 형성하여 제작함을 특징으로 하는 리드 온 칩 패키지.2. The adhesive layer 40 of claim 1, wherein the adhesive layer 40 is formed on the insulating layer 20 by a mask or a method of printing. The adhesive layer 40 is formed of a thermosetting or thermoplastic resin. Lead-on chip package, characterized in that the forming.
KR2019930015493U 1993-08-12 1993-08-12 Lead on package KR200147421Y1 (en)

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KR2019930015493U KR200147421Y1 (en) 1993-08-12 1993-08-12 Lead on package

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KR2019930015493U KR200147421Y1 (en) 1993-08-12 1993-08-12 Lead on package

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KR950007352U KR950007352U (en) 1995-03-21
KR200147421Y1 true KR200147421Y1 (en) 1999-06-15

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