KR20010099590A - 이산화실리콘층 형성방법과 트렌치 분리지역 형성방법 - Google Patents
이산화실리콘층 형성방법과 트렌치 분리지역 형성방법 Download PDFInfo
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- KR20010099590A KR20010099590A KR1020017000435A KR20017000435A KR20010099590A KR 20010099590 A KR20010099590 A KR 20010099590A KR 1020017000435 A KR1020017000435 A KR 1020017000435A KR 20017000435 A KR20017000435 A KR 20017000435A KR 20010099590 A KR20010099590 A KR 20010099590A
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- silicon dioxide
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 title claims abstract description 212
- 235000012239 silicon dioxide Nutrition 0.000 title claims abstract description 106
- 239000000377 silicon dioxide Substances 0.000 title claims abstract description 106
- 238000000034 method Methods 0.000 title claims abstract description 56
- 238000002955 isolation Methods 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims abstract description 76
- 230000008021 deposition Effects 0.000 claims abstract description 56
- 238000005530 etching Methods 0.000 claims abstract description 31
- 239000002243 precursor Substances 0.000 claims abstract description 11
- 239000003507 refrigerant Substances 0.000 claims abstract description 3
- 238000000151 deposition Methods 0.000 claims abstract 53
- 238000001816 cooling Methods 0.000 claims abstract 2
- 239000007789 gas Substances 0.000 claims description 46
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 15
- 239000001301 oxygen Substances 0.000 claims description 15
- 229910052760 oxygen Inorganic materials 0.000 claims description 15
- 238000010438 heat treatment Methods 0.000 claims description 5
- 230000006698 induction Effects 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000000112 cooling gas Substances 0.000 claims 1
- 239000000203 mixture Substances 0.000 claims 1
- 238000001020 plasma etching Methods 0.000 claims 1
- 230000003252 repetitive effect Effects 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 42
- 239000004065 semiconductor Substances 0.000 description 17
- 238000005137 deposition process Methods 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000000926 separation method Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
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- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/04—Coating on selected surface areas, e.g. using masks
- C23C16/045—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/40—Oxides
- C23C16/401—Oxides containing silicon
- C23C16/402—Silicon dioxide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31608—Deposition of SiO2
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- Formation Of Insulating Films (AREA)
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Abstract
Description
Claims (40)
- 기판 근처에서 고밀도 플라즈마를 형성시키고;가스를 플라즈마 속으로 흐르게하고 가스중 적어도 일부가 이산화실리콘을 형성하게 하며;가스로부터 형성된 이산화실리콘을 기판위에 침적시키고;이산화실리콘 침적동안 기판의 온도를 500℃이상으로 유지시키는 단계를 포함하는 이산화실리콘층 형성방법.
- 제 1 항에 있어서, 기판에 구멍을 형성하고;구멍내에 이산화실리콘을 침적시키는 단계를 더욱 포함하는 방법.
- 제 1 항에 있어서, 가스가 SiH4와 산소를 포함함을 특징으로 하는 방법.
- 제 1 항에 있어서, 가스가 SiH4와, 산소 및 Ar을 포함함을 특징으로 하는 방법.
- 기판 근처에서 고밀도 플라즈마를 형성시키고;가스를 플라즈마 속으로 흐르게하고 가스중 적어도 일부가 이산화실리콘을형성하게 하며;가스로부터 형성된 이산화실리콘을 기판위에 침적시키고;이산화실리콘 침적동안 기판을 냉매가스로 냉각시키지 않은 단계를 포함하는 이산화실리콘 형성방법.
- 제 5 항에 있어서, 침적동안 기판의 온도를 500℃이상으로 유지시키는 단계를 더욱 포함하는 방법.
- 기판 근처에서 고밀도 플라즈마를 형성시키고;가스를 플라즈마 속으로 흐르게하고 가스중 적어도 일부가 이산화실리콘을 형성하게 하며;한 침적속도에서 기판위에 가스로부터 형성된 이산화실리콘을 침적시키고;침적동안 한 엣칭속도에서 플라즈마로 침적된 이산화실리콘을 엣칭하고;엣칭 및 침적동안 기판의 온도를 500℃이상으로 유지시키는 단계를 포함하는 이산화실리콘층 형성방법.
- 제 7 항에 있어서, 가스가 SiH4와 산소를 포함함을 특징으로 하는 방법.
- 제 7 항에 있어서, 가스가 SiH4와, 산소 및 Ar을 포함함을 특징으로 하는 방법.
- 제 7 항에 있어서, 기판에 구멍을 형성하고;구멍내에 이산화실리콘을 침적시키는 단계를 더욱 포함하는 방법.
- 기판 근처에서 고밀도 플라즈마를 형성시키고;가스를 플라즈마 속으로 흐르게하고 가스중 적어도 일부가 이산화실리콘을 형성하게 하며;한 침적속도에서 기판위에 가스로부터 형성된 이산화실리콘을 침적시키고;침적동안 한 엣칭속도에서 플라즈마로 침적된 이산화실리콘을 엣칭하고;엣칭 및 침적동안 기판의 온도를 500℃이상으로 유지시키고, 온도 유지 단계는 기판을 냉각가스에 노출시키지 않는 이산화실리콘 형성방법.
- 기판 근처에서 고밀도 플라즈마를 형성하고;플라즈마 속으로 가스를 흐르게 하고 가스중 적어도 일부가 이산화실리콘을 형성하게 하며;한 침적 속도에서 가스로부터 형성된 이산화실리콘을 기판위에 침적시키고;침적동안 더 낮은 온도 조건에서 동일한 기판의 동일한 처리조건하에서 이루어지는 것보다 2배 이상의 침적속도:엣칭속도 비율을 달성시키는 승온 조건하에서 한 엣칭속도로 플라즈마를 써서 침적된 이산화실리콘을 엣칭하는 단계를 포함하는이산화실리콘층 형성방법.
- 기판속으로 1마이크론 미만으로 연장되는 구멍을 형성하고;산소의 조건하에서 기판을 가열하여 구멍내에 제 1 이산화실리콘층을 형성하고;구멍내에 제 2 이산화실리콘층을 형성하여 구멍을 채우고 제 2 이산화실리콘층 형성단계는 다음 단계를 포함하며:기판 근처에 고밀도 플라즈마를 형성하고 플라즈마속으로 가스를 흐르게 하고 가스중 적어도 일부가 이산화실리콘을 형성하게 하며;기판을 500℃이상의 온도로 유지시키며;상기 온도에서 기판을 유지하는 동안 가스로부터 형성된 이산화실리콘이 구멍내에 침적되는 단계를 포함하는 얕은 트렌치 분리영역 형성방법.
- 제 13 항에 있어서, 가스가 SiH4와 산소를 포함함을 특징으로 하는 방법.
- 제 13 항에 있어서, 기판 온도 유지단계가 기판을 플라즈마로 가열하는 과정을 포함함을 특징으로 하는 방법.
- 제 13 항에 있어서, 한 침적속도에서 이산화실리콘이 침적되며 침적속도:엣칭속도 비율이 4:1 이상이 되도록하는 엣칭속도에서 플라즈마로 침적된 이산화실리콘을 엣칭하는 단계를 더욱 포함하는 방법.
- 제 13 항에 있어서, 침적속도:엣칭속도의 비율이 6:1 이상임을 특징으로 하는 방법.
- 제 13 항에 있어서, 침적속도:엣칭속도의 비율이 9:1 이상임을 특징으로 하는 방법.
- 1이상의 가로세로비를 갖는 구멍을 포함하는 기판 근처에서 이산화실리콘 선구물질을 포함하는 고밀도 플라즈마를 형성시키고;선구물질로부터 이산화실리콘을 형성하고 이산화실리콘이 한 침적속도에서 구멍내에 침적되고;침적동안 침적속도:엣칭속도의 비율이 4:1 이상이 되게하는 엣칭속도에서 플라즈마로 구멍내에 침적된 이산화실리콘을 엣칭하는 단계를 포함하는 이산화실리콘층 형성방법.
- 제 19 항에 있어서, 구멍이 2.5 내지 1의 가로세로비를 가짐을 특징으로 하는 방법.
- 제 19 항에 있어서, 플라즈마를 발생시키는 유도코일을 포함하는 반응챔버에 기판을 배치하고 반응 챔버에서 침적 및 엣칭이 일어나며;유도 코일에 제 1 바이어스를 제공하고;엣칭동안 기판에 제 2 바이어스를 제공하는 단계를 더욱 포함하는 방법.
- 1이상의 가로세로비를 갖는 구멍을 포함한 기판 근처에서 고밀도 플라즈마를 형성시키고;플라즈마 속으로 가스를 흐르게 하고 가스중 적어도 일부가 이산화실리콘을 형성하게 하며;한 침적속도에서 구멍내에 가스로부터 형성된 이산화실리콘을 침적시키고;침적동안 침적속도:엣칭속도 비율이 4:1 이상이 되게하는 엣칭속도에서 플라즈마는 구멍내에 침적된 이산화실리콘을 엣칭하는 단계를 포함하는 이산화실리콘 형성방법.
- 제 22 항에 있어서, 구멍이 2.5 내지 1 의 가로세로비를 가짐을 특징으로 하는 방법.
- 제 22 항에 있어서, 침적속도:엣칭속도의 비율이 6:1 이상임을 특징으로 하는 방법.
- 제 22 항에 있어서, 침적속도:엣칭속도의 비율이 9:1 이상임을 특징으로 하는 방법.
- 제 22 항에 있어서, 침적 및 엣칭동안 기판온도를 500℃이상으로 유지시키는 단계를 더욱 포함하는 방법.
- 제 22 항에 있어서, 기판에 구멍을 형성하고;구멍내에 이산화실리콘을 침적시키는 단계를 더욱 포함하는 방법.
- 제 22 항에 있어서, 가스가 SiH4와 산소를 포함함을 특징으로 하는 방법.
- 제 22 항에 있어서, 가스가 SiH4와, 산소 및 Ar을 포함함을 특징으로 하는 방법.
- 제 22 항에 있어서, 가스가 SiH4, 산소 및 Ar으로 구성된 혼합물임을 특징으로 하는 방법.
- 스텝을 포함한 기판 근처에서 고밀도 플라즈마를 형성하고;플라즈마 속으로 가스를 흐르게 하며 가스중 적어도 일부가 이산화실리콘을형성하게 하며;기판 스텝위에 가스로부터 형성된 이산화실리콘을 침적시키고;이산화실리콘 침적동안 기판 온도를 500℃이상으로 유지함으로써 더 낮은 온도의 경우보다 더 양호한 스텝 피복을 달성하는 침적이 이루어짐을 특징으로 하는 이산화실리콘층 형성방법.
- 제 31 항에 있어서, 기판에 구멍을 형성하고;구멍내에 이산화실리콘을 침적시키는 단계를 더욱 포함하는 방법.
- 제 31 항에 있어서, 가스가 SiH4와 산소를 포함함을 특징으로 하는 방법.
- 제 31 항에 있어서, 가스가 SiH4와, 산소 및 Ar을 포함함을 특징으로 하는 방법.
- 구멍주변에 스텝(step)을 포함하는 기판속으로 1마이크론 미만으로 연장되는 구멍을 형성하고;산소의 조건하에서 기판을 가열하여 구멍내에 제 1 이산화실리콘층을 형성하고;구멍내에 제 2 이산화실리콘층을 형성하여 구멍을 채우고 제 2 이산화실리콘층 형성단계는 다음 단계를 포함하며:기판 근처에 고밀도 플라즈마를 형성하고 플라즈마속으로 가스를 흐르게 하고 가스중 적어도 일부가 이산화실리콘을 형성하게 하며;기판을 500℃이상의 온도로 유지시키며;상기 온도에서 기판을 유지하는 동안 가스로부터 형성된 이산화실리콘이 구멍내에 스텝위로 침적되는 단계를 포함하여 더 낮은 온도의 경우보다 더 양호한 스텝 되풀이된 침적이 이루어짐을 특징으로 하는 얕은 트렌치 분리영역 형성방법.
- 제 35 항에 있어서, 가스가 SiH4와 산소를 포함함을 특징으로 하는 방법.
- 제 35 항에 있어서, 기판 온도 유지단계가 기판을 플라즈마로 가열하는 과정을 포함함을 특징으로 하는 방법.
- 제 35 항에 있어서, 한 침적속도에서 이산화실리콘이 침적되며 침적속도:엣칭속도 비율이 4:1 이상이 되도록하는 엣칭속도에서 플라즈마로 침적된 이산화실리콘을 엣칭하는 단계를 더욱 포함하는 방법.
- 제 35 항에 있어서, 침적속도:엣칭속도의 비율이 6:1 이상임을 특징으로 하는 방법.
- 제 35 항에 있어서, 침적속도:엣칭속도의 비율이 9:1 이상임을 특징으로 하는 방법.
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US09/113,467 US6759306B1 (en) | 1998-07-10 | 1998-07-10 | Methods of forming silicon dioxide layers and methods of forming trench isolation regions |
US09/113,467 | 1998-07-10 |
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Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6759306B1 (en) * | 1998-07-10 | 2004-07-06 | Micron Technology, Inc. | Methods of forming silicon dioxide layers and methods of forming trench isolation regions |
US6319796B1 (en) * | 1999-08-18 | 2001-11-20 | Vlsi Technology, Inc. | Manufacture of an integrated circuit isolation structure |
DE10220695A1 (de) * | 2002-05-10 | 2003-11-27 | Alplas Gmbh | Vorrichtung zum Entfernen von Sauerstoff aus Getränkebehältern |
US8158488B2 (en) * | 2004-08-31 | 2012-04-17 | Micron Technology, Inc. | Method of increasing deposition rate of silicon dioxide on a catalyst |
TW200633121A (en) * | 2005-03-03 | 2006-09-16 | Powerchip Semiconductor Corp | Method for manufacturing shallow trench isolation structure |
US7268057B2 (en) * | 2005-03-30 | 2007-09-11 | Micron Technology, Inc. | Methods of filling openings with oxide, and methods of forming trenched isolation regions |
US8021992B2 (en) * | 2005-09-01 | 2011-09-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | High aspect ratio gap fill application using high density plasma chemical vapor deposition |
US7737526B2 (en) * | 2007-03-28 | 2010-06-15 | Advanced Analogic Technologies, Inc. | Isolated trench MOSFET in epi-less semiconductor sustrate |
WO2009006272A1 (en) | 2007-06-28 | 2009-01-08 | Advanced Technology Materials, Inc. | Precursors for silicon dioxide gap fill |
Family Cites Families (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63234534A (ja) | 1987-03-24 | 1988-09-29 | Oki Electric Ind Co Ltd | 半導体素子の製造方法 |
US5270759A (en) * | 1989-11-15 | 1993-12-14 | Asahi Kogaku Kogyo Kabushiki Kaisha | Apparatus for stopping down diaphragm to an intermediate setting, upon setting diaphragm to a desired setting |
US5270264A (en) * | 1991-12-20 | 1993-12-14 | Intel Corporation | Process for filling submicron spaces with dielectric |
US5180490A (en) | 1992-01-31 | 1993-01-19 | Baldwin Filters, Inc. | Lubricant filter assembly with internal bypass lock-out |
US5531834A (en) | 1993-07-13 | 1996-07-02 | Tokyo Electron Kabushiki Kaisha | Plasma film forming method and apparatus and plasma processing apparatus |
US5614055A (en) * | 1993-08-27 | 1997-03-25 | Applied Materials, Inc. | High density plasma CVD and etching reactor |
JPH0776777A (ja) | 1993-09-08 | 1995-03-20 | Nissin Electric Co Ltd | 酸化シリコン膜形成方法及び装置 |
JPH088232A (ja) | 1994-06-22 | 1996-01-12 | Sony Corp | プラズマ処理方法 |
US5447884A (en) | 1994-06-29 | 1995-09-05 | International Business Machines Corporation | Shallow trench isolation with thin nitride liner |
JP3326974B2 (ja) | 1994-07-28 | 2002-09-24 | ソニー株式会社 | 多層配線の形成方法および半導体装置の製造方法 |
US5494854A (en) * | 1994-08-17 | 1996-02-27 | Texas Instruments Incorporated | Enhancement in throughput and planarity during CMP using a dielectric stack containing HDP-SiO2 films |
US5962923A (en) | 1995-08-07 | 1999-10-05 | Applied Materials, Inc. | Semiconductor device having a low thermal budget metal filling and planarization of contacts, vias and trenches |
JP3979687B2 (ja) * | 1995-10-26 | 2007-09-19 | アプライド マテリアルズ インコーポレイテッド | ハロゲンをドープした酸化珪素膜の膜安定性を改良する方法 |
DE69623651T2 (de) | 1995-12-27 | 2003-04-24 | Lam Research Corp., Fremont | Verfahren zur füllung von gräben auf einer halbleiterscheibe |
US5679606A (en) * | 1995-12-27 | 1997-10-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | method of forming inter-metal-dielectric structure |
US5976993A (en) * | 1996-03-28 | 1999-11-02 | Applied Materials, Inc. | Method for reducing the intrinsic stress of high density plasma films |
US5660895A (en) | 1996-04-24 | 1997-08-26 | Board Of Supervisors Of Louisiana State University And Agricultural And Mechanical College | Low-temperature plasma-enhanced chemical vapor deposition of silicon oxide films and fluorinated silicon oxide films using disilane as a silicon precursor |
JP4195734B2 (ja) * | 1996-06-10 | 2008-12-10 | テキサス インスツルメンツ インコーポレイテツド | 集積回路のトレンチ分離製作方法 |
US6444037B1 (en) * | 1996-11-13 | 2002-09-03 | Applied Materials, Inc. | Chamber liner for high temperature processing chamber |
US6114216A (en) | 1996-11-13 | 2000-09-05 | Applied Materials, Inc. | Methods for shallow trench isolation |
US5763315A (en) | 1997-01-28 | 1998-06-09 | International Business Machines Corporation | Shallow trench isolation with oxide-nitride/oxynitride liner |
US6013584A (en) * | 1997-02-19 | 2000-01-11 | Applied Materials, Inc. | Methods and apparatus for forming HDP-CVD PSG film used for advanced pre-metal dielectric layer applications |
US5968610A (en) * | 1997-04-02 | 1999-10-19 | United Microelectronics Corp. | Multi-step high density plasma chemical vapor deposition process |
DE69824368T2 (de) * | 1997-04-07 | 2005-06-16 | Koninklijke Philips Electronics N.V. | Herstellungsverfahren einer halbleitervorrichtung mit flacher grabenisolation |
US5726090A (en) | 1997-05-01 | 1998-03-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gap-filling of O3 -TEOS for shallow trench isolation |
US6077786A (en) | 1997-05-08 | 2000-06-20 | International Business Machines Corporation | Methods and apparatus for filling high aspect ratio structures with silicate glass |
US5731241A (en) | 1997-05-15 | 1998-03-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned sacrificial oxide for shallow trench isolation |
US6286451B1 (en) * | 1997-05-29 | 2001-09-11 | Applied Materials, Inc. | Dome: shape and temperature controlled surfaces |
US6136685A (en) * | 1997-06-03 | 2000-10-24 | Applied Materials, Inc. | High deposition rate recipe for low dielectric constant films |
US5872058A (en) * | 1997-06-17 | 1999-02-16 | Novellus Systems, Inc. | High aspect ratio gapfill process by using HDP |
US6110544A (en) * | 1997-06-26 | 2000-08-29 | General Electric Company | Protective coating by high rate arc plasma deposition |
JP3141827B2 (ja) | 1997-11-20 | 2001-03-07 | 日本電気株式会社 | 半導体装置の製造方法 |
US6015759A (en) * | 1997-12-08 | 2000-01-18 | Quester Technology, Inc. | Surface modification of semiconductors using electromagnetic radiation |
US6340435B1 (en) * | 1998-02-11 | 2002-01-22 | Applied Materials, Inc. | Integrated low K dielectrics and etch stops |
US6228775B1 (en) * | 1998-02-24 | 2001-05-08 | Micron Technology, Inc. | Plasma etching method using low ionization potential gas |
US6194038B1 (en) | 1998-03-20 | 2001-02-27 | Applied Materials, Inc. | Method for deposition of a conformal layer on a substrate |
US5945724A (en) | 1998-04-09 | 1999-08-31 | Micron Technology, Inc. | Trench isolation region for semiconductor device |
US6165854A (en) | 1998-05-04 | 2000-12-26 | Texas Instruments - Acer Incorporated | Method to form shallow trench isolation with an oxynitride buffer layer |
US6030881A (en) * | 1998-05-05 | 2000-02-29 | Novellus Systems, Inc. | High throughput chemical vapor deposition process capable of filling high aspect ratio structures |
US6593241B1 (en) * | 1998-05-11 | 2003-07-15 | Applied Materials Inc. | Method of planarizing a semiconductor device using a high density plasma system |
US6153509A (en) | 1998-07-01 | 2000-11-28 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device |
US6759306B1 (en) * | 1998-07-10 | 2004-07-06 | Micron Technology, Inc. | Methods of forming silicon dioxide layers and methods of forming trench isolation regions |
US6255211B1 (en) | 1998-10-02 | 2001-07-03 | Texas Instruments Incorporated | Silicon carbide stop layer in chemical mechanical polishing over metallization layers |
US6140208A (en) | 1999-02-05 | 2000-10-31 | International Business Machines Corporation | Shallow trench isolation (STI) with bilayer of oxide-nitride for VLSI applications |
US6180490B1 (en) * | 1999-05-25 | 2001-01-30 | Chartered Semiconductor Manufacturing Ltd. | Method of filling shallow trenches |
-
1998
- 1998-07-10 US US09/113,467 patent/US6759306B1/en not_active Expired - Lifetime
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- 1999-07-09 KR KR10-2001-7000435A patent/KR100420848B1/ko not_active IP Right Cessation
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JP3527474B2 (ja) | 2004-05-17 |
US6759306B1 (en) | 2004-07-06 |
US7211499B2 (en) | 2007-05-01 |
JP2002520852A (ja) | 2002-07-09 |
KR100420848B1 (ko) | 2004-03-02 |
US20060205175A1 (en) | 2006-09-14 |
WO2000003430A1 (en) | 2000-01-20 |
US6737328B1 (en) | 2004-05-18 |
US20040180558A1 (en) | 2004-09-16 |
US7018908B2 (en) | 2006-03-28 |
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