KR20010082903A - Method for fabricating of semiconductor device - Google Patents
Method for fabricating of semiconductor device Download PDFInfo
- Publication number
- KR20010082903A KR20010082903A KR1020000008440A KR20000008440A KR20010082903A KR 20010082903 A KR20010082903 A KR 20010082903A KR 1020000008440 A KR1020000008440 A KR 1020000008440A KR 20000008440 A KR20000008440 A KR 20000008440A KR 20010082903 A KR20010082903 A KR 20010082903A
- Authority
- KR
- South Korea
- Prior art keywords
- metal layer
- insulating film
- etching
- gate
- semiconductor device
- Prior art date
Links
Classifications
-
- E—FIXED CONSTRUCTIONS
- E02—HYDRAULIC ENGINEERING; FOUNDATIONS; SOIL SHIFTING
- E02B—HYDRAULIC ENGINEERING
- E02B8/00—Details of barrages or weirs ; Energy dissipating devices carried by lock or dry-dock gates
- E02B8/08—Fish passes or other means providing for migration of fish; Passages for rafts or boats
-
- E—FIXED CONSTRUCTIONS
- E02—HYDRAULIC ENGINEERING; FOUNDATIONS; SOIL SHIFTING
- E02B—HYDRAULIC ENGINEERING
- E02B5/00—Artificial water canals, e.g. irrigation canals
- E02B5/02—Making or lining canals
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Mechanical Engineering (AREA)
- Civil Engineering (AREA)
- Structural Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체소자에 대한 것으로, 특히 게이트전극의 저항을 줄일 수 있는 반도체소자의 제조방법에 관한 것이다.The present invention relates to a semiconductor device, and more particularly to a method for manufacturing a semiconductor device that can reduce the resistance of the gate electrode.
이하, 첨부 도면을 참조하여 종래 반도체소자의 제조방법에 대하여 설명하면 다음과 같다.Hereinafter, a manufacturing method of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a와 도 1b는 종래 제 1 방법에 의한 반도체소자의 제조방법을 나타낸 공정단면도이고, 도 2a 내지 도 2c는 종래 제 2 방법에 의한 반도체소자의 제조방법을 나타낸 공정단면도이다.1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a first method, and FIGS. 2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a second method.
종래 제 1 방법에 따른 반도체소자의 제조방법은 도 1a에 도시한 바와 같이 반도체기판(1)에 게이트산화막(2)과 폴리실리콘층(3)과 베리어메탈층(4)을 차례로 증착하고, 베리어메탈층(4)상에 저항이 낮은 메탈층(5)을 증착한다.In the conventional method of manufacturing a semiconductor device according to the first method, as shown in FIG. 1A, a gate oxide film 2, a polysilicon layer 3, and a barrier metal layer 4 are sequentially deposited on a semiconductor substrate 1, and a barrier is used. A low resistance metal layer 5 is deposited on the metal layer 4.
이후에 메탈층(5)상에 추후에 캡절연막을 형성하기 위한 산화막이나 질화막으로 절연막(6)을 증착한다.Thereafter, the insulating film 6 is deposited on the metal layer 5 by an oxide film or a nitride film for forming a cap insulating film later.
그리고 도면에는 도시되지 않았지만 절연막(6)상에 감광막을 도포하고 게이트 형성 부분만 남도록 노광 및 현상하여서 감광막을 선택적으로 패터닝한다.Although not shown in the figure, a photosensitive film is coated on the insulating film 6, and the photosensitive film is selectively patterned by exposing and developing so that only the gate forming portion remains.
이후에 패터닝된 감광막을 마스크로 도 1b에 도시한 바와 같이 절연막(6)을 이방성 식각해서 캡절연막(6a)을 형성하고, 다음에 감광막을 제거하고 세정한다.Subsequently, as shown in FIG. 1B using the patterned photosensitive film as a mask, the insulating film 6 is anisotropically etched to form a cap insulating film 6a, and then the photosensitive film is removed and cleaned.
다음에 캡절연막(6a)을 마스크로 메탈층(5)과 베리어메탈층(4)과 폴리실리콘층(3)을 차례로 이방성 식각해서 게이트전극을 형성한다.Next, the gate electrode is formed by anisotropically etching the metal layer 5, the barrier metal layer 4, and the polysilicon layer 3 with the cap insulating film 6a as a mask.
여기서 상기의 캡절연막(6a)은 형성하지 않아도 되는데 형성하지 않을 경우에는 메탈층(5)상에 감광막을 패터닝한 후에 패터닝된 감광막을 마스크로 메탈층(5)과 베리어메탈층(4)과 폴리실리콘층(3)을 차례로 식각해서 게이트전극을 형성한다.In this case, the cap insulating film 6a is not required to be formed. When the cap insulating film 6a is not formed, the photosensitive film is patterned on the metal layer 5 and then the metal layer 5, the barrier metal layer 4 and the poly are patterned using the patterned photosensitive film. The silicon layer 3 is sequentially etched to form a gate electrode.
다음에 종래 제 2 방법에 따른 반도체소자의 제조방법은 도 2a에 도시한 바와 같이 반도체기판(11)에 게이트산화막(12)을 형성한 후에 게이트산화막(12)상에 폴리실리콘층을 증착한다. 이후에 사진식각공정으로 게이트형성 영역에만 남도록 폴리실리콘층을 이방성 식각해서 폴리게이트(13)을 패턴형성한다.Next, in the method of manufacturing a semiconductor device according to the second method, a polysilicon layer is deposited on the gate oxide film 12 after the gate oxide film 12 is formed on the semiconductor substrate 11 as shown in FIG. 2A. Thereafter, the polysilicon layer is anisotropically etched so that only the gate forming region remains in the photolithography process, thereby forming the polygate 13.
이후에 폴리게이트(13)를 포함한 반도체기판(11)상에 절연막을 증착한 후에 폴리게이트(13) 양측의 반도체기판(11)상에만 남도록 이방성 식각해서 측벽절연막(14)을 형성한다.Thereafter, after the insulating film is deposited on the semiconductor substrate 11 including the polygate 13, the sidewall insulating film 14 is formed by anisotropic etching so as to remain only on the semiconductor substrate 11 on both sides of the polygate 13.
그리고 도 2b에 도시한 바와 같이 폴리게이트(13)를 제거하여서 게이트산화막(12)이 드러나도록 한다.As shown in FIG. 2B, the gate oxide layer 12 is exposed by removing the polygate 13.
이후에 도 2c에 도시한 바와 같이 전면에 메탈층을 증착한 후에 드러난 게이트산화막(12)상에 측벽절연막(14)과 동일높이로 형성되도록 식각이나 연마공정을 진행하여 게이트전극(15)을 형성한다.Subsequently, as shown in FIG. 2C, the gate electrode 15 is formed by performing an etching or polishing process to form the same height as the sidewall insulating layer 14 on the gate oxide layer 12 exposed after the metal layer is deposited on the entire surface. do.
상기와 같은 종래 반도체소자의 제조방법은 다음과 같은 문제가 있다.The conventional method of manufacturing a semiconductor device as described above has the following problems.
첫째, 게이트산화막상에 폴리실리콘층을 직접증착할 경우에 수직 프로파일을 이루도록 식각하기가 어렵고, 게이트산화막에 식각데미지가 발생할 우려가 있고 게이트저항을 낮추는데 한계가 있다.First, when the polysilicon layer is directly deposited on the gate oxide layer, it is difficult to etch to form a vertical profile, and there is a risk of etching damage on the gate oxide layer and a limitation in lowering the gate resistance.
둘째, 폴리게이트를 형성한 후에 제거하고 그 부분에 메탈게이트를 형성하는 공정은 게이트형성을 위한 식각과 제거공정을 각각 두 번 진행하여야 하므로 공정이 복잡하다.Second, the process of removing the polygate after forming the metal gate and forming the metal gate in the portion thereof is complicated because the etching and the removing process for forming the gate must be performed twice.
본 발명은 상기와 같은 문제를 해결하기 위하여 안출한 것으로 특히, 공정을 단순화 시키면서 게이트의 저항을 줄이기에 알맞은 반도체소자의 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and in particular, an object of the present invention is to provide a method for manufacturing a semiconductor device suitable for reducing the resistance of the gate while simplifying the process.
도 1a와 도 1b는 종래 제 1 방법에 의한 반도체소자의 제조방법을 나타낸 공정단면도1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a first method.
도 2a 내지 도 2c는 종래 제 2 방법에 의한 반도체소자의 제조방법을 나타낸 공정단면도2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a conventional second method.
도 3a와 도 3b는 본 발명의 실시예에 따른 반도체소자의 제조방법을 나타낸 공정단면도3A and 3B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
31 : 반도체기판 32 : 게이트산화막31 semiconductor substrate 32 gate oxide film
33 : 제 1 메탈층 34 : 베리어메탈층33: first metal layer 34: barrier metal layer
35 : 제 2 메탈층 36 : 절연막35 second metal layer 36 insulating film
36a : 캡절연막36a: cap insulation film
상기와 같은 목적을 달성하기 위한 본 발명 반도체소자의 제조방법은 반도체기판에 게이트절연막을 형성하는 공정, 상기 게이트절연막상에 제 1, 제 2 메탈층을 차례로 형성하는 공정, 상기 제 2 메탈층상에 절연막을 형성하는 공정, 상기 절연막을 식각하여 게이트 형성 부분 상측의 상기 제 2 메탈층상에 캡절연막을 형성하는 공정, 상기 캡절연막을 마스크로 상기 제 2 메탈층과 제 1 메탈층을 차례로 식각하여 게이트전극을 형성하는 공정을 포함함을 특징으로 한다.A method of manufacturing a semiconductor device according to the present invention for achieving the above object is a step of forming a gate insulating film on a semiconductor substrate, a step of sequentially forming a first, a second metal layer on the gate insulating film, on the second metal layer Forming an insulating film; etching the insulating film to form a cap insulating film on the second metal layer above the gate forming portion; and etching the second metal layer and the first metal layer in sequence using the cap insulating film as a mask. It characterized in that it comprises a step of forming an electrode.
이하, 첨부 도면을 참조하여 본 발명 반도체소자의 제조방법에 대하여 설명하면 다음과 같다.Hereinafter, a manufacturing method of a semiconductor device of the present invention will be described with reference to the accompanying drawings.
도 3a와 도 3b는 본 발명의 실시예에 따른 반도체소자의 제조방법을 나타낸 공정단면도이다.3A and 3B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
본 발명 반도체소자의 제조방법은 도 3a에 도시한 바와 같이 반도체기판(31)에 열산화나 화학기상증착법으로 게이트산화막(32)을 형성한다.In the method of manufacturing the semiconductor device of the present invention, as shown in FIG. 3A, the gate oxide film 32 is formed on the semiconductor substrate 31 by thermal oxidation or chemical vapor deposition.
이후에 게이트산화막(32)상에 티타늄/티타늄 나이트라이드(Ti/TiN)로 구성된 제 1 메탈층(33)을 증착하고, 제 1 메탈층(33)에 베리어메탈층(34)을 증착한다. 이때 베리어메탈층(34)은 증착하지 않아도 된다.Thereafter, a first metal layer 33 composed of titanium / titanium nitride (Ti / TiN) is deposited on the gate oxide layer 32, and a barrier metal layer 34 is deposited on the first metal layer 33. At this time, the barrier metal layer 34 does not have to be deposited.
그리고 상기 베리어메탈층(34)상에 텅스텐으로 구성된 제 2 메탈층(35)을 증착한다.The second metal layer 35 made of tungsten is deposited on the barrier metal layer 34.
이후에 제 2 메탈층(35)상에 화학기상증착법으로 산화막이나 질화막으로 구성된절연막(36)을 증착한다.Thereafter, an insulating film 36 composed of an oxide film or a nitride film is deposited on the second metal layer 35 by chemical vapor deposition.
그리고 도면에는 도시되지 않았지만 절연막(36)상에 감광막을 도포하고 게이트 형성 부분만 남도록 노광 및 현상하여서 감광막을 선택적으로 패터닝한다.Although not shown in the figure, a photoresist film is coated on the insulating film 36, and the photoresist film is selectively patterned by exposing and developing so that only the gate forming portion remains.
이후에 패터닝된 감광막을 마스크로 도 3b에 도시한 바와 같이 절연막(36)을 이방성 식각해서 캡절연막(36a)을 형성하고, 다음에 감광막을 제거하고 세정한다.Subsequently, as shown in FIG. 3B using the patterned photosensitive film as a mask, the insulating film 36 is anisotropically etched to form a cap insulating film 36a. Then, the photosensitive film is removed and cleaned.
다음에 캡절연막(36a)을 마스크로 제 2 메탈층(35)과 베리어금메탈층(34)과 제 1 메탈층(33)을 차례로 이방성 식각해서 게이트전극을 형성한다. 이때 게이트전극을 식각할 때 텅스텐(W)/TiN/Ti은 MREIT 식각장비를 이용해서 식각한다.Next, the gate electrode is formed by anisotropically etching the second metal layer 35, the barrier gold metal layer 34, and the first metal layer 33 using the cap insulating film 36a as a mask. At this time, when etching the gate electrode, tungsten (W) / TiN / Ti is etched using a MREIT etching equipment.
여기에서 텅스텐 식각시 식각가스로는 SF6, N2가스를 사용하고, 압력은 5∼40mt범위에서 진행하고, 파워는 100∼300W 범위에서 실시한다.In the tungsten etching process, SF 6 and N 2 gas are used as the etching gas, the pressure proceeds in the range of 5 to 40 mt, and the power is performed in the range of 100 to 300W.
그리고 Ti/TiN으로 구성된 제 1 메탈층(33)의 식각은 Cl, N2, O2의 혼합가스 플라즈마를 이용해서 수직으로 게이트산화막(32)에 식각 데미지(damage)가 발생하지 않도록 실시한다. 이때 압력은 5∼40mt범위가 되도록 하고, 파워는 100∼300W 범위에서 실시한다.The etching of the first metal layer 33 made of Ti / TiN is performed so that an etch damage is not generated in the gate oxide layer 32 vertically using a mixed gas plasma of Cl, N 2 , and O 2 . At this time, the pressure is in the range of 5 to 40mt, and the power is performed in the range of 100 to 300W.
상기와 같은 본 발명 반도체소자의 제조방법은 다음과 같은 효과가 있다.The method of manufacturing the semiconductor device of the present invention as described above has the following effects.
게이트산화막 상부에 곧바로 Ti/TiN으로 구성된 메탈층을 증착한 후 Cl, N2,O2의 혼합가스 플라즈마를 이용해서 식각하므로 게이트산화막의 손상없이 저항이 낮은 게이트전극을 형성할 수 있을 뿐만 아니라 그 공정을 단순화 시킬 수 있다.After depositing a metal layer composed of Ti / TiN directly on top of the gate oxide layer and etching using a mixed gas plasma of Cl, N 2 and O 2 , it is possible to form a low-resistance gate electrode without damaging the gate oxide layer. The process can be simplified.
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020000008440A KR100364810B1 (en) | 2000-02-22 | 2000-02-22 | Method for fabricating of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020000008440A KR100364810B1 (en) | 2000-02-22 | 2000-02-22 | Method for fabricating of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20010082903A true KR20010082903A (en) | 2001-08-31 |
KR100364810B1 KR100364810B1 (en) | 2002-12-16 |
Family
ID=19648693
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020000008440A KR100364810B1 (en) | 2000-02-22 | 2000-02-22 | Method for fabricating of semiconductor device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100364810B1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101062836B1 (en) * | 2007-12-21 | 2011-09-07 | 주식회사 하이닉스반도체 | Semiconductor device manufacturing method |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5886724A (en) * | 1981-11-18 | 1983-05-24 | Nec Corp | Preparation of electrode and wiring |
JPS62163341A (en) * | 1986-01-14 | 1987-07-20 | Fujitsu Ltd | Patterning method for high melting-point metallic film |
JPH06151381A (en) * | 1992-11-09 | 1994-05-31 | Hitachi Ltd | Creation of metal pattern |
KR960009013A (en) * | 1994-08-18 | 1996-03-22 | 김광호 | Titanium nitride (TiN) gate electrode formation method |
KR100238872B1 (en) * | 1997-05-28 | 2000-01-15 | 윤종용 | Method of manufacturing semiconductor device |
-
2000
- 2000-02-22 KR KR1020000008440A patent/KR100364810B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR100364810B1 (en) | 2002-12-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2004032221A1 (en) | Hardmask employing multiple layers of silicon oxynitride | |
JP2008502141A (en) | Gate stack and gate stack etching sequence for metal gate integration | |
US5936279A (en) | Method of fabricating self-align contact window with silicon nitride side wall | |
JP2002252348A (en) | Method for manufacturing semiconductor device | |
KR100364810B1 (en) | Method for fabricating of semiconductor device | |
KR100558038B1 (en) | Method for fabricating semiconductor device | |
KR101123041B1 (en) | Method for forming semiconductor device | |
KR100811449B1 (en) | Semiconductor device and the fabricating method thereof | |
KR100511907B1 (en) | Method of manufacturing semiconductor device | |
KR20040005381A (en) | Method for fabricating cmos image sensor device | |
KR20050114949A (en) | Method for gate electrode of semiconductor device | |
KR100356475B1 (en) | Method of manufacturing a transistor | |
KR100390815B1 (en) | A forming method of gate electrode | |
KR100298427B1 (en) | Method for fabricating semiconductor device | |
KR100474744B1 (en) | Method for fabricating gate spacer of semiconductor device | |
KR100314738B1 (en) | Method for forming gate electrode in semiconductor device | |
KR100603589B1 (en) | Method of forming contact hole in semiconductor device | |
KR20000004522A (en) | Method for manufacturing semiconductor devices | |
KR100772699B1 (en) | Method for forming semiconductor device | |
KR100223942B1 (en) | Method of manufacturing gate of semiconductor device | |
KR100249175B1 (en) | Method for fabricating of capacitor | |
KR20030000662A (en) | Method for manufacturing a transistor in a semiconductor device | |
KR20010004275A (en) | Method of manufacturing a semiconductor device | |
KR20090030507A (en) | Method for fabricating semiconductor device | |
KR20030001820A (en) | Method for manufacturing of semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20101125 Year of fee payment: 9 |
|
LAPS | Lapse due to unpaid annual fee |