KR100558038B1 - Method for fabricating semiconductor device - Google Patents

Abstract

To provide a method for manufacturing a semiconductor device that can improve the storage node contact resistance of the memory cell by removing the polymer, the method of manufacturing a semiconductor device for achieving the above object comprises the steps of forming a transistor on a substrate; Forming a first interlayer insulating film having a contact hole on the substrate to expose the source / drain regions of the transistor; Forming a first contact plug in the contact hole; Forming a bit line on the first interlayer dielectric layer to be in contact with one source / drain region of the transistor; Forming sidewall spacers on both sides of the bit line; Depositing a second interlayer insulating film on the entire surface of the substrate including the bit line and sidewall spacers; Etching the second interlayer insulating layer to expose the first contact plug to form a self-aligned contact hole; Performing a post-treatment process on the self-aligned contact hole using a plasma gas of NF ₃ + He + O ₂ mixed gas; And forming a second contact plug for storage node contact only in the self-aligned contact hole.

Polymer, Resistor, SAC, Contact Plug, Gas

Description

Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}             

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

FIG. 2 is an interface TEM analysis photograph of the first and second contact plugs of FIG. 1E. FIG.

3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

4 is an interface TEM analysis photograph of the first and second contact plugs of FIG. 3E.

* Explanation of symbols for the main parts of the drawings

30 semiconductor substrate 31 interlayer insulating film

32: first contact plug 33: bit line

34: cap insulation film 35a: side wall spacer

36: second interlayer insulating film 37: third insulating film

38: fourth insulating film 39: photosensitive film

40: self-aligned contact hole 41: the second contact plug

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of manufacturing a semiconductor device capable of improving storage node contact resistance of a memory cell.

As the degree of integration of semiconductor devices increases, the open area of the active area is gradually reduced, and the process technology for forming contacts is becoming more and more advanced. Accordingly, in the case of devices having a design rule of 0.21 µm or less, devices are manufactured by applying a self alignment contact (SAC) process to form small contacts.

In the SAC process, a spacer of a transistor is formed of a SiN film instead of an HTO film, thereby increasing an etching selectivity when forming a contact hole, thereby increasing a process margin for misalignment.

Hereinafter, a method of manufacturing a semiconductor device according to the prior art will be described with reference to the accompanying drawings.

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art, and FIG. 2 is an interface TEM image of the first and second contact plugs of FIG. 1E.

First, as shown in FIG. 1A, a first interlayer insulating layer 11 is deposited on a semiconductor substrate 10 on which a gate electrode and a source / drain region (not shown) are formed, and the first interlayer insulating layer 11 is exposed so that the source / drain regions are exposed. ) Is etched to form a first contact hole. Thereafter, a first contact plug 12 is formed in the first contact hole.

Subsequently, as shown in FIG. 1B, a metal film for forming a bit line and a first insulating film for a hard mask are sequentially deposited. Thereafter, the first insulating film is etched using the bit line forming mask, and the metal film is etched using the etched first insulating film as a mask to form the bit line 13 and the cap insulating film 14. At this time, the first insulating film is formed of a nitride film and the metal film is formed of tungsten.

Next, a second insulating film 15 for forming sidewall spacers is deposited on the entire surface of the semiconductor substrate 10 including the bit line 13 and the cap insulating film 14. At this time, the second insulating film 15 is formed of a nitride film.

Next, as shown in FIG. 1C, the sidewall spacers 15a are formed on the side surfaces of the bit line 13 and the cap insulation layer 14 by etching back the second insulating layer 15.

Next, the second interlayer insulating film 16 and the third and fourth insulating films 17 and 18 are sequentially placed on the entire surface of the semiconductor substrate 10 including the bit line 13, the cap insulating film 14, and the sidewall spacers 15a. Deposit. In this case, the second interlayer insulating film 16 and the fourth insulating film 18 are formed of an oxide film, and the third insulating film 17 is formed of a nitride film to be used as an etch stop layer.

Subsequently, as illustrated in FIG. 1D, the photoresist film 19 is coated on the fourth insulating film 18, and then the exposure and development processes are performed to expose the fourth insulating film 18 on the first contact plug 12. The photosensitive film 19 is patterned as much as possible.

Next, the fourth and third insulating films 18 and 17 and the second interlayer insulating film 16 are sequentially etched using the patterned photoresist film 19 as a mask so that the first contact plug 12 is exposed. Align Contact) hole 20 is formed. Thereafter, after forming the self-aligned contact hole 20, C4F8 (C5F8) + Ar + O2 gas is used to perform post-treatment.

Subsequently, after the photosensitive film 19 is removed, a semiconductor layer is deposited on the entire surface including the self-aligned contact hole 20 as shown in FIG. 1E. At this time, the semiconductor layer uses polysilicon. Thereafter, the entire semiconductor layer is etched to remain only in the self-aligned contact hole 20 to form a second contact plug 21 for storage node contact.

After the process of forming the self-aligned contact hole 20 during the above process, the post-treatment using C4F8 (C5F8) + Ar + O2 gas is carried out to remove the first contact plug 12 as shown in FIGS. 1D and 2. An excessive amount of amorphous oxide film, that is, a polymer, is formed on the upper portion with a thickness of about 20 to 30 micrometers. Such generated polymers cannot be completely removed in a subsequent cleaning process.

As a result, the contact area between the first contact plug 12 and the second contact plug 21 for the storage node contact is reduced, and a problem arises in that the contact resistance becomes large.

As a result, the 'T' defective (tRWL) rate is increased in the probe test and the final test, resulting in low yield and adversely affecting the leaf lash.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a semiconductor device capable of improving the storage node contact resistance of a memory cell by removing a polymer.

According to an aspect of the present invention for achieving the above technical problem, forming a transistor on a substrate; Forming a first interlayer insulating film having a contact hole on the substrate to expose the source / drain regions of the transistor; Forming a first contact plug in the contact hole; Forming a bit line on the first interlayer dielectric layer to be in contact with one source / drain region of the transistor; Forming sidewall spacers on both sides of the bit line; Depositing a second interlayer insulating film on the entire surface of the substrate including the bit line and sidewall spacers; Etching the second interlayer insulating layer to expose the first contact plug to form a self-aligned contact hole; Performing a post-treatment process on the self-aligned contact hole using a plasma gas of NF ₃ + He + O ₂ mixed gas; And forming a second contact plug for a storage node contact only in the self-aligned contact hole.

Hereinafter, a method of manufacturing a semiconductor device according to a preferred embodiment of the present invention will be introduced in order to enable those skilled in the art to more easily implement the present invention.

3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, and FIG. 4 is an interface TEM analysis photograph of the first and second contact plugs of FIG. 3E.

First, as shown in FIG. 3A, a transistor having a gate electrode and a source / drain region (not shown) is formed on the semiconductor substrate 30, and a first interlayer insulating layer 31 is formed on the semiconductor substrate 30 including the transistor. The first interlayer dielectric layer 31 is etched to form a first contact hole so as to expose the source / drain regions. Thereafter, a first contact plug 32 is formed in the first contact hole.

Next, as shown in FIG. 3B, a metal film for forming a bit line and a first insulating film for a hard mask are sequentially deposited. Thereafter, the first insulating film is etched using the bit line forming mask, and the metal film is etched using the etched first insulating film as a mask to form the bit line 33 and the cap insulating film 34. The metal film is in contact with the source / drain regions of the transistor, the first insulating film is formed of a nitride film, and the metal film is formed of tungsten.

Next, a second insulating film 35 for forming sidewall spacers is deposited on the entire surface of the semiconductor substrate 30 including the bit line 33 and the cap insulating film 34. At this time, the second insulating film 35 is formed of a nitride film.

Next, as shown in FIG. 3C, the second insulating layer 35 is etched back to form sidewall spacers 35a on the side surfaces of the bit line 33 and the cap insulating layer 34.

Next, the second interlayer insulating film 36 and the third and fourth insulating films 37 and 38 are sequentially placed on the entire surface of the semiconductor substrate 30 including the bit lines 33, the cap insulating film 34, and the sidewall spacers 35a. Deposit. In this case, the second interlayer insulating film 36 and the fourth insulating film 38 are formed of an oxide film, and the third insulating film 37 is formed of a nitride film to be used as an etch stop layer.

Subsequently, after the photoresist film 39 is coated on the fourth insulating film 38 as shown in FIG. 3D, an exposure and development process is performed to expose the fourth insulating film 38 on the first contact plug 32. The photosensitive film 39 is patterned as much as possible.

Next, the fourth and third insulating films 38 and 37 and the second interlayer insulating film 36 are sequentially etched using the patterned photoresist film 39 as a mask so that the first contact plug 32 is exposed. Align Contact) hole 40 is formed.

Subsequently, an after process (AP) is performed using a plasma gas of NF ₃ + He + O ₂ mixed gas in the same equipment. At this time, the flow rate of the gas has a range of 20 ~ 200sccm NF ₃ , 10 ~ 100sccm He, 10 ~ 20sccm O ₂ .

As described above, when the post-treatment process is performed using NF ₃ + He + O ₂ mixed gas, the polymers of the SixFyOz and Si-C forms into pure SiO ₂ polymers and are completely removed in a subsequent cleaning process.

In addition, in the post-treatment process, in addition to the gas, CF4 + Ar + O2 gas may be used. At this time, the working pressure should be 30 ~ 200mT, and the bottom power should be 20 ~ 300W.

Subsequently, after the photosensitive film 39 is removed, a semiconductor layer is deposited on the entire surface including the self-aligned contact hole 40 as illustrated in FIG. 3E. At this time, the semiconductor layer uses a polysilicon layer. Thereafter, the entire semiconductor layer is etched to remain only in the self-aligned contact hole 40 to form a second contact plug 41 for the storage node contact.

As described above, when the post-treatment process is performed using NF ₃ + He + O ₂ gas, an abnormal substance, ie, a polymer, is observed at the interface between the first and second contact plugs 32 and 41 as shown in FIG. 4. It doesn't work.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The method of manufacturing the semiconductor device of the present invention described above has the following effects.

The polymer may be removed to prevent an increase in contact resistance between the first contact plug and the second contact plug (storage node contact).

Accordingly, the yield can be improved by improving the occurrence of 'T' defect (tRWL) as a result of the probe test and the final test.

Claims (7)

Forming a transistor on the substrate; Forming a first interlayer insulating film having a contact hole on the substrate to expose the source / drain regions of the transistor; Forming a first contact plug in the contact hole; Forming a bit line on the first interlayer dielectric layer to be in contact with one source / drain region of the transistor; Forming sidewall spacers on both sides of the bit line; Depositing a second interlayer insulating film on the entire surface of the substrate including the bit line and sidewall spacers; Etching the second interlayer insulating layer to expose the first contact plug to form a self-aligned contact hole; Performing a post-treatment process on the self-aligned contact hole using a plasma gas of NF ₃ + He + O ₂ mixed gas; And Forming a second contact plug for storage node contact only within the self-aligned contact hole Method for manufacturing a semiconductor device comprising a. The method of claim 1, In the NF ₃ + He + O ₂ mixed gas, NF ₃ is 20 to 200 sccm, He is 10 to 100 sccm, O ₂ has a range of 10 to 20 sccm. delete delete The method of claim 1, And forming a cap insulation film formed of a nitride film on the bit line. The method of claim 1, And the sidewall spacers are formed of a nitride film. The method of claim 1, And the post-treatment process is performed in the same equipment as the self-aligned contact hole forming equipment.

Images