KR100596892B1 - Method for forming transistors of semiconductor devices - Google Patents

Method for forming transistors of semiconductor devices Download PDF

Info

Publication number
KR100596892B1
KR100596892B1 KR1020040001580A KR20040001580A KR100596892B1 KR 100596892 B1 KR100596892 B1 KR 100596892B1 KR 1020040001580 A KR1020040001580 A KR 1020040001580A KR 20040001580 A KR20040001580 A KR 20040001580A KR 100596892 B1 KR100596892 B1 KR 100596892B1
Authority
KR
South Korea
Prior art keywords
buffer oxide
oxide film
hard mask
film
entire surface
Prior art date
Application number
KR1020040001580A
Other languages
Korean (ko)
Other versions
KR20050073230A (en
Inventor
백현철
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020040001580A priority Critical patent/KR100596892B1/en
Publication of KR20050073230A publication Critical patent/KR20050073230A/en
Application granted granted Critical
Publication of KR100596892B1 publication Critical patent/KR100596892B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052—Wet cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
    • H01L21/02315—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02469—Group 12/16 materials
    • H01L21/02472—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 트랜지스터 형성 방법에 관한 것으로서, 하드마스크인 질화막을 구비한 게이트 전극의 전표면에 형성한 버퍼 산화막 중에서 하드마스크 측벽의 버퍼 산화막을 제거한 후 후속 질화막 형성 공정을 실시함으로써 버퍼 산화막을 통한 수소(hydrogen)의 침입에 따른 셀(Cell) 전압의 강하를 방지하여 공정수율 및 소자의 신뢰성을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a transistor of a semiconductor device, wherein a buffer oxide film is formed by removing a buffer oxide film on a sidewall of a hard mask from a buffer oxide film formed on the entire surface of a gate electrode having a nitride film as a hard mask, and then performing a subsequent nitride film forming process. It is possible to improve the process yield and the reliability of the device by preventing the drop of the cell voltage due to the penetration of hydrogen through.

Description

반도체 소자의 트랜지스터 형성 방법{METHOD FOR FORMING TRANSISTORS OF SEMICONDUCTOR DEVICES}METHODE FOR FORMING TRANSISTORS OF SEMICONDUCTOR DEVICES

도 1a 내지 도 1c 는 종래 기술에 따른 반도체 소자의 트랜지스터 형성 공정도.1A to 1C are transistor forming process diagrams of a semiconductor device according to the prior art.

도 2 는 종래 기술에 따른 반도체 소자의 트랜지스터 단면 TEM 사진도.2 is a cross-sectional TEM photograph of a semiconductor device according to the prior art.

도 3a 내지 도 3e 는 본 발명에 따른 반도체 소자의 트랜지스터 형성 공정도.3A to 3E are transistor forming process diagrams of a semiconductor device according to the present invention.

< 도면의 주요한 부분에 대한 부호의 설명 ><Description of the reference numerals for the main parts of the drawings>

10,40 : 반도체 기판 12 : 폴리 실리콘 패턴 10,40: semiconductor substrate 12: polysilicon pattern

14 : WSi 패턴 16,44 : 하드마스크14: WSi pattern 16, 44: hard mask

18,42 : 게이트 전극 20,46 : 버퍼 산화막18,42 gate electrode 20,46 buffer oxide film

22,50 : 질화막 24 : 스페이서22,50 nitride film 24 spacer

26,52 : 콘택 플러그 48 : 감광막26, 52: contact plug 48: photosensitive film

49 : 감광막 패턴49: photosensitive film pattern

본 발명은 반도체 소자의 트랜지스터 형성 방법에 관한 것으로서, 특히 하드마스크인 질화막을 구비한 게이트 전극의 전표면에 형성한 버퍼 산화막 중에서 하드마스크 측벽의 버퍼 산화막을 제거한 후 후속 질화막 형성 공정을 실시함으로써 버퍼 산화막을 통한 수소(hydrogen)의 침입에 따른 셀(Cell) 전압의 강하를 방지하여 공정수율 및 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 트랜지스터 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a transistor of a semiconductor device. In particular, a buffer oxide film is formed by removing a buffer oxide film on a sidewall of a hard mask from a buffer oxide film formed on the entire surface of a gate electrode having a nitride film as a hard mask, and then performing a subsequent nitride film forming process. The present invention relates to a method for forming a transistor of a semiconductor device capable of improving a process yield and device reliability by preventing a drop in cell voltage due to hydrogen intrusion.

반도체 소자의 크기가 작아짐에 따라 소자의 미세화에 관한 노력과 더불어, 반도체 소자의 특성열화를 방지하려는 노력이 가해지고 있다.As the size of a semiconductor device decreases, efforts have been made to miniaturize the device and to prevent deterioration of characteristics of the semiconductor device.

현재 반도체 소자에서 게이트 산화막, 게이트 도전층 및 하드마스크의 적층구조로 이루어진 게이트 전극의 측벽에 스페이서를 형성하기 위하여 버퍼 산화막과 질화막의 순차 증착 후 엣치 백을 실시한다. 여기서 상기 버퍼 산화막은 반도체 기판과 질화막의 열팽창계수 차이에 의한 전이(dislocation) 등을 방지하기 위하여, 상기 구조와 질화막 사이에 증착한다.In order to form spacers on sidewalls of a gate electrode having a stacked structure of a gate oxide film, a gate conductive layer, and a hard mask in a semiconductor device, an etching back is performed after sequentially depositing a buffer oxide film and a nitride film. Here, the buffer oxide film is deposited between the structure and the nitride film in order to prevent dislocation due to the difference in thermal expansion coefficient between the semiconductor substrate and the nitride film.

도 1a 내지 도 1c 는 종래 기술에 따른 반도체 소자의 트랜지스터 형성 공정도이다.1A to 1C are flowcharts of transistor formation of a semiconductor device according to the prior art.

도 1a 를 참조하면, 반도체 기판(10) 상에 게이트 산화막(도시안됨), 폴리 실리콘 패턴(12) 및 WSi 패턴(14)의 적층구조로 이루어진 게이트 전극(18) 위에 질화막으로 하드마스크(16)를 형성한다.Referring to FIG. 1A, a hard mask 16 is formed of a nitride film on a gate electrode 18 having a stacked structure of a gate oxide film (not shown), a polysilicon pattern 12, and a WSi pattern 14 on a semiconductor substrate 10. To form.

그다음, 상기 구조의 전표면에 버퍼 산화막(20)을 증착한다.Then, a buffer oxide film 20 is deposited on the entire surface of the structure.

도 1b 를 참조하면, 상기 구조의 전표면에 스페이서용 질화막(22)을 증착한 다. Referring to FIG. 1B, a nitride nitride film 22 for a spacer is deposited on the entire surface of the structure.

도 1c 를 참조하면, 상기 구조에 전면식각 공정을 수행하여 반도체 기판(10)을 노출시켜 스페이서(24)를 형성한다.Referring to FIG. 1C, a spacer 24 is formed by exposing the semiconductor substrate 10 by performing an entire surface etching process on the structure.

그다음, 상기 구조의 전표면에 층간절연막(도시안됨)을 증착한다. Then, an interlayer insulating film (not shown) is deposited on the entire surface of the structure.

그후, 콘택 마스크(도시안됨)를 이용한 사진식각 공정으로 콘택 홀 영역으로 예정된 부분의 상기 층간절연막을 식각하여 콘택 홀(도시안됨)을 형성한다.Thereafter, a contact hole (not shown) is formed by etching the interlayer insulating film in a portion intended for the contact hole region by a photolithography process using a contact mask (not shown).

이후, 상기 구조의 전표면에 상기 콘택 홀을 매립하는 콘택 플러그용 도전체(도시안됨)를 증착한다. 그리고, 평탄화 공정으로 하드마스크(16)를 노출시켜 콘택 플러그(26)를 분리한 후 후속공정을 진행한다.Thereafter, a contact plug conductor (not shown) is deposited on the entire surface of the structure to fill the contact hole. In addition, the hard mask 16 is exposed by the planarization process to separate the contact plug 26, and then a subsequent process is performed.

이때, 하드마스크(26) 측벽의 버퍼 산화막(20)에 후속공정에 의한 상부구조물로부터의 수소(hydrogen)가 침입하여 소자의 특성을 열화시킨다. 특히 WSi 패턴(14)과 폴리 실리콘 패턴(12)으로의 수소의 침입은 소자의 셀(Cell) 전압을 100 ~ 500 mV 강하시켜 소자의 신뢰성을 저하시킨다.At this time, hydrogen from the upper structure in a subsequent process penetrates into the buffer oxide film 20 on the sidewall of the hard mask 26 to deteriorate the characteristics of the device. In particular, the intrusion of hydrogen into the WSi pattern 14 and the polysilicon pattern 12 lowers the cell voltage of the device by 100 to 500 mV, thereby lowering the reliability of the device.

도 2 는 종래 기술에 따른 반도체 소자의 트랜지스터 단면 TEM 사진도이다.2 is a cross-sectional TEM photograph of a semiconductor device according to the prior art.

도 2 를 참조하면, 원형 점선 부분에서 수소의 침투가 발생되어 하측으로 진행함을 볼 수 있다.Referring to Figure 2, it can be seen that the penetration of hydrogen occurs in the circular dotted line portion proceeds to the lower side.

이를 방지하기 위하여 콘택 플러그의 분리 후 버퍼 산화막에 이온을 주입하여 클러스터(cluster)를 형성하는 방법과, 콘택 플러그의 분리 후 게이트 전극의 상부를 질화막으로 실링(sealing)하는 방법이 있다.In order to prevent this, there are a method of forming a cluster by injecting ions into the buffer oxide film after separation of the contact plug, and a method of sealing an upper portion of the gate electrode with a nitride film after separation of the contact plug.

그러나, 전자는 이온주입 공정의 추가와 리프레쉬 특성의 열화라는 문제점이 발생하고, 후자는 실제 패터닝을 포함한 주변기술의 난이도가 높아 100nm급 소자에서는 적용하지 못하는 문제점이 있다.However, the former suffers from the addition of an ion implantation process and deterioration of the refresh characteristics, and the latter has a problem of being difficult to apply to a 100 nm device because of the difficulty of peripheral technologies including actual patterning.

본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 하드마스크인 질화막을 구비한 게이트 전극의 전표면에 형성한 버퍼 산화막 중에서 하드마스크 측벽의 버퍼 산화막을 제거한 후 후속 질화막 형성 공정을 실시함으로써 버퍼 산화막을 통한 수소(hydrogen)의 침입에 따른 셀(Cell) 전압의 강하를 방지하여 공정수율 및 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 트랜지스터 형성 방법을 제공함에 있다.The present invention has been made to solve the above problems, and an object of the present invention is to remove the buffer oxide film on the sidewall of the hard mask from the buffer oxide film formed on the entire surface of the gate electrode having the nitride film as a hard mask, and then perform a subsequent nitride film forming process. The present invention provides a method of forming a transistor of a semiconductor device capable of preventing a drop in cell voltage due to intrusion of hydrogen through a buffer oxide film, thereby improving process yield and device reliability.

본 발명은 상기와 같은 목적을 달성하기 위한 것으로서, 본 발명에 따른 반도체 소자의 트랜지스터 형성 방법의 특징은, The present invention is to achieve the above object, the characteristics of the transistor forming method of a semiconductor device according to the present invention,

반도체 소자의 트랜지스터 형성 방법에 있어서,In the transistor formation method of a semiconductor element,

반도체 기판 상에 하드마스크를 구비한 게이트 전극을 형성하는 공정과,Forming a gate electrode having a hard mask on the semiconductor substrate;

상기 구조의 전표면에 버퍼 산화막을 증착하는 공정과,Depositing a buffer oxide film on the entire surface of the structure;

상기 구조의 전표면에 감광막을 형성하는 공정과,Forming a photosensitive film on the entire surface of the structure;

상기 감광막을 소정 두께 제거하되, 상기 게이트 전극과 상기 하드마스크의 계면 상측의 일정 높이까지 제거하는 공정과,Removing the photoresist by a predetermined thickness, and removing the photoresist to a predetermined height above an interface between the gate electrode and the hard mask;

상기 버퍼 산화막을 제거하는 공정과,Removing the buffer oxide film;

상기 구조의 전표면에 질화막을 증착하는 공정을 구비함에 있다. And depositing a nitride film on the entire surface of the structure.                     

또한 본 발명의 다른 특징은, 상기 게이트 전극과 하드마스크의 계면 상측의 일정 높이는 상기 계면으로부터 100 Å 이상 인 것과, 상기 감광막을 제거하는 공정은 O2 플라즈마 방식 및 부분노광에 의한 습식세정 방식중 어느 하나의 방식으로 실시하는 것과, 상기 버퍼 산화막을 제거하는 공정은 플라즈마 방식 및 습식세정 방식 중 어느 하나의 방식으로 실시하는 것과, 상기 습식세정 방식은 BOE 또는 HF 중 어느 하나를 사용하여 실시하는 것을 특징으로 한다.In addition, another feature of the present invention, the predetermined height above the interface between the gate electrode and the hard mask is 100 kPa or more from the interface, the step of removing the photosensitive film is any one of the O2 plasma method and the wet cleaning method by partial exposure. And the step of removing the buffer oxide film may be performed by any one of a plasma method and a wet cleaning method, and the wet cleaning method may be performed using either BOE or HF. do.

이하 본 발명에 따른 반도체 소자의 트랜지스터 형성 방법을 첨부도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, a method of forming a transistor of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 3a 내지 도 3e 는 본 발명에 따른 반도체 소자의 트랜지스터 형성 공정도이다.3A to 3E are flowcharts of transistor formation of a semiconductor device according to the present invention.

도 3a 를 참조하면, 반도체 기판(40) 상에 하드마스크(44)를 구비한 게이트 전극(42)을 형성한다. Referring to FIG. 3A, a gate electrode 42 having a hard mask 44 is formed on a semiconductor substrate 40.

그다음, 상기 구조의 전표면에 버퍼 산화막(46)을 증착한다.A buffer oxide film 46 is then deposited on the entire surface of the structure.

그후, 상기 구조의 전표면에 감광막(48)을 형성한다.Thereafter, a photosensitive film 48 is formed on the entire surface of the structure.

도 3b 를 참조하면, 게이트 전극(42)과 하드마스크(44)간 계면 상측의 일정 높이까지 감광막(48)을 제거한다. 여기서, 상기 일정 높이는 100 Å 이상인 것이 바람직하다. 또한, 감광막(48)을 제거하는 공정은 O2 플라즈마 방식 및 부분노광에 의한 습식세정 방식중 어느 하나의 방식으로 실시하는 것이 바람직하다. 이러써, 게이트 전극(42) 사이에 잔류 감광막 패턴(49)이 발생한다.Referring to FIG. 3B, the photosensitive film 48 is removed to a predetermined height above the interface between the gate electrode 42 and the hard mask 44. Here, it is preferable that the said fixed height is 100 kPa or more. In addition, it is preferable to perform the process of removing the photosensitive film 48 by either the O2 plasma system or the wet cleaning system by partial exposure. Thus, the residual photosensitive film pattern 49 is generated between the gate electrodes 42.

도 3c 를 참조하면, 버퍼 산화막(46)의 노출된 부분을 제거한다. 여기서, 버 퍼 산화막(46)의 노출된 부분을 제거하는 공정은 플라즈마 방식 및 습식세정 방식 중 어느 하나의 방식으로 실시하는 것이 바람직하다. 또한, 상기 습식세정 방식의 사용시 BOE 또는 HF 중 어느 하나를 사용하여 실시하는 것이 바람직하다.Referring to FIG. 3C, the exposed portion of the buffer oxide layer 46 is removed. Here, the step of removing the exposed portion of the buffer oxide film 46 is preferably carried out by any one of a plasma method and a wet cleaning method. In addition, when the wet cleaning method is used, it is preferable to carry out using either BOE or HF.

도 3d 를 참조하면, 잔류 감광막 패턴(49)을 제거하고 상기 구조의 전표면에 질화막(50)을 증착한다. 이로써, 하드마스크 측벽에 버퍼 산화막이 없으므로, 상부구조로 부터의 수소 침투를 억제할 수 있다.Referring to FIG. 3D, the residual photoresist pattern 49 is removed and a nitride film 50 is deposited on the entire surface of the structure. As a result, since there is no buffer oxide film on the sidewall of the hard mask, hydrogen penetration from the superstructure can be suppressed.

도 3e 를 참조하면, 상기 구조의 전표면에 층간절연막(도시안됨)을 증착한다. Referring to FIG. 3E, an interlayer insulating film (not shown) is deposited on the entire surface of the structure.

그다음, 콘택 마스크(도시안됨)를 이용한 사진식각 공정으로 콘택 홀 영역으로 예정된 부분의 상기 버퍼 산화막(46), 질화막(50) 및 층간절연막을 식각하여 콘택 홀(도시안됨)을 형성한다.Next, a contact hole (not shown) is formed by etching the buffer oxide film 46, the nitride film 50, and the interlayer insulating film in a portion intended for the contact hole region by a photolithography process using a contact mask (not shown).

그후, 상기 구조의 전표면에 상기 콘택 홀을 매립하는 콘택 플러그용 도전체(도시안됨)를 증착한다. 그리고, 평탄화 공정으로 하드마스크(44)를 노출시켜 콘택 플러그(52)를 분리한 후 후속공정을 진행한다.Then, a contact plug conductor (not shown) is deposited on the entire surface of the structure. In addition, the hard mask 44 is exposed by the planarization process to separate the contact plug 52, and then the subsequent process is performed.

본 발명에 따른 반도체 소자의 트랜지스터 형성 방법은, 하드마스크(44) 측벽에 질화막(50)을 형성하여 후속공정의 상부구조로부터의 수소의 침투를 방지하여 종래 기술에서 발생할 수 있는 셀 전압 강하를 방지할 수 있고, 게이트 전극 상부 사이의 공간이 증가하여 ?? 필(gap fill)이 향상된다.In the method for forming a transistor of a semiconductor device according to the present invention, the nitride film 50 is formed on the sidewall of the hard mask 44 to prevent penetration of hydrogen from the superstructure of a subsequent process, thereby preventing a cell voltage drop that may occur in the prior art. And the space between the top of the gate electrode is increased ?? The fill fill is improved.

이상에서 설명한 바와 같이, 본 발명에 따른 반도체 소자의 트랜지스터 형성 방법은, 하드마스크인 질화막을 구비한 게이트 전극의 전표면에 형성한 버퍼 산화막 중에서 하드마스크 측벽의 버퍼 산화막을 제거한 후 후속 질화막 형성 공정을 실시함으로써 버퍼 산화막을 통한 수소(hydrogen)의 침입에 따른 셀(Cell) 전압의 강하를 방지하여 공정수율 및 소자의 신뢰성을 향상시킬 수 있는 효과가 있다.As described above, the method for forming a transistor of a semiconductor device according to the present invention comprises removing the buffer oxide film on the sidewall of the hard mask from the buffer oxide film formed on the entire surface of the gate electrode having the nitride film as the hard mask, and then performing the subsequent nitride film forming process. By doing so, it is possible to prevent the drop of the cell voltage due to the intrusion of hydrogen through the buffer oxide layer, thereby improving the process yield and the reliability of the device.

Claims (5)

반도체 기판 상에 하드마스크를 구비한 게이트 전극을 형성하는 공정과,Forming a gate electrode having a hard mask on the semiconductor substrate; 상기 구조의 전표면에 버퍼 산화막을 증착하는 공정과,Depositing a buffer oxide film on the entire surface of the structure; 상기 구조의 전표면에 감광막을 형성하는 공정과,Forming a photosensitive film on the entire surface of the structure; 상기 감광막을 소정 두께 제거하되, 상기 게이트 전극과 상기 하드마스크의 계면 상측의 일정 높이까지 제거하여 버퍼 산화막의 일부를 노출시키는 공정과,Removing the photoresist by a predetermined thickness, and removing a portion of the buffer oxide layer by removing the photoresist to a predetermined height above the interface between the gate electrode and the hard mask; 상기 버퍼 산화막의 노출된 부분을 제거하는 공정과,Removing the exposed portion of the buffer oxide film; 상기 구조의 전표면에 질화막을 증착하는 공정을 구비하는 반도체 소자의 트랜지스터 형성 방법.And depositing a nitride film on the entire surface of the structure. 제1항에 있어서,The method of claim 1, 상기 게이트 전극과 하드마스크간 계면 상측의 일정 높이는 상기 계면으로부터 100 Å 이상 인 것을 특징으로 하는 반도체 소자의 트랜지스터 형성 방법.And a predetermined height above the interface between the gate electrode and the hard mask is 100 kW or more from the interface. 제1항에 있어서,The method of claim 1, 상기 감광막을 제거하는 공정은 O2 플라즈마 방식 및 부분노광에 의한 습식세정 방식중 어느 하나의 방식으로 실시하는 것을 특징으로 하는 반도체 소자의 트랜지스터 형성 방법.The method of removing the photoresist film is performed by any one of an O2 plasma method and a wet cleaning method by partial exposure. 제1항에 있어서,The method of claim 1, 상기 버퍼 산화막의 노출된 부분을 제거하는 공정은 플라즈마 방식 및 습식세정 방식 중 어느 하나의 방식으로 실시하는 것을 특징으로 하는 반도체 소자의 트랜지스터 형성 방법.And removing the exposed portion of the buffer oxide film by any one of a plasma method and a wet cleaning method. 제4항에 있어서,The method of claim 4, wherein 상기 습식세정 방식은 BOE 또는 HF 중 어느 하나를 사용하여 실시하는 것을 특징으로 하는 반도체 소자의 트랜지스터 형성 방법.The wet cleaning method is a transistor forming method of a semiconductor device, characterized in that performed using either BOE or HF.
KR1020040001580A 2004-01-09 2004-01-09 Method for forming transistors of semiconductor devices KR100596892B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020040001580A KR100596892B1 (en) 2004-01-09 2004-01-09 Method for forming transistors of semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020040001580A KR100596892B1 (en) 2004-01-09 2004-01-09 Method for forming transistors of semiconductor devices

Publications (2)

Publication Number Publication Date
KR20050073230A KR20050073230A (en) 2005-07-13
KR100596892B1 true KR100596892B1 (en) 2006-07-04

Family

ID=37262373

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020040001580A KR100596892B1 (en) 2004-01-09 2004-01-09 Method for forming transistors of semiconductor devices

Country Status (1)

Country Link
KR (1) KR100596892B1 (en)

Also Published As

Publication number Publication date
KR20050073230A (en) 2005-07-13

Similar Documents

Publication Publication Date Title
KR101095767B1 (en) Semiconductor device
KR101130005B1 (en) Semiconductor device and method for forming using the same
US20080160698A1 (en) Method for fabricating a semiconductor device
KR20090121475A (en) Vertical semiconductor device and method of manufacturing the same
KR100596892B1 (en) Method for forming transistors of semiconductor devices
KR100702785B1 (en) Method of manufacturing a transistor in a semiconductor device
US7189622B2 (en) Method for fabricating semiconductor device
KR20120121723A (en) Semiconductor device and method for forming the same
KR101128885B1 (en) Method for forming semiconductor device
KR101120185B1 (en) Method for forming semiconductor device
KR20110010383A (en) Method for forming semiconductor device
KR100900237B1 (en) Semiconductor device and method of manufacturing the same
KR100733228B1 (en) Semiconductor device and method for fabricating the same
KR100680451B1 (en) Method of forming a contact plug in a semiconductor device
KR101019701B1 (en) Semiconductor device and method of manufacturing the same
KR100704472B1 (en) Method for manufacturing semiconductor device with recess gate
KR100827515B1 (en) Method for manufacturing of semiconductor device
KR101128904B1 (en) Method for Fabricating Transistor of Semiconductor Device
KR20060119354A (en) Method for forming a recess gate electrode
KR100709468B1 (en) Method for forming floating gate in flash memory device
KR100520176B1 (en) A method for forming a semiconductor device
KR100687397B1 (en) Method of manufacturing a semiconductor device
KR101043364B1 (en) Method for manufacturing the semiconductor device
KR100894786B1 (en) Method of manufacturing a memory device
KR100621451B1 (en) method for manufacturing semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110526

Year of fee payment: 6

LAPS Lapse due to unpaid annual fee