KR100827515B1 - Method for manufacturing of semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to prevent a gate from being contacted to a landing plug without damaging the gate by forming the gate to bury a gate polysilicon layer and a gate electrode layer. A gate reserved region is etched on an active region to form a recess. A gate oxide film is formed on a recess sidewall and a device isolation film. A gate polysilicon layer is formed on the active region in source/drain reserved regions and inside the recess. An etching process is performed to remove a predetermined thickness of the gate polysilicon layer. A gate electrode layer(32) is formed to bury the gate polysilicon layer inside the recess. A blanket ion implantation process is performed to form source/drain regions in the active region. An insulation film(40) for a gate spacer is formed on an overall surface.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}

1A to 1R are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a gate of a semiconductor device.

A general gate uses a stack structure in which a gate polysilicon layer, a gate tungsten silicide layer, and a gate hard mask layer are stacked on an active region of a semiconductor substrate.

A method of manufacturing a gate having such a stack structure is as follows.

First, a gate oxide film is formed over the semiconductor substrate.

Next, a gate polysilicon layer, a gate tungsten silicide layer, and a gate hard mask layer are formed on the gate oxide layer.

Next, the gate hard mask layer, the gate tungsten silicide layer, and the gate polysilicon layer are etched using a mask defining a gate to form a gate.

Next, a buffer oxide film, a spacer nitride film, and a spacer oxide film are formed over the substrate including the gate.

Next, an interlayer insulating film is formed to fill the gaps between the gates, and the landing plug contact hole is formed by etching the interlayer insulating film with a landing plug contact mask.

Next, a landing plug spacer is formed on the side of the landing plug contact hole, and a conductive film is embedded in the landing plug contact hole to complete the landing plug.

That is, the gate stack manufacturing method of the conventional stack structure is complicated in the process step, and as the gap between the gates is gradually reduced according to the high integration of the semiconductor device, it is difficult to secure the process margin.

In particular, during the etching process for forming the landing plug contact hole, a shoulder of the gate hard mask layer is lost, and thus a bridge is generated between the gate and the landing plug.

In addition, as the semiconductor device is highly integrated, a short channel effect is induced as the channel length of the transistor is shortened, thereby degrading characteristics of the transistor.

The present invention has been made to solve the above problems, to provide a method for manufacturing a semiconductor device that can prevent the bridge (bridge) between the gate and the landing plug in the gate forming process, and can simplify the process steps. There is a purpose.

Method for manufacturing a semiconductor device according to the present invention for achieving the above object,

Etching the gate predetermined region on the active region to form a recess;

Forming a gate oxide layer on the recess sidewall and the isolation layer;

Forming a gate polysilicon layer over the active region and in the recess of the source / drain predetermined region;

Removing the gate polysilicon layer by a predetermined thickness by performing a front surface etching process;

Forming a gate electrode layer filling an upper portion of the gate polysilicon layer in the recess;

Forming a source / drain region in the active region by performing a blanket ion implantation process;

Forming an insulating film for a gate spacer on the entire surface

Characterized in that it comprises a.

In the method for manufacturing a semiconductor device according to the present invention, the forming of the gate polysilicon layer may include

Forming the gate polysilicon layer over the entire surface;

Forming a photoresist pattern on the gate polysilicon layer to cover the source / drain predetermined region;

Etching the gate polysilicon layer using the photoresist pattern as a mask;

Removing the photoresist pattern

To include,

The gate electrode layer forming process

Forming the gate electrode layer over the entire surface;

Exposing the gate oxide layer by performing an entire surface etching process on the gate electrode layer

To include,

After forming the nitride film for the gate spacer

Forming a first interlayer insulating film over the entire surface;

Forming a landing plug contact hole by etching the first interlayer insulating layer by a photolithography process using a landing plug contact mask;

Forming a nitride film for a landing plug contact spacer on the first interlayer insulating layer including the landing plug contact hole;

Removing the nitride film for the landing plug contact spacer at the bottom of the landing plug contact hole;

Forming a conductive film for landing plug on the entire surface;

Forming a landing plug by performing an entire surface etching process on the landing plug conductive film

It further comprises a,

After the landing plug forming step

Forming a second interlayer insulating film over the entire surface;

Forming a bit line contact hole by etching the second interlayer insulating layer by a photolithography process using a bit line contact mask;

Forming a bit line including a barrier layer, a bit line electrode layer, and a bit line hard mask layer on the second interlayer insulating layer including the bit line contact hole;

Forming a third interlayer insulating film on the bit line;

Forming a storage electrode contact hole by etching the third interlayer insulating layer and the second interlayer insulating layer by a photolithography process using a storage electrode contact mask;

Completing a storage electrode by forming a conductive film for the storage electrode in the storage electrode contact hole;

It characterized in that it further comprises.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1R are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

Referring to FIG. 1A, a pad oxide film (not shown) and a pad nitride film (not shown) are sequentially formed on the semiconductor substrate 10.

Subsequently, the pad nitride layer, the pad oxide layer, and the semiconductor substrate 10 having a predetermined depth are etched by a photolithography process using a device isolation mask to form a device isolation trench (not shown).

Next, a sidewall oxidation process is performed on the sidewalls and the bottom of the device isolation trench to form a sidewall oxide film 12.

Next, a liner nitride layer 14 is formed on the entire surface including the sidewall oxide layer 12, and a liner oxide layer 16 is formed on the liner nitride layer 14.

Next, an insulating layer is formed on the liner oxide layer 16 to completely gap-fill the trench for device isolation.

In this case, the insulating film is preferably formed of a high density plasma (HDP) oxide film.

Next, a planarization process is performed to expose the pad nitride layer, and the pad nitride layer and the pad oxide layer are removed to form the device isolation layer 20 defining the active region 18.

Next, a first photoresist pattern (not shown) is formed on the semiconductor substrate 10 to expose a gate predetermined region.

Next, the recess 22 is formed by etching the active region 18 by a predetermined depth using the first photoresist pattern.

Next, a gate oxide film 24 is formed on the entire surface including the recess 22.

Referring to FIG. 1B, a second photoresist layer pattern 26 exposing a source / drain predetermined region is formed on the gate oxide layer 24.

Referring to FIG. 1C, the gate oxide layer 24 is etched using the second photoresist layer pattern 26 to form a gate oxide layer pattern 24a.

Next, the second photosensitive film pattern 26 is removed.

Referring to FIG. 1D, a gate polysilicon layer 28 is formed over the entire surface.

Referring to FIG. 1E, a third photoresist pattern 30 is formed on the gate polysilicon layer 28 to cover the source / drain predetermined region.

Referring to FIG. 1F, the gate polysilicon layer 28 is etched using the third photoresist pattern 30 as a mask, and is formed in the upper portion of the active region 18 and the recess 22 in the source / drain predetermined region. The gate polysilicon layer pattern 28a is formed.

Next, the third photoresist pattern 30 is removed.

Referring to FIG. 1G, the gate polysilicon layer pattern 28a may be removed by performing a front surface etching process on the gate polysilicon layer pattern 28a.

In this case, the front surface etching process is to form a structure in which the gate polysilicon layer pattern 28a and the gate electrode layer 32 are stacked in the recess 22, and the active region 18 of the source / drain predetermined region is formed. The gate polysilicon layer pattern 28a may be partially left on the top surface.

Referring to FIG. 1H, the gate electrode layer 32 is formed over the entire surface.

In this case, the gate electrode layer 32 is preferably formed of a tungsten silicide (Wsi) layer.

Referring to FIG. 1I, the gate oxide layer pattern 24a is exposed by performing an entire surface etching process on the gate electrode layer 32.

Next, a blanket implant process is performed to form a source / drain region (not shown) in the active region 18.

In this case, ions are also implanted into the gate polysilicon layer pattern 28a remaining on the active region 18 of the source / drain region, thereby increasing a carrier. As a result, the channel resistance may be reduced, and damage to the semiconductor substrate 10 may be prevented during the etching process for forming the subsequent landing plug contact hole.

Referring to FIG. 1J, an insulating film 34 for a gate spacer is formed on the entire surface.

At this time, the gate spacer insulating film 34 is preferably formed of a nitride film.

Referring to FIG. 1K, a first interlayer insulating layer 36 is formed on the gate spacer insulating layer 34.

In this case, the first interlayer insulating layer 36 is preferably formed of a BPSG (Boron Phosphorus Silicate Glass) film.

Referring to FIG. 1L, a fourth photoresist pattern (not shown) is formed on the first interlayer insulating layer 36 to expose a predetermined region of the landing plug contact region.

Next, the first interlayer insulating layer 36 is etched using the fourth photoresist pattern as a mask to form a landing plug contact hole 38 exposing the gate polysilicon layer pattern 28a.

Then, the fifth photosensitive film pattern is removed.

Referring to FIG. 1M, an insulating film 40 for a landing plug contact spacer is formed on the first interlayer insulating layer 36 including the landing plug contact hole 38.

In this case, the landing plug contact spacer insulating film 40 may be formed of a nitride film.

Referring to FIG. 1N, the insulating plug 40 for the landing plug contact spacer at the bottom of the landing plug contact hole 38 is removed.

Referring to FIG. 1O, a conductive plug 42 for landing plug is formed on the entire surface.

At this time, the landing plug conductive film 42 is preferably formed of polysilicon.

Referring to FIG. 1P, the landing plug 44 may be formed by performing an entire surface etching process on the landing plug conductive layer 42.

Referring to FIG. 1Q, a second interlayer insulating film 46 is formed on the entire surface.

In this case, the second interlayer insulating film 46 may be formed of a BPSG (Boron Phosphorus Silicate Glass) oxide film.

Next, a fifth photoresist pattern (not shown) is formed on the second interlayer insulating layer 46 to expose the bit line contact predetermined region.

Next, the second interlayer insulating layer 46 is etched using the fifth photoresist pattern as a mask to form a bit line contact hole (not shown) that exposes the landing plug 44.

Then, the fifth photosensitive film pattern is removed.

Next, the barrier layer 48, the bit line electrode layer 50, and the bit line hard mask layer 52 are formed on the entire surface including the bit line contact hole.

At this time, the bit line electrode layer 50 is preferably formed of a tungsten (W) layer.

Next, the bit line hard mask layer 52, the bit line electrode layer 50, and the barrier layer 48 are etched by a photolithography process using a mask defining a bit line to complete the bit line.

Referring to FIG. 1R, a third interlayer insulating layer 54 is formed on the bit line hard mask layer 52.

In this case, the third interlayer insulating film 54 is preferably formed of a high density plasma (HDP) oxide film.

Next, a sixth photoresist layer pattern (not shown) is formed on the third interlayer insulating layer 54 to expose a storage electrode contact region.

Next, the third interlayer insulating layer 54 and the second interlayer insulating layer 46 are etched using the sixth photoresist pattern as a mask to form a storage electrode contact hole (not shown).

Then, the sixth photosensitive film pattern is removed.

Next, a storage electrode contact plug 56 is formed by filling a storage electrode conductive film in the storage electrode contact hole.

As described above, in the method of manufacturing the semiconductor device according to the present invention, a process margin between the gate and the landing plug can be secured by forming a gate having a buried structure filling the gate polysilicon layer and the gate electrode layer in the recess region. Thus, even when the gate hard mask layer is not formed separately, a bridge between the gate and the landing plug can be prevented without damaging the gate during the etching process for forming the landing plug contact hole.

The present invention can omit the process for forming the buffer oxide film, the nitride film for the spacer, the oxide film for the spacer, and the interlayer insulating film, thereby simplifying the process steps. In addition, the present invention can reduce the height of the landing plug and the storage electrode contact plug, and increase the height of the storage electrode, thereby sufficiently securing the capacitance.

In addition, the present invention performs an ion implantation process for source / drain formation while partially leaving a gate polysilicon layer on the semiconductor substrate in the source / drain predetermined region to increase carriers, thereby reducing channel resistance and landing plug contact. Damage to the semiconductor substrate may be prevented during the etching process for forming the hole.

As described above, in the method of manufacturing the semiconductor device according to the present invention, a process margin between the gate and the landing plug may be secured by forming a gate having a buried structure filling the gate polysilicon layer and the gate electrode layer in the recess region. Therefore, even if the gate hard mask layer is not formed separately, the bridge between the gate and the landing plug can be prevented without damaging the gate during the etching process for forming the landing plug contact hole.

In addition, the present invention can omit the process for forming the buffer oxide film, the nitride film for the spacer, the oxide film for the spacer, and the formation of the interlayer insulating film, thereby simplifying the process steps, and reducing the height of the landing plug and the storage electrode contact plug, and storing the same. The height of the electrode can be increased to provide an effect of sufficiently securing the capacitance.

In addition, the present invention performs an ion implantation process for source / drain formation while partially leaving a gate polysilicon layer on the semiconductor substrate in the source / drain predetermined region to increase carriers, thereby reducing channel resistance and landing plug contact. The etching process for forming the hole provides an effect of preventing damage to the semiconductor substrate.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (5)

Etching the gate predetermined area on the active area to form a recess; Forming a gate oxide layer on the recess sidewall and the isolation layer; Forming a gate polysilicon layer over the active region and in the recess of the source / drain predetermined region; Removing a predetermined thickness of the gate polysilicon layer by performing an entire surface etching process; Forming a gate electrode layer filling an upper portion of the gate polysilicon layer in the recess; Performing a blanket ion implantation process to form source / drain regions in the active region; And Forming an insulating film for a gate spacer on the entire surface Method of manufacturing a semiconductor device comprising a. The method of claim 1, wherein the gate polysilicon layer forming step Forming the gate polysilicon layer over the entire surface; Forming a photoresist pattern on the gate polysilicon layer to cover the source / drain predetermined region; Etching the gate polysilicon layer using the photoresist pattern as a mask; And Removing the photoresist pattern Method of manufacturing a semiconductor device comprising a. The method of claim 1, wherein the gate electrode layer forming process is performed. Forming the gate electrode layer over the entire surface; And Exposing the gate oxide layer by performing an entire surface etching process on the gate electrode layer Method of manufacturing a semiconductor device comprising a. The method of claim 1, further comprising, after forming the nitride film for the gate spacer. Forming a first interlayer insulating film over the entire surface; Etching the first interlayer insulating layer by a photolithography process using a landing plug contact mask to form a landing plug contact hole; Forming an insulating film for a landing plug contact spacer on the first interlayer insulating layer including the landing plug contact hole; Removing the insulating film for the landing plug contact spacers at the bottom of the landing plug contact hole; Forming a conductive film for landing plug on the entire surface; And Forming a landing plug by performing an entire surface etching process on the landing plug conductive film Method of manufacturing a semiconductor device further comprising. 5. The method of claim 4, wherein after the landing plug forming step Forming a second interlayer insulating film over the entire surface; Forming a bit line contact hole by etching the second interlayer insulating layer by a photolithography process using a bit line contact mask; Forming a bit line including a barrier layer, a bit line electrode layer, and a bit line hard mask layer on the second interlayer insulating layer including the bit line contact hole; Forming a third interlayer insulating film on the bit line; Forming a storage electrode contact hole by etching the third interlayer insulating layer and the second interlayer insulating layer by a photolithography process using a storage electrode contact mask; And Completing a storage electrode by forming a conductive film for the storage electrode in the storage electrode contact hole; Method of manufacturing a semiconductor device further comprising.

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