KR20080002549A - Method of manufacturing bitline contact hole in semiconductor device - Google Patents

Abstract

A method for forming a bitline contact hole in a semiconductor device is provided to decrease the number of process steps by using an NBC(nitride barrier contact etch) process while avoiding an open defect and an SAC(self-aligned contact) fail. A gate line is formed on a semiconductor substrate(21) in which a cell region and a peripheral region are defined, including a gate hard mask nitride layer. A landing plug contact is formed between the gate lines in the cell region. An interlayer dielectric is formed on the resultant structure. A mask is formed on the interlayer dielectric, simultaneously defining a bitline contact hole to be formed in the cell region and a bitline contact hole to be formed in the peripheral region. By performing a first etch process using the mask as an etch barrier, the bitline contact hole is partially opened by a first etch process using the mask as an etch barrier and the bitline contact hole is completely opened in the cell region. A second etch process is performed to completely open the bitline contact hole in the peripheral region. In the first etch process, etch gas having high etch selectivity with respect to a nitride layer can be used wherein plenty of polymer(31) is generated by the etch gas.

Description

Method for forming bit line contact hole of semiconductor device {METHOD OF MANUFACTURING BITLINE CONTACT HOLE IN SEMICONDUCTOR DEVICE}

1 is a view schematically showing a bit line contact hole forming method according to the prior art.

2A to 2D are cross-sectional views illustrating a method of forming a bit line contact hole according to an exemplary embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

21 semiconductor substrate 22 gate oxide film

23 gate electrode 24 gate hard mask nitride film

25A, 25B: gate spacer 26: cell spacer nitride film

27: first interlayer insulating film 28: landing plug contact

29: second interlayer insulating film 30: NBC mask

31: polymer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly to a method for forming a bit line contact hole in a semiconductor device.

Bitline contact hole (BLC) forms 'BLC1' in the cell area and 'BLC2' in the surrounding area during the DRAM manufacturing process.

In the BLC2 etching process for forming BLC2, the active region (N + junction region, P + junction region) and on-gate region of the peripheral region are etched, and the cell region is etched during BLC1 etching for BLC1 formation.

1 is a view schematically showing a bit line contact hole forming method according to the prior art.

Referring to FIG. 1, a semiconductor substrate 11 having a cell region and a peripheral region defined therein forms a gate line on each region. In this case, the gate line has a structure in which the gate oxide film 12, the gate electrode 13, and the gate hard mask nitride film 14 are stacked in this order.

Subsequently, gate spacers 15A and 15B are formed on both side walls of the gate line. At this time, the spacer etching is performed only in the peripheral region to form the sidewall gate spacer 15B. Thereafter, ion implantation for forming the N + junction and the P + junction proceeds in the peripheral region.

Subsequently, after forming the cell spacer film 16 on the entire surface, the first interlayer insulating film 17 is formed.

Next, the landing plug contact 18 is formed only in the cell region. In this case, in order to form the landing plug contact 18, contact etching is performed to expose the surface of the semiconductor substrate between the gate lines in the cell region, and polysilicon deposition and CMP are performed. Here, the CMP proceeds until the surface of the gate hard mask nitride film 14 is exposed.

Subsequently, after forming the second interlayer insulating film 18 on the entire surface, BLC1 and BLC2 are formed, respectively. Here, BLC1 is a contact hole exposing a part of the landing plug contact in the cell region, and BLC2 is a contact hole exposing the surfaces of the N + junction, P + junction and the gate electrode in the peripheral region.

However, the prior art has a problem in that the number of process steps increases because BLC1 and BLC2 are formed respectively.

Therefore, NBC (Nitride Barrier Contact etch) etching that merges BLC2 etching and BLC1 etching is applied.

However, in the case of applying NBC etching, the BLC1 etching target for etching the upper portion of the active area of the peripheral area is 4000Å and the BLC1 etching target for etching the landing plug contact of the cell area is 1000Å, so the BLC1 is different. If the etch target does not open in the BLC2 region (not open, see '19'), and if the BLC2 etch target, the etch target of the BLC1 region is too large, the loss of gate hard mask nitride film (drawing symbol ' 20 '), which results in a Self Aligned Contact (SAC) failure between the gate line and BLC1.

The present invention has been proposed to solve the above problems of the prior art, a semiconductor device capable of preventing open defects and SAC fail when BLC2 etching and BLC1 etching simultaneously using NBC (Nitride Barrier Contact etch) etching The purpose of the present invention is to provide a method for forming a bit line contact hole.

According to an aspect of the present invention, there is provided a method of forming a bit line contact hole, the method including: forming a gate line including a gate hard mask nitride layer on each region of a semiconductor substrate in which a cell region and a peripheral region are defined; Forming a landing plug contact between the gate line of the cell region; Forming an interlayer insulating film on the entire surface including the landing plug contact; Forming a mask on the interlayer insulating layer to simultaneously define a bit line contact hole to be formed in the cell region and a bit line contact hole to be formed in the peripheral region; Partially opening the bit line contact hole in the peripheral area and completely opening the bit line contact hole in the cell region through a first etching using the mask as an etching barrier; And performing a second etching to completely open the bit line contact hole in the peripheral area, wherein the first etching uses an etching gas having a high etching selectivity with respect to the nitride film. The second etching is characterized by using an etching gas for simultaneously etching the oxide film and the nitride film in a ratio of 1: 1.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

In the present invention to be described later, the etching process step is etched by dividing the etching process step into two steps during the NBC etching process to merge the BLC1 and BLC2 etching.

In the first etching step, as the SAC etching step using the SAC (Self Aligned Contact) etching gas, the gate hard mask nitride layer is etched in the BLC1 region where the etching target is small because the etching target is etched to leave 500 위에서 above the active region which is the BLC2 etching region. As a result, a lot of polymer is generated and an etch stop occurs.

Next, in the second etching step, if the oxide film remaining in the BLC2 region is etched by applying the oxide etching step, the BLC1 region no longer causes gate hard mask nitride film loss due to the polymer generated in the first etching step. An NBC etching process that merges etching and BLC2 etching can be applied.

It will be described in detail with reference to the accompanying drawings.

2A to 2D are cross-sectional views illustrating a method of forming a bit line contact hole according to an exemplary embodiment of the present invention.

As shown in FIG. 2A, a gate line is formed on each region of the semiconductor substrate 21 in which a cell region and a peripheral region are defined. In this case, the gate lines are stacked in the order of the gate oxide film 22, the gate electrode 23, and the gate hard mask nitride film 24.

Subsequently, gate spacers 25A and 25B are formed on both side walls of the gate line. At this time, the spacer etching is performed only in the peripheral region to form a gate spacer 25B having a sidewall shape. Thereafter, ion implantation for forming the N + junction and the P + junction proceeds in the peripheral region.

Subsequently, after forming the cell spacer nitride film 26 on the entire surface, the first interlayer insulating film 27 is formed. Here, the cell spacer nitride layer 26 serves as an etching barrier during subsequent contact etching for forming the landing plug contact, thereby preventing the gate line from being attacked.

Next, the landing plug contact 28 is formed only in the cell region. In this case, in order to form the landing plug contact 28, contact etching is performed to expose the surface of the semiconductor substrate between the gate lines in the cell region, and polysilicon deposition and CMP (or front etching) are performed. Here, the CMP proceeds until the surface of the gate hard mask nitride film 24 is exposed.

Subsequently, the second interlayer insulating film 29 is deposited on the entire surface and then planarized. In this case, the second interlayer insulating film 29 is formed of an oxide film material such as BPSG, and the first interlayer insulating film 27 is also formed of BPSG and a thin oxide film material.

Subsequently, an NBC mask 30 using a photosensitive film is formed on the second interlayer insulating film 29. In this case, the NBC mask 30 is a mask in which the bit line contact hole BLC1 to be formed in the cell region and the bit line contact hole BLC2 to be formed in the peripheral region are defined at the same time. Hereinafter, BLC1 is a landing plug contact ( 28) and the BLC2 will be formed over the active region of the peripheral region. The BLC2 formed on the gate electrode in the peripheral region will be omitted for convenience.

After forming the NBC mask 30 as described above, the NBC etching proceeds at the same time BLC1 etching and BLC2 etching.

The present invention proceeds by dividing the NBC etching into a first etching step (FIG. 2B) and a second etching step (FIG. 2C) as shown in FIGS. 2B and 2C.

First, as shown in FIG. 2B, the first etching step is performed using the NBC mask 29 as an etching barrier.

The first etching step uses an etching gas having a self-aligned contact (abbreviated as 'SAC etching gas'), that is, a gas having a high etching selectivity with respect to the nitride film which is well etched without the oxide film being etched well. . As such, when the SAC etching gas is used, as the gate hard mask nitride layer 24 is etched in a small amount in the cell region, many polymers 31 are generated, thereby causing an etch stop. At this time, the etch target during the first etching step is a target T1 that leaves about 500 Å on the active region of the BLC2 region, because the cell spacer nitrate 26 is on the active region. This is because there is a possibility of BLC2 opening if a target is reached up to 26).

Preferably, the SAC etching gas used in the first etching step uses any one selected from the group consisting of C ₄ F ₆ , C ₄ F _8, and C ₅ F ₈ . In order to generate a large amount of the polymer 31, the pressure of the etching chamber is 5 to 100 mT, and the etching target is a target T1 that leaves 500 to 1000 Pa over the active region of the BLC2 region.

As described above, when the first etching step is performed, BLC1 is formed on the landing plug contact 28 in the cell region, and BLC2 is partially opened on the active region of the peripheral region. On the other hand, when the BLC1 is opened in the first etching step, the loss of the gate hard mask nitride film 24 is very small, 500 mu m or less.

Next, the second etching step shown in FIG. 2C is performed.

As shown in FIG. 2C, the second etching step is an oxide layer etching step. The oxide etching step is to simultaneously etch the oxide film and the nitride film at a ratio of 1: 1. In order to completely open the partially opened BLC2, the remaining first interlayer insulating film 27 and the cell spacer nitride film 26 in the peripheral region are etched. Etch at the same time.

For example, the second etching step uses at least one gas selected from the group consisting of CF ₄ , CHF ₃ , O _2, and Ar (ie, single use or a mixture of two or more). In addition, the pressure of the etching chamber used in the second etching step is 5 to 100 mT, and the loss of the active region generated after the oxide film etching can be adjusted to 50 to 500 kPa.

As described above, when the second etching step is performed, the BLC2 is completely opened. In the case of BLC1, the loss of the gate hard mask nitride film 24 is no longer caused by the polymer 31 generated in the first etching step. You can see none (SAC Fail Free).

The polymer 31 is removed by a subsequent cleaning process, as shown in FIG. 2D. Typically, cleaning is performed after the contact etching, in which case the polymer 31 may be removed at the same time.

According to the above-described embodiment, the CD bias generated when merging BLC1 and BLC2 can be adjusted to 20 nm or less. Here, CD bias refers to the difference between the ID (Inspection Dimension) bias of BLC1 and BLC2, that is, the difference between the Development Inspection CD (DICD) and the Final Inspection CD (FICD). It can be minimized.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above can prevent open failure and SAC fail even when BLC2 and BLC1 etching are performed simultaneously using NBC (Nitride Barrier Contact etch) etching, and the present invention also prevents NBC while preventing open failure and SAC fail. Applying the process reduces the number of process steps, thereby reducing the unit cost and shorten the development period.

Claims (8)

Forming a gate line including a gate hard mask nitride layer on each region of the semiconductor substrate in which a cell region and a peripheral region are defined; Forming a landing plug contact between the gate line of the cell region; Forming an interlayer insulating film on the entire surface including the landing plug contact; Forming a mask on the interlayer insulating layer to simultaneously define a bit line contact hole to be formed in the cell region and a bit line contact hole to be formed in the peripheral region; Partially opening the bit line contact hole in the peripheral area and completely opening the bit line contact hole in the cell region through a first etching using the mask as an etching barrier; Performing a second etching to completely open the bit line contact hole in the peripheral region; Bit line contact hole forming method of a semiconductor device comprising a. The method of claim 1, The first etching is, A method for forming a bit line contact hole in a semiconductor device using an etching gas having a large etching selectivity with respect to a nitride film. The method of claim 2, In the first etching, the etching gas is a bit line contact hole forming method of a semiconductor device using a gas that generates a large amount of polymer. The method of claim 3, The etching gas during the first etching, A method for forming a bit line contact hole in a semiconductor device using any one selected from the group consisting of C ₄ F ₆ , C ₄ F _8, and C ₅ F ₈ . The method of claim 4, wherein At the first etching, A method of forming a bit line contact hole in a semiconductor device, wherein the etching chamber has a pressure of 5 to 100 mT, and the etching target is a target for leaving an interlayer insulating film in the surrounding area of 500 to 1000 kPa. The method of claim 1, The second etching is, A method of forming a bit line contact hole in a semiconductor device using an etching gas for simultaneously etching an oxide film and a nitride film at a ratio of 1: 1. The method of claim 6, At the second etching time, The etching gas is a bit line contact hole forming method of a semiconductor device using at least one gas selected from the group consisting of CF ₄ , CHF ₃ , O ₂ and Ar. The method of claim 7, wherein At the second etching time, A method of forming a bit line contact hole in a semiconductor device in which an etching chamber has a pressure of 5 to 100 mT, and an etching target is a target in which the semiconductor substrate in the peripheral region is lost by 50 to 500 kPa.

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