KR20010063891A - Semiconductor device forming method - Google Patents

Semiconductor device forming method Download PDF

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Publication number
KR20010063891A
KR20010063891A KR1019990061995A KR19990061995A KR20010063891A KR 20010063891 A KR20010063891 A KR 20010063891A KR 1019990061995 A KR1019990061995 A KR 1019990061995A KR 19990061995 A KR19990061995 A KR 19990061995A KR 20010063891 A KR20010063891 A KR 20010063891A
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Prior art keywords
gate oxide
oxide film
oxide layer
semiconductor substrate
film
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KR1019990061995A
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Korean (ko)
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이석우
김종관
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박종섭
주식회사 하이닉스반도체
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Priority to KR1019990061995A priority Critical patent/KR20010063891A/en
Publication of KR20010063891A publication Critical patent/KR20010063891A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to maintain a threshold voltage of a device with a thin oxide layer by changing a period of ion implantation. CONSTITUTION: A buffer oxide layer is formed on a semiconductor substrate(21). The buffer oxide layer is exposed by applying and patterning a photoresist thereon. Ions are implanted on the semiconductor substrate(21). The photoresist and the buffer oxide layer are removed. The first gate oxide layer(24) is formed by oxidizing the semiconductor substrate(21). The second gate oxide layer(25) is formed thereon. A photoresist layer is formed on the wholes structure. The first gate oxide layer(24) is removed partially and ions are implanted therein. The photoresist layer is removed. The first gate oxide layer(24) is removed and the second gate oxide layer(25) is formed thereon. The first gate oxide layer(24) is removed.

Description

반도체장치 제조방법{SEMICONDUCTOR DEVICE FORMING METHOD}Semiconductor device manufacturing method {SEMICONDUCTOR DEVICE FORMING METHOD}

본 발명은 반도체장치 제조방법에 관한 것으로, 특히 게이트산화막의 두께가 서로 틀리는 듀얼게이트(DUAL GATE)를 가지는 피모스트랜지스터 제조에 있어서 문턱전압(Vt)의 변화를 방지하기에 적당하도록 한 반도체장치 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to manufacturing a semiconductor device suitable for preventing a change in threshold voltage (Vt) in manufacturing a PMOS transistor having dual gates having different thicknesses of gate oxide films. It is about a method.

종래 반도체장치 제조방법의 일실시예를 도 1a 내지 도 1d의 수순단면도를 참고하여 설명하면 다음과 같다.An embodiment of a conventional semiconductor device manufacturing method is described below with reference to the procedure cross-sectional view of FIGS. 1A to 1D.

절연영역(2)이 형성된 반도체기판(1)상에 버퍼산화막(3)을 형성하고 반도체기판(1)상에 이온을 주입하는 제 1공정과; 상기 버퍼산화막(3)을 제거한후 반도체기판(1)을 산화하여 그 상부에 제 1 게이트산화막(4)을 형성하는 제 2공정과; 상기 구조물 상부전면에 감광막(PR1)을 형성하고, 얇은 게이트산화막이 형성될부분(B)의 제 1게이트산화막(4)이 드러나도록 패터닝한 후 드러난 제 1게이트산화막(4)을 일부 식각하는 제 3공정과; 상기 감광막(PR1)을 제거하고, 두꺼운 게이트산화막이 형성될 부분(A)의 제 1게이트산화막(4)의 잔량을 조절하면서 상기 얇은 게이트산화막이 형성될 부분(B)의 잔류하는 제 1게이트산화막(4)을 제거한 후 그 상부전면을 산화하여 제 2게이트산화막(25)을 형성하면서 두꺼운 게이트산화막 및 얇은 게이트 산화막의 두께를 맞추는 제 4공정으로 이루어진다.Forming a buffer oxide film 3 on the semiconductor substrate 1 on which the insulating region 2 is formed and injecting ions onto the semiconductor substrate 1; A second process of removing the buffer oxide film 3 and oxidizing the semiconductor substrate 1 to form a first gate oxide film 4 thereon; The photoresist film PR1 is formed on the upper surface of the structure, and the first gate oxide film 4 of the portion B on which the thin gate oxide film is to be formed is patterned so as to be exposed, and the first gate oxide film 4 is partially etched. 3 step; The first gate oxide film remaining in the portion B in which the thin gate oxide film is to be formed while removing the photoresist film PR1 and adjusting the remaining amount of the first gate oxide film 4 in the portion A in which the thick gate oxide film is to be formed. After removing (4), a fourth process is performed in which the upper front surface is oxidized to form the second gate oxide film 25 so as to match the thickness of the thick gate oxide film and the thin gate oxide film.

먼저, 도 1a에 도시한 바와 같이 절연영역(2)이 형성된 반도체기판(1) 상에 버퍼산화막(3)을 형성하고 상기 반도체기판(1)상에 이온을 주입한다.First, as shown in FIG. 1A, a buffer oxide film 3 is formed on a semiconductor substrate 1 on which an insulating region 2 is formed, and ions are implanted on the semiconductor substrate 1.

이때, 상기 버퍼산화막(3)은 이온주입에 따른 반도체기판(1)의 손상을 완화하기위한 것이며, 주입되는 이온에 의해 게이트의 문턱전압이 결정된다.In this case, the buffer oxide film 3 is intended to mitigate damage to the semiconductor substrate 1 due to ion implantation, and the threshold voltage of the gate is determined by the implanted ions.

그 다음, 도 1b에 도시한 바와 같이 상기 버퍼산화막(3)을 제거한후 반도체기판(1)을 산화하여 그 상부에 제 1게이트산화막(4)을 형성한다.Next, as shown in FIG. 1B, the buffer oxide film 3 is removed and the semiconductor substrate 1 is oxidized to form a first gate oxide film 4 thereon.

그 다음, 도 1c에 도시한 바와 같이 상기 구조물 상부전면에 감광막(PR1)을 형성하고, 얇은 게이트산화막이 형성될부분(B)의 제 1게이트산화막(4)이 드러나도록 패터닝한 후 드러난 제 1게이트산화막(4)을 일부 식각한다.Next, as shown in FIG. 1C, the photoresist film PR1 is formed on the upper surface of the structure, and the first gate exposed after patterning the first gate oxide film 4 of the portion B in which the thin gate oxide film is to be formed is exposed. The gate oxide film 4 is partially etched.

이때, 상기 얇은 게이트산화막이 형성될부분(B)의 제 1게이트산화막(4)을 일부 제거하기 위해 BOE(Buffered Oxide Etchant)를 이용하는데, 식각하는 양은 관계가 없지만 후속 공정에서 두꺼운 게이트산화막이 형성될 부분(A)의 제 1게이트산화막(4) 두께를 맞추면서 모두 제거될 수 있을 정도만 남긴다.In this case, a buffered oxide etchant (BOE) is used to remove a portion of the first gate oxide layer 4 of the portion B in which the thin gate oxide layer is to be formed. The etching amount is not related, but a thick gate oxide layer is formed in a subsequent process. The thickness of the first gate oxide film 4 of the portion A to be made is matched, leaving only enough to be removed.

그 다음, 도 1d에 도시한 바와 같이 상기 감광막(PR1)을 제거하고, 두꺼운 게이트산화막이 형성될 부분(A)의 제 1게이트산화막(4)의 잔량을 조절하면서 상기 얇은 게이트산화막이 형성될 부분(B)의 잔류하는 제 1게이트산화막(4)을 제거한 후 그 상부전면을 산화하여 제 2게이트산화막(25)을 형성하면서 두꺼운 게이트산화막 및 얇은 게이트 산화막의 두께를 맞춘다.Next, as shown in FIG. 1D, the photoresist film PR1 is removed, and the portion where the thin gate oxide film is to be formed while adjusting the remaining amount of the first gate oxide film 4 in the portion A in which the thick gate oxide film is to be formed. After the remaining first gate oxide film 4 in (B) is removed, the upper front surface is oxidized to form the second gate oxide film 25 while matching the thicknesses of the thick gate oxide film and the thin gate oxide film.

이때, 희석한 불화수소(HF)를 이용하여 상기 두꺼운 게이트산화막이 형성될 부분(A)의 제 1게이트산화막(4) 잔량을 조절하면서 얇은 게이트산화막이 형성될 부분(B)에 잔류하는 제 1게이트산화막(4)을 모두 제거한다.At this time, the first gate oxide film remaining in the portion B where the thin gate oxide film is to be formed while controlling the remaining amount of the first gate oxide film 4 in the portion A in which the thick gate oxide film is to be formed using diluted hydrogen fluoride (HF). All of the gate oxide film 4 is removed.

상기한 바와 같은 종래 반도체장치 제조방법은 게이트의 문턱전압을 결정하는 이온주입후 두번의 산화를 거치면서 기 주입된 불순물이온의 재분포(dopant redistribution)에 의해 얇은 게이트산화막을 가지는 소자의 문턱전압이 변화하는 문제점이 있었다.In the conventional semiconductor device manufacturing method as described above, the threshold voltage of a device having a thin gate oxide film is increased by the redistribution of impurity ions implanted through two oxidations after ion implantation to determine the threshold voltage of the gate. There was a changing problem.

본 발명은 상기한 바와 같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 이온주입 시기를 변경함으로써 얇은 산화막을 가지는 소자의 문턱전압을 이온주입시 결정한 값으로 유지할 수 있는 반도체장치 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to manufacture a semiconductor device capable of maintaining the threshold voltage of a device having a thin oxide film at a value determined during ion implantation by changing the ion implantation timing. To provide a method.

도 1은 종래 반도체장치 제조방법을 보인 수순단면도.1 is a cross-sectional view showing a conventional semiconductor device manufacturing method.

도 2는 본 발명 일실시예의 수순단면도.Figure 2 is a cross-sectional view of the procedure of an embodiment of the present invention.

*** 도면의 주요부분에 대한 부호의 설명 ****** Explanation of symbols for main parts of drawing ***

21 : 반도체기판 22 : 격리영역21: semiconductor substrate 22: isolation region

23 : 버퍼산화막 24 : 제 1게이트산화막23: buffer oxide film 24: first gate oxide film

25 : 제 2게이트산화막 PR21,PR22 : 감광막25: second gate oxide film PR21, PR22: photosensitive film

상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체장치 제조방법은 절연영역이 형성된 반도체기판상에 버퍼산화막을 형성하고, 그 구조물 상부전면에 감광막을 도포한 후 두꺼운 산화막이 형성될 부분의 버퍼산화막이 드러나도록 패터닝하고, 반도체기판상에 이온을 주입하는 제 1공정과; 상기 감광막 및 버퍼산화막을 제거한후 반도체기판을 산화하여 그 상부에 제 1 게이트산화막을 형성하는 제 2공정과; 상기 구조물 상부전면에 감광막을 형성하고, 얇은 게이트산화막이 형성될부분의 제 1게이트산화막이 드러나도록 패터닝한 후 드러난 제 1게이트산화막을 일부 식각하고, 이를 통해 얇은 게이트산화막이 형성될부분의 반도체기판상에 이온을 주입하는 제 3공정과; 상기 감광막을 제거하고, 두꺼운 게이트산화막이 형성될 부분의 제 1게이트산화막 잔량을 조절하면서 상기 얇은 게이트산화막이 형성될 부분에 잔류하는 제 1게이트산화막을 제거한 후 그 상부전면을 산화하여 제 2게이트산화막을 형성하면서 두꺼운 게이트산화막 및 얇은 게이트 산화막의 두께를 맞추는 제 4공정으로 이루어지는 것을 특징으로한다.A semiconductor device manufacturing method for achieving the object of the present invention as described above is to form a buffer oxide film on a semiconductor substrate formed with an insulating region, a photoresist film is applied to the entire upper surface of the structure, the buffer oxide film of the portion where the thick oxide film will be formed A first step of patterning such that it is exposed and implanting ions onto the semiconductor substrate; A second process of removing the photosensitive film and the buffer oxide film and oxidizing the semiconductor substrate to form a first gate oxide film thereon; After forming a photoresist film on the upper surface of the structure, patterning the first gate oxide film of the portion where the thin gate oxide film is to be exposed, the first gate oxide film is partially etched, thereby through the semiconductor substrate of the portion where the thin gate oxide film is to be formed A third step of implanting ions into the phase; The photoresist layer is removed, the first gate oxide layer remaining on the portion where the thin gate oxide layer is to be formed is removed while the remaining amount of the first gate oxide layer on the portion where the thick gate oxide layer is to be formed is removed, and the upper surface is oxidized to oxidize the second gate oxide layer. And a fourth process of matching the thicknesses of the thick gate oxide film and the thin gate oxide film with each other.

상기한 바와 같은 본 발명에의한 반도체장치 제조방법을 도 2a 내지 도 2d에 도시한 수순단면도를 일 실시예로하여 상세히 설명하면 다음과 같다.A method of manufacturing a semiconductor device according to the present invention as described above will be described in detail with reference to a cross-sectional view of the procedure shown in FIGS. 2A to 2D as an embodiment.

먼저, 도 2a에 도시한 바와 같이 절연영역(22)이 형성된 반도체기판(21)상에 버퍼산화막(23)을 형성하고, 그 구조물 상부전면에 감광막(PR21)을 도포한 후 두꺼운 산화막이 형성될 부분(A)의 버퍼산화막(23)이 드러나도록 패터닝하고, 반도체기판(21)상에 이온을 주입한다.First, as shown in FIG. 2A, the buffer oxide film 23 is formed on the semiconductor substrate 21 on which the insulating region 22 is formed, the photoresist film PR21 is coated on the upper surface of the structure, and then a thick oxide film is formed. The buffer oxide film 23 of the portion A is patterned to be exposed, and ions are implanted onto the semiconductor substrate 21.

이때, 상기 버퍼산화막(23)은 이온주입에 따른 반도체기판(21)의 손상을 완화하기위한 것이며, 주입하는 이온을 조절하여 게이트의 문턱전압을 결정하는데, 상기 과정에서는 두꺼운 산화막이 형성될 부분(A)의 반도체기판(21)에만 이온을 주입한다.In this case, the buffer oxide film 23 is to mitigate the damage of the semiconductor substrate 21 due to the ion implantation, and the threshold voltage of the gate is determined by controlling the implanted ions. Ions are implanted only into the semiconductor substrate 21 of A).

그 다음, 도 2b에 도시한 바와 같이 상기 감광막(PR21) 및 버퍼산화막(23)을 제거한후 반도체기판(21)을 산화하여 그 상부에 제 1게이트산화막(24)을 형성한다.Next, as shown in FIG. 2B, the photoresist film PR21 and the buffer oxide film 23 are removed, and the semiconductor substrate 21 is oxidized to form a first gate oxide film 24 thereon.

그 다음, 도 2c에 도시한 바와 같이 상기 구조물 상부전면에 감광막(PR22)을 형성한 후 얇은 게이트산화막이 형성될부분(B)의 제 1게이트산화막(24)이 드러나도록 패터닝한 후 드러난 제 1게이트산화막(4)을 일부 제거하고, 이를 통해 반도체기판(21)상에 이온을 주입한다.Next, as shown in FIG. 2C, after the photoresist film PR22 is formed on the upper surface of the structure, the first gate oxide film 24 of the portion B in which the thin gate oxide film is to be formed is patterned so as to be exposed. The gate oxide film 4 is partially removed, and ions are implanted onto the semiconductor substrate 21 through the gate oxide film 4.

이때, 상기 얇은 게이트산화막이 형성될부분(B)의 제 1게이트산화막(24)을 일부 제거하기 위해 BOE를 이용하는데, 식각하는 양은 관계가 없지만 후속 공정에서두꺼운 게이트산화막이 형성될 부분(A)의 제 1게이트산화막(24) 두께를 맞추면서 모두 제거될 수 있을 정도만 남기고, 이를 통해 얇은 게이트산화막이 형성될부분(B)의 반도체기판(21)상에 이온을 주입하여 문턱전압을 설정하면 얇은 게이트산화막이 형성될부분(B)에 주입되는 불순물이온은 후속공정에서 한번의 산화과정만을 거치므로 문턱전압의 변화를 방지할 수 있게 된다.In this case, BOE is used to remove part of the first gate oxide layer 24 of the portion B on which the thin gate oxide layer is to be formed. The amount of etching is irrelevant, but a portion where the thick gate oxide layer is to be formed in a subsequent process (A). The thickness of the first gate oxide film 24 of the first gate oxide film 24 may be removed, leaving only enough to be removed. Thus, when the threshold voltage is set by injecting ions onto the semiconductor substrate 21 of the portion B where the thin gate oxide film is to be formed, a thin gate is formed. Impurity ions implanted in the portion (B) where the oxide film is to be formed are prevented from changing the threshold voltage since only one oxidation process is performed in a subsequent process.

그 다음, 도 2d에 도시한 바와 같이 상기 감광막(PR22)을 제거하고, 두꺼운 게이트산화막이 형성될 부분(A)의 제 1게이트산화막(24) 잔량을 조절하면서 상기 얇은 게이트산화막이 형성될 부분(B)에 잔류하는 제 1게이트산화막(24)을 제거한 후 그 상부전면을 산화하여 제 2게이트산화막(25)을 형성하면서 두꺼운 게이트산화막 및 얇은 게이트 산화막의 두께를 맞춘다.Next, as shown in FIG. 2D, the photoresist film PR22 is removed, and the portion where the thin gate oxide film is to be formed while adjusting the remaining amount of the first gate oxide film 24 in the portion A in which the thick gate oxide film is to be formed ( After the first gate oxide film 24 remaining in B) is removed, the upper front surface is oxidized to form the second gate oxide film 25 while matching the thicknesses of the thick gate oxide film and the thin gate oxide film.

이때, 희석한 불화수소(HF)를 이용하여 상기 두꺼운 게이트산화막이 형성될 부분(A)의 제 1게이트산화막(24)의 잔량을 조절하면서 얇은 게이트산화막이 형성될 부분(B)에 잔류하는 제 1게이트산화막(24)을 모두 제거한다.At this time, by using the diluted hydrogen fluoride (HF) to adjust the remaining amount of the first gate oxide film 24 of the portion (A) where the thick gate oxide film is to be formed while remaining in the portion (B) where the thin gate oxide film is to be formed All of the one gate oxide film 24 is removed.

상기한 바와 같은 본 발명 반도체장치 제조방법은 얇은 게이트산화막이 형성되는 부분은 제 1게이트산화막이 형성된 후에 이온을 주입함으로써 상기 부분에 주입된 불순물이온은 1번의 산화과정만을 거치도록하여 얇은 산화막을 가지는 소자의 문턱전압의 변화를 방지할 수 있는 효과가 있다.In the method of manufacturing a semiconductor device of the present invention as described above, the portion where the thin gate oxide film is formed is implanted with ions after the first gate oxide film is formed, so that the impurity ions injected into the portion have only one oxidation process to have a thin oxide film. There is an effect that can prevent the change of the threshold voltage of the device.

Claims (1)

절연영역이 형성된 반도체기판상에 버퍼산화막을 형성하고, 그 구조물 상부전면에 감광막을 도포한 후 두꺼운 산화막이 형성될 부분의 버퍼산화막이 드러나도록 패터닝하고, 반도체기판상에 이온을 주입하는 제 1공정과; 상기 감광막 및 버퍼산화막을 제거한후 반도체기판을 산화하여 그 상부에 제 1 게이트산화막을 형성하는 제 2공정과; 상기 구조물 상부전면에 감광막을 형성하고, 얇은 게이트산화막이 형성될부분의 제 1게이트산화막이 드러나도록 패터닝한 후 드러난 제 1게이트산화막을 일부 식각하고, 이를 통해 얇은 게이트산화막이 형성될부분의 반도체기판상에 이온을 주입하는 제 3공정과; 상기 감광막을 제거하고, 두꺼운 게이트산화막이 형성될 부분의 제 1게이트산화막 잔량을 조절하면서 상기 얇은 게이트산화막이 형성될 부분에 잔류하는 제 1게이트산화막을 제거한 후 그 상부전면을 산화하여 제 2게이트산화막을 형성하면서 두꺼운 게이트산화막 및 얇은 게이트 산화막의 두께를 맞추는 제 4공정으로 이루어지는 것을 특징으로 하는 반도체장치 제조방법.A first process of forming a buffer oxide film on a semiconductor substrate on which an insulating region is formed, applying a photoresist film on the entire surface of the structure, patterning the buffer oxide film to reveal a thick oxide film, and injecting ions onto the semiconductor substrate. and; A second process of removing the photosensitive film and the buffer oxide film and oxidizing the semiconductor substrate to form a first gate oxide film thereon; After forming a photoresist film on the upper surface of the structure, patterning the first gate oxide film of the portion where the thin gate oxide film is to be exposed, the first gate oxide film is partially etched, thereby through the semiconductor substrate of the portion where the thin gate oxide film is to be formed A third step of implanting ions into the phase; The photoresist layer is removed, the first gate oxide layer remaining on the portion where the thin gate oxide layer is to be formed is removed while the remaining amount of the first gate oxide layer on the portion where the thick gate oxide layer is to be formed is removed, and the upper surface is oxidized to oxidize the second gate oxide layer. And forming a thick gate oxide film and a thin gate oxide film while forming a thickness.
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