KR100319631B1 - Method for forming isolation region of semiconductor device - Google Patents
Method for forming isolation region of semiconductor device Download PDFInfo
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- KR100319631B1 KR100319631B1 KR1019990026317A KR19990026317A KR100319631B1 KR 100319631 B1 KR100319631 B1 KR 100319631B1 KR 1019990026317 A KR1019990026317 A KR 1019990026317A KR 19990026317 A KR19990026317 A KR 19990026317A KR 100319631 B1 KR100319631 B1 KR 100319631B1
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- oxide film
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- eye structure
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 title claims abstract description 23
- 238000002955 isolation Methods 0.000 title description 9
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 150000004767 nitrides Chemical class 0.000 claims abstract description 20
- 239000011810 insulating material Substances 0.000 claims abstract description 14
- 230000003647 oxidation Effects 0.000 claims abstract description 7
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 7
- -1 oxygen ions Chemical class 0.000 claims abstract description 7
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 5
- 239000001301 oxygen Substances 0.000 claims abstract description 5
- 239000007772 electrode material Substances 0.000 claims abstract description 4
- 238000000206 photolithography Methods 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims description 5
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- 238000000926 separation method Methods 0.000 abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
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- E—FIXED CONSTRUCTIONS
- E04—BUILDING
- E04G—SCAFFOLDING; FORMS; SHUTTERING; BUILDING IMPLEMENTS OR AIDS, OR THEIR USE; HANDLING BUILDING MATERIALS ON THE SITE; REPAIRING, BREAKING-UP OR OTHER WORK ON EXISTING BUILDINGS
- E04G9/00—Forming or shuttering elements for general use
- E04G9/02—Forming boards or similar elements
- E04G9/05—Forming boards or similar elements the form surface being of plastics
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29B—PREPARATION OR PRETREATMENT OF THE MATERIAL TO BE SHAPED; MAKING GRANULES OR PREFORMS; RECOVERY OF PLASTICS OR OTHER CONSTITUENTS OF WASTE MATERIAL CONTAINING PLASTICS
- B29B17/00—Recovery of plastics or other constituents of waste material containing plastics
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- E—FIXED CONSTRUCTIONS
- E04—BUILDING
- E04G—SCAFFOLDING; FORMS; SHUTTERING; BUILDING IMPLEMENTS OR AIDS, OR THEIR USE; HANDLING BUILDING MATERIALS ON THE SITE; REPAIRING, BREAKING-UP OR OTHER WORK ON EXISTING BUILDINGS
- E04G17/00—Connecting or other auxiliary members for forms, falsework structures, or shutterings
- E04G17/06—Tying means; Spacers ; Devices for extracting or inserting wall ties
- E04G17/065—Tying means, the tensional elements of which are threaded to enable their fastening or tensioning
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- E—FIXED CONSTRUCTIONS
- E04—BUILDING
- E04G—SCAFFOLDING; FORMS; SHUTTERING; BUILDING IMPLEMENTS OR AIDS, OR THEIR USE; HANDLING BUILDING MATERIALS ON THE SITE; REPAIRING, BREAKING-UP OR OTHER WORK ON EXISTING BUILDINGS
- E04G9/00—Forming or shuttering elements for general use
- E04G9/02—Forming boards or similar elements
- E04G2009/028—Forming boards or similar elements with reinforcing ribs on the underside
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Abstract
본 발명은 반도체소자의 분리영역 형성방법에 관한 것으로, 종래에는 분리영역과 반도체기판의 경계영역 상부에 홈이 형성되어 그 홈에서 게이트산화막이 얇게 형성됨에 따라 소자동작시 전류가 집중되어 신뢰성이 저하되는 문제점이 있었다. 따라서, 본 발명은 반도체기판의 상부에 순차적으로 제1산화막과 질화막을 형성한 다음 사진식각공정을 통해 질화막과 제1산화막을 식각하고, 계속해서 반도체기판을 소정의 깊이로 식각하여 피지아이구조를 형성하는 공정과; 산화공정을 실시하여 상기 피지아이구조의 표면에 제2산화막을 형성한 다음 상부전면에 절연물질을 형성하는 공정과; 상기 절연물질을 평탄화하여 피지아이구조를 채운 다음 상기 반도체기판과 피지아이구조의 경계영역 상부에 산소이온을 주입하는 공정과; 상기 절연막과 제1산화막을 제거하여 노출된 반도체기판의 상부에 게이트산화막을 형성한 다음 상부전면에 게이트 전극물질을 형성하는 공정으로 이루어지는 반도체소자의 분리영역 형성방법을 통해 분리영역과 액티브영역의 경계영역 상부에서 게이트산화막의 두께를 두껍게 형성함으로써, 소자동작시 전류의 집중을 완화하여 반도체소자의 신뢰성을 향상시킬 수 있는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a separation region of a semiconductor device. In the related art, a groove is formed in an upper portion of a separation region and a boundary region of a semiconductor substrate, and a thin gate oxide film is formed therein. There was a problem. Therefore, in the present invention, the first oxide film and the nitride film are sequentially formed on the semiconductor substrate, and the nitride film and the first oxide film are etched through the photolithography process, and the semiconductor substrate is subsequently etched to a predetermined depth to form the PIG eye structure. Forming step; Performing an oxidation process to form a second oxide film on the surface of the Fiji eye structure and then forming an insulating material on the upper front surface; Flattening the insulating material to fill the PJ eye structure, and then implanting oxygen ions into an upper portion of a boundary region between the semiconductor substrate and the PJ eye structure; Forming a gate oxide film on the exposed semiconductor substrate by removing the insulating film and the first oxide film, and then forming a gate electrode material on the upper surface of the semiconductor device. By forming the thickness of the gate oxide film in the upper portion of the region, there is an effect that can reduce the concentration of current during the operation of the device to improve the reliability of the semiconductor device.
Description
본 발명은 반도체소자의 분리영역 형성방법에 관한 것으로, 특히 피지아이(profiled groove isolation : PGI) 구조의 분리영역과 액티브영역의 경계영역 상부에서 게이트산화막의 두께가 얇아짐에 따라 발생하는 게이트산화막 무결성(gate oxide integrity : GOI) 특성의 불량을 방지하기에 적당하도록 한 반도체소자의 분리영역 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an isolation region of a semiconductor device, and in particular, gate oxide film integrity generated as the thickness of the gate oxide layer becomes thinner on the boundary region of a PGI structure and an active region. The present invention relates to a method for forming an isolation region of a semiconductor device suitable for preventing poor gate oxide integrity (GOI) characteristics.
종래 반도체소자의 분리영역 형성방법을 첨부한 도1a 내지 도1e의 수순단면도를 참조하여 상세히 설명하면 다음과 같다.A detailed description will now be made with reference to the procedure cross-sectional view of FIGS. 1A to 1E attached to a method of forming a separation region of a conventional semiconductor device.
먼저, 도1a에 도시한 바와같이 반도체기판(1)의 상부에 산화막(2)과 질화막(3)을 순차적으로 형성한 후, 질화막(3)의 상부에 감광막(PR1)을 도포하고, 노광 및 현상하여 분리영역이 형성될 영역의 질화막(3)이 노출되도록 감광막(PR1) 패턴을 형성한다.First, as shown in FIG. 1A, the oxide film 2 and the nitride film 3 are sequentially formed on the semiconductor substrate 1, and then the photosensitive film PR1 is coated on the nitride film 3, and the exposure and The photosensitive film PR1 pattern is formed to expose the nitride film 3 in the region where the isolation region is to be formed.
그리고, 도1b에 도시한 바와같이 상기 감광막(PR1) 패턴을 마스크로 적용하여 질화막(3)과 산화막(2)을 식각하고, 계속해서 반도체기판(1)을 소정의 깊이로 식각하여 피지아이구조(4)를 형성한다.1B, the nitride film 3 and the oxide film 2 are etched by applying the photoresist film PR1 pattern as a mask, and the semiconductor substrate 1 is subsequently etched to a predetermined depth, so that the fiji eye structure is etched. (4) is formed.
그리고, 도1c에 도시한 바와같이 상기 감광막(PR1) 패턴을 제거하고, 산화공정을 실시하여 상기 피지아이구조(4)의 표면상에 얇은 산화막(5)을 형성한 다음 상부전면에 고밀도 플라즈마(high density plasma : HDP)를 이용한 절연물질(6)을 형성한다.As shown in FIG. 1C, the photoresist film PR1 pattern is removed, and an oxidation process is performed to form a thin oxide film 5 on the surface of the Fiji eye structure 4. Insulating material (6) is formed using high density plasma (HDP).
그리고, 도1d에 도시한 바와같이 상기 절연물질(6)을 화학기계적 연마(chemical mechanical polishing : CMP)를 통해 평탄화한 다음 상기 질화막(3)과 산화막(2)을 제거하여 반도체기판(1)을 노출시킨다. 이때, 상기 질화막(3) 및 산화막(2)이 제거됨에 따라 평탄화된 절연물질(6)과 노출된 반도체기판(1)은 소정의 단차를 갖게 되며, 또한 경계영역 상부에는 홈(7)이 형성된다.As shown in FIG. 1D, the insulating material 6 is planarized through chemical mechanical polishing (CMP), and then the nitride film 3 and the oxide film 2 are removed to remove the semiconductor substrate 1. Expose In this case, as the nitride film 3 and the oxide film 2 are removed, the planarized insulating material 6 and the exposed semiconductor substrate 1 have a predetermined step, and a groove 7 is formed on the boundary region. do.
그리고, 도1e에 도시한 바와같이 상기 노출된 반도체기판(1)의 상부에 게이트산화막(8)을 형성한 다음 상부전면에 게이트전극으로 적용되는 물질로 예를 들어 폴리실리콘(9)을 증착한다.As shown in FIG. 1E, a gate oxide film 8 is formed on the exposed semiconductor substrate 1, and then polysilicon 9 is deposited using a material applied as a gate electrode on the entire upper surface thereof. .
그러나, 상기한 바와같은 종래 반도체소자의 분리영역 형성방법은 분리영역과 반도체기판의 경계영역 상부에 홈이 형성되어 그 홈에서 게이트산화막이 얇게 형성됨에 따라 소자동작시 전류가 집중되어 신뢰성이 저하되는 문제점이 있었다.However, in the method of forming a separation region of a conventional semiconductor device as described above, a groove is formed in an upper portion of a separation region and a boundary region of the semiconductor substrate, and thus a thin gate oxide film is formed in the groove, whereby current is concentrated during operation of the device, thereby reducing reliability. There was a problem.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 분리영역과 액티브영역의 경계영역 상부에서 게이트산화막의 두께가 얇아지는 것을 방지할 수 있는 반도체소자의 분리영역 형성방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a separation region of a semiconductor device capable of preventing the thickness of the gate oxide film from thinning on the boundary region between the isolation region and the active region. It is to provide a formation method.
도1a 내지 도1e는 종래 반도체소자의 분리영역 형성방법을 보인 수순단면도.1A to 1E are cross-sectional views showing a method of forming a separation region of a conventional semiconductor device.
도2a 내지 도2f는 본 발명의 일 실시예를 보인 수순단면도.2a to 2f are cross-sectional views showing an embodiment of the present invention.
***도면의 주요부분에 대한 부호의 설명****** Explanation of symbols for main parts of drawing ***
11:반도체기판 12,15:산화막11: Semiconductor substrate 12, 15: oxide film
13:질화막 14:피지아이구조13: Nitride 14: Fiji eye structure
16:절연물질 17:이온주입영역16: Insulation material 17: Ion injection area
18:게이트산화막 19:폴리실리콘18: gate oxide film 19: polysilicon
PR11:감광막PR11: Photosensitive film
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자의 분리영역 형성방법은 반도체기판의 상부에 순차적으로 제1산화막과 질화막을 형성한 다음 사진식각공정을 통해 질화막과 제1산화막을 식각하고, 계속해서 반도체기판을 소정의 깊이로 식각하여 피지아이구조를 형성하는 공정과; 산화공정을 실시하여 상기 피지아이구조의 표면에 제2산화막을 형성한 다음 상부전면에 절연물질을 형성하는 공정과; 상기 절연물질을 평탄화하여 피지아이구조를 채운 다음 상기 반도체기판과 피지아이구조의 경계영역 상부에 산소이온을 주입하는 공정과; 상기 절연막과 제1산화막을 제거하여 노출된 반도체기판의 상부에 게이트산화막을 형성한 다음 상부전면에 게이트 전극물질을 형성하는 공정을 구비하여 이루어지는 것을 특징으로 한다.In the method of forming an isolation region of a semiconductor device as described above, a first oxide film and a nitride film are sequentially formed on an upper surface of a semiconductor substrate, and then the nitride film and the first oxide film are etched through a photolithography process. Subsequently etching the semiconductor substrate to a predetermined depth to form a fiji eye structure; Performing an oxidation process to form a second oxide film on the surface of the Fiji eye structure and then forming an insulating material on the upper front surface; Flattening the insulating material to fill the PJ eye structure, and then implanting oxygen ions into an upper portion of a boundary region between the semiconductor substrate and the PJ eye structure; And removing the insulating film and the first oxide film to form a gate oxide film on the exposed semiconductor substrate, and then forming a gate electrode material on the upper surface of the semiconductor substrate.
상기한 바와같은 본 발명에 의한 반도체소자의 분리영역 형성방법을 첨부한 도2a 내지 도2f의 수순단면도를 일 실시예로 하여 상세히 설명하면 다음과 같다.The cross-sectional view of FIG. 2A to FIG. 2F attached to the method for forming the isolation region of the semiconductor device according to the present invention as described above will be described in detail as follows.
먼저, 도2a에 도시한 바와같이 반도체기판(11)의 상부에 산화막(12)과 질화막(13)을 순차적으로 형성한 후, 질화막(13)의 상부에 감광막(PR11)을 도포하고, 노광 및 현상하여 분리영역이 형성될 영역의 질화막(13)이 노출되도록 감광막(PR11) 패턴을 형성한다.First, as shown in FIG. 2A, an oxide film 12 and a nitride film 13 are sequentially formed on the semiconductor substrate 11, and then a photoresist film PR11 is coated on the nitride film 13, followed by exposure and The photosensitive film PR11 pattern is formed to expose the nitride film 13 in the region where the isolation region is to be formed.
그리고, 도2b에 도시한 바와같이 상기 감광막(PR11) 패턴을 마스크로 적용하여 질화막(13)과 산화막(12)을 식각하고, 계속해서 반도체기판(11)을 소정의 깊이로 식각하여 피지아이구조(14)를 형성한다.As shown in FIG. 2B, the nitride film 13 and the oxide film 12 are etched by applying the photoresist film PR11 pattern as a mask, and then the semiconductor substrate 11 is etched to a predetermined depth, so that the fiji eye structure is etched. (14) is formed.
그리고, 도2c에 도시한 바와같이 상기 감광막(PR11) 패턴을 제거하고, 산화공정을 실시하여 상기 피지아이구조(14)의 표면상에 얇은 산화막(15)을 형성한 다음 상부전면에 고밀도 플라즈마를 이용한 절연물질(16)을 형성한다.As shown in FIG. 2C, the photoresist film PR11 pattern is removed, and an oxidation process is performed to form a thin oxide film 15 on the surface of the Fiji eye structure 14, and then a high density plasma is applied to the upper surface. The insulating material 16 used is formed.
그리고, 도2d에 도시한 바와같이 상기 절연물질(16)을 화학기계적 연마를 통해 평탄화한 다음 상기 반도체기판(11)과 절연물질(16)이 채워진 피지아이구조(14)의 경계영역 상부에 산소이온을 주입하여 이온주입영역(17)을 형성한다. 이때, 본 발명의 다른 예로써, 이온주입영역(17)에 불소이온(fluorine)을 주입할 수 있다.As shown in FIG. 2D, the insulating material 16 is planarized by chemical mechanical polishing, and then oxygen is formed on the upper boundary region of the Fiji eye structure 14 filled with the semiconductor substrate 11 and the insulating material 16. Ions are implanted to form the ion implantation region 17. In this case, as another example of the present invention, fluorine ions may be injected into the ion implantation region 17.
그리고, 도2e에 도시한 바와같이 상기 질화막(13)과 산화막(12)을 제거하여 반도체기판(11)을 노출시킨다.As shown in FIG. 2E, the nitride film 13 and the oxide film 12 are removed to expose the semiconductor substrate 11.
그리고, 도2f에 도시한 바와같이 상기 노출된 반도체기판(11)의 상부에 게이트산화막(18)을 형성한 다음 상부전면에 게이트전극으로 적용되는 물질로 예를 들어 폴리실리콘(19)을 증착한다. 이때, 상기 이온주입영역(17)에 주입된 산소이온 또는 불소이온은 게이트산화막(18)을 형성하기 위한 산화공정에서 다른 영역에 비해 산화가 잘 이루어지도록 하기 때문에 게이트산화막(18)이 상기 반도체기판(11)과 피지아이구조(14)의 경계영역 상부에서 두껍게 형성된다.As shown in FIG. 2F, a gate oxide film 18 is formed on the exposed semiconductor substrate 11, and then, for example, polysilicon 19 is deposited on the upper surface of the gate oxide film 18. . In this case, since the oxygen ions or the fluorine ions implanted in the ion implantation region 17 are more easily oxidized than the other regions in the oxidation process for forming the gate oxide layer 18, the gate oxide layer 18 is formed on the semiconductor substrate. It is thickly formed on the upper boundary area between the (11) and the PJI structure 14.
상기한 바와같은 본 발명에 의한 반도체소자의 분리영역 형성방법은 분리영역과 액티브영역의 경계영역 상부에서 게이트산화막의 두께를 두껍게 형성함으로써, 소자동작시 전류의 집중을 완화하여 반도체소자의 신뢰성을 향상시킬 수 있는 효과가 있다.As described above, in the method of forming a separation region of a semiconductor device according to the present invention, the thickness of the gate oxide layer is formed thicker on the boundary region between the isolation region and the active region, thereby reducing the concentration of current during device operation, thereby improving reliability of the semiconductor device. It can be effected.
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