KR20010048438A - method for forming of dual gate oxide - Google Patents
method for forming of dual gate oxide Download PDFInfo
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- KR20010048438A KR20010048438A KR1019990053124A KR19990053124A KR20010048438A KR 20010048438 A KR20010048438 A KR 20010048438A KR 1019990053124 A KR1019990053124 A KR 1019990053124A KR 19990053124 A KR19990053124 A KR 19990053124A KR 20010048438 A KR20010048438 A KR 20010048438A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
Abstract
Description
본 발명은 반도체 소자의 제조공정에 관한 것으로, 특히 듀얼 게이트 산화막의 형성공정을 간소화시키는데 적당한 듀얼 게이트 산화막의 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing process of a semiconductor device, and more particularly, to a method of forming a dual gate oxide film suitable for simplifying the process of forming a dual gate oxide film.
일반적으로 로직(LOGIC)칩에 있어서 저전력 중심의 칩으로 진행되고 있는 추세에 비추어 볼 때, 동작 전압이 낮아야 하고, 이를 위해서는 게이트 절연막의 두께도 매우 얇아야 한다.In general, the logic chip has a low power-centric chip, the operating voltage must be low, the gate insulating film thickness must be very thin.
하지만, 실제 외부전원이 들어오는 입/출력 단자에서는 매우 얇은 게이트 절연막은 사용할 수가 없다.However, a very thin gate insulating film cannot be used in an input / output terminal that actually receives an external power source.
따라서, 필요한 부분에 따라 선택적으로 게이트 산화막의 두께를 다르게 하는 듀얼 게이트 산화막의 형성공정은 필연적이다.Therefore, the formation process of the dual gate oxide film which selectively varies the thickness of the gate oxide film according to the required portion is inevitable.
이하, 첨부된 도면을 참고하여 종래의 듀얼 게이트 산화막의 형성방법을 설명하면 다음과 같다.Hereinafter, a method of forming a conventional dual gate oxide film will be described with reference to the accompanying drawings.
도 1a 내지 도 1c는 종래의 듀얼 게이트 산화막의 형성방법을 나타낸 공정단면도이다.1A to 1C are cross-sectional views illustrating a method of forming a conventional dual gate oxide film.
도 1a에 도시한 바와 같이, 반도체 기판(11)에 산화(Oxidation) 공정을 실시하여 반도체 기판(11)의 표면에 소정 두께를 갖는 제 1 게이트 산화막(12)을 형성한다.As shown in FIG. 1A, an oxide process is performed on the semiconductor substrate 11 to form a first gate oxide film 12 having a predetermined thickness on the surface of the semiconductor substrate 11.
이어, 상기 제 1 게이트 산화막(12)상에 포토레지스트(13)를 도포한 후, 노광 현상공정으로 포토레지스트(13)를 패터닝하여 제 2 게이트 산화막이 형성될 영역을 정의한다.Subsequently, after the photoresist 13 is applied on the first gate oxide film 12, the photoresist 13 is patterned by an exposure developing process to define a region in which the second gate oxide film is to be formed.
도 1b에 도시한 바와 같이, 상기 패터닝된 포토레지스트(13)를 마스크로 이용하여 상기 노출된 제 1 게이트 산화막(12)을 습식식각으로 제거한다.As shown in FIG. 1B, the exposed first gate oxide layer 12 is wet-etched using the patterned photoresist 13 as a mask.
여기서 상기 포토레지스트(13)를 마스크로 이용하여 제 1 게이트 산화막(12)을 선택적으로 제거할 때 도면에는 도시되지 않았지만 소정두께가 잔류할 수 있다.Here, when the first gate oxide film 12 is selectively removed using the photoresist 13 as a mask, a predetermined thickness may remain, although not shown in the drawing.
도 1c에 도시한 바와 같이, 상기 포토레지스트(13)를 제거하고, 상기 반도체 기판(11)에 산화공정을 실시하여 상기 노출된 반도체 기판(11)의 표면에 제 2 게이트 산화막(14)을 형성한다.As shown in FIG. 1C, the photoresist 13 is removed and an oxidation process is performed on the semiconductor substrate 11 to form a second gate oxide film 14 on the exposed surface of the semiconductor substrate 11. do.
여기서 상기 포토레지스트(12)를 제거할 때 잔류하고 있는 제 1 게이트 산화막(12)도 표면으로부터 소정두께만큼 식각되고, 상기 제 2 게이트 산화막(14) 형성시 제 1 게이트 산화막(12)도 산화되면서 두꺼운 제 1 게이트 산화막(12)이 형성되어 듀얼 게이트 산화막이 형성된다.Here, the first gate oxide film 12 remaining when the photoresist 12 is removed is also etched from the surface by a predetermined thickness, and the first gate oxide film 12 is also oxidized when the second gate oxide film 14 is formed. A thick first gate oxide film 12 is formed to form a dual gate oxide film.
즉, 상기 제 1 게이트 산화막(12)은 제 2 게이트 산화막(14)보다 두껍게 형성된다.That is, the first gate oxide film 12 is formed thicker than the second gate oxide film 14.
그러나 상기와 같은 종래의 듀얼 게이트 산화막의 형성방법에 있어서 다음과같은 문제점이 있었다.However, the above-described conventional method for forming a dual gate oxide film has the following problems.
즉, 듀얼 게이트 산화막을 형성하기 위하여 식각과 산화 공정을 반복함으로써 공정이 복잡해지고, 식각후 산화를 실시하기 때문에 콘트롤되어야 할 게이트 산화막의 두께 컨트롤이 어렵다.That is, the process is complicated by repeating the etching and oxidation processes to form the dual gate oxide film, and since the oxidation is performed after etching, it is difficult to control the thickness of the gate oxide film to be controlled.
본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로 이온주입을 이용하여 한 번의 산화공정으로 듀얼 게이트 산화막을 형성하여 공정을 간소화시키도록 한 듀얼 게이트 산화막의 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and provides a method of forming a dual gate oxide film to simplify the process by forming a dual gate oxide film in one oxidation process using ion implantation. have.
도 1a 내지 도 1c는 종래의 듀얼 게이트 산화막의 형성방법을 나타낸 공정단면도1A to 1C are cross-sectional views illustrating a method of forming a conventional dual gate oxide film.
도 2a 내지 도 2c는 본 발명에 의한 듀얼 게이트 산화막의 형성방법을 나타낸 공정단면도2A to 2C are cross-sectional views illustrating a method of forming a dual gate oxide film according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
21 : 반도체 기판 22 : 포토레지스트21 semiconductor substrate 22 photoresist
23 : 제 1 게이트 산화막 24 : 제 2 게이트 산화막23: first gate oxide film 24: second gate oxide film
상기와 같은 목적을 달성하기 위한 본 발명에 의한 듀얼 게이트 산화막의 형성방법은 반도체 기판을 제 1 영역과 제 2 영역으로 정의하는 단계와, 상기 반도체 기판의 제 1 영역에만 산소 이온을 주입하는 단계와, 상기 반도체 기판에 산화 공정을 실시하여 제 1 영역과 제 2 영역에 서로 다른 두께를 갖는 제 1 게이트 산화막 및 제 2 게이트 산화막을 동시에 형성하는 단계를 포함하여 형성함을 특징으로 한다.A method of forming a dual gate oxide film according to the present invention for achieving the above object comprises the steps of defining a semiconductor substrate as a first region and a second region, implanting oxygen ions into only the first region of the semiconductor substrate; And simultaneously forming the first gate oxide film and the second gate oxide film having different thicknesses in the first region and the second region by performing an oxidation process on the semiconductor substrate.
이하, 첨부된 도면을 참고하여 본 발명에 의한 듀얼 게이트 산화막의 형성방법을 보다 상세히 설명하면 다음과 같다.Hereinafter, a method of forming a dual gate oxide film according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명에 의한 듀얼 게이트 산화막의 형성방법을 나타낸 공정단면도이다.2A to 2C are cross-sectional views illustrating a method of forming a dual gate oxide film according to the present invention.
도 2a에 도시한 바와 같이, 반도체 기판(21)상에 포토레지스트(22)를 도포한 후, 노광 및 현상공정으로 포토레지스트(22)를 패터닝하여 제 1 게이트 산화막과 제 2 게이트 산화막이 형성될 영역을 정의한다.As shown in FIG. 2A, after the photoresist 22 is applied onto the semiconductor substrate 21, the photoresist 22 is patterned by exposure and development to form a first gate oxide film and a second gate oxide film. Define the area.
즉, 상기 포토레지스트(22)가 잔류하는 영역이 제 2 게이트 산화막이 형성될 영역이다.That is, the region where the photoresist 22 remains is the region where the second gate oxide film is to be formed.
도 2b에 도시한 바와 같이, 상기 패터닝된 포토레지스트(22)를 마스크로 이용하여 노출된 반도체 기판(21)에 산소(O2)이온을 주입한다.As shown in FIG. 2B, oxygen (O 2 ) ions are implanted into the exposed semiconductor substrate 21 using the patterned photoresist 22 as a mask.
도 2c에 도시한 바와 같이, 상기 포토레지스트(22)를 제거하고, 상기 산소 이온이 주입된 반도체 기판(21)에 산화공정을 실시하여 서로 다른 두께를 갖는 제 1 게이트 산화막(23)과 제 2 게이트 산화막(24)을 동시에 형성한다.As shown in FIG. 2C, the photoresist 22 is removed, and an oxide process is performed on the semiconductor substrate 21 into which the oxygen ions are implanted, so that the first gate oxide film 23 and the second gate oxide film 23 having different thicknesses. The gate oxide film 24 is formed at the same time.
여기서 상기 산소 이온이 주입된 반도체 기판(21)의 표면에 형성되는 제 1 게이트 산화막(23)은 산소 이온이 주입되지 않는 반도체 기판(21)의 표면에 형성되는 제 2 게이트 산화막(24)보다 두껍게 형성되어 듀얼 게이트 산화막이 형성된다.Here, the first gate oxide film 23 formed on the surface of the semiconductor substrate 21 into which the oxygen ions are implanted is thicker than the second gate oxide film 24 formed on the surface of the semiconductor substrate 21 into which the oxygen ions are not implanted. And a dual gate oxide film is formed.
즉, 산소 이온이 주입된 영역은 산소를 시드(Seed)로하여 산화 시간이 짧게 되어 같은 시간안에 산화하면 두 영역은 서로 다른 두께의 게이트 산화막이 형성된다.That is, in the region where oxygen ions are implanted, the oxidation time is shortened by using oxygen as a seed, and when the oxide is oxidized in the same time, gate oxide films having different thicknesses are formed in the two regions.
이상에서 설명한 바와 같이 본 발명에 의한 듀얼 게이트 산화막의 형성방법은 다음과 같은 효과가 있다.As described above, the method of forming the dual gate oxide film according to the present invention has the following effects.
즉, 식각과 산화의 공정을 반복해야 하는 종래의 공정을 단순화시키어 TAT를 단축시킬 수 있고, 이온을 콘트롤함으로써 크리티칼(Critical)하게 콘트롤 되어야 하는 게이트 산화막을 종래의 습식식각을 사용하는 공정에 비해보다 콘트롤이 용이하다.That is, the TAT can be shortened by simplifying the conventional process of repeating the etching and oxidation process, and the gate oxide film to be controlled critically by controlling the ions is compared with the process using the conventional wet etching. It is easier to control.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100609225B1 (en) * | 2004-12-29 | 2006-08-02 | 동부일렉트로닉스 주식회사 | Fabricating method of gate oxidation layer in semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100609225B1 (en) * | 2004-12-29 | 2006-08-02 | 동부일렉트로닉스 주식회사 | Fabricating method of gate oxidation layer in semiconductor device |
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