KR20010058582A - semiconductor package and its manufacturing method - Google Patents
semiconductor package and its manufacturing method Download PDFInfo
- Publication number
- KR20010058582A KR20010058582A KR1019990065932A KR19990065932A KR20010058582A KR 20010058582 A KR20010058582 A KR 20010058582A KR 1019990065932 A KR1019990065932 A KR 1019990065932A KR 19990065932 A KR19990065932 A KR 19990065932A KR 20010058582 A KR20010058582 A KR 20010058582A
- Authority
- KR
- South Korea
- Prior art keywords
- circuit board
- circuit
- semiconductor package
- semiconductor chip
- conductive
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73207—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
Description
본 발명은 반도체패키지 및 그 제조 방법에 관한 것으로, 더욱 상세하게 설명하면 볼그리드어레이(Ball Grid Array) 패키지 기술과 플립칩(Flip Chip) 패키지 기술을 응용한 반도체패키지 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package using a ball grid array package technology and a flip chip package technology.
통상적으로 볼그리드어레이 패키지는 써킷필름, 써킷테이프 또는 인쇄회로기판(이하 '써킷필름'으로 통칭함) 등에 반도체칩을 탑재하고, 상기 반도체칩과 써킷필름을 도전성와이어로 상호 접속한 후, 봉지재로 상기 반도체칩 등을 원사이드 몰딩하며, 입출력 단자로서 상기 써킷필름의 저면에 도전성볼을 어레이된 상태로 융착하여 제조된 반도체패키지를 말한다.In general, a ball grid array package includes a semiconductor chip mounted on a circuit film, a circuit tape or a printed circuit board (hereinafter referred to as a 'circuit film'), and interconnects the semiconductor chip and the circuit film with conductive wires, The semiconductor package is a one-side molding of the semiconductor chip and the like, and is a semiconductor package manufactured by fusion bonding conductive balls on the bottom surface of the circuit film as an input / output terminal.
한편, 플립칩 패키지는 상기와 같은 볼그리드어레이 패키지 등에서 반도체칩과 써킷필름을 접속하는 수단으로서 통상적인 도전성와이어대신 골드볼 또는 솔더볼 등의 도전성볼을 이용하여 접속한 패키지를 말한다.On the other hand, the flip chip package as a means for connecting the semiconductor chip and the circuit film in the ball grid array package as described above refers to a package connected by using conductive balls such as gold balls or solder balls instead of conventional conductive wires.
상기한 두 패키지 모두 통상 1개의 반도체칩이 탑재되며, 또한 마더보드에도 상기 1개의 반도체패키지가 실장되어 사용되고 있다.In the above two packages, one semiconductor chip is usually mounted, and one semiconductor package is mounted and used on a motherboard.
그러나 이러한 반도체패키지에 대하여 적층 가능한 반도체패키지는 아직 개시된 바 없으며, 따라서 좁은 면적의 마더보드상에서 고밀도, 고기능화한 시스템을 구현하는데는 한계가 있다.However, a stackable semiconductor package has not yet been disclosed for such a semiconductor package, and thus there is a limit in implementing a high density, highly functionalized system on a small area motherboard.
따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 볼그리드어레이 패키지 기술과 플립칩 패키지 기술을 응용하여, 반도체패키지끼리 적층가능하게 함으로써, 고밀도화 및 고기능화한 시스템을 용이하게 구현할 수 있는 반도체패키지 및 그 제조 방법을 제공하는데 있다.Accordingly, the present invention has been made to solve the above-mentioned problems, and by applying the ball grid array package technology and flip chip package technology, the semiconductor packages can be stacked, it is possible to easily implement a high-density and highly functionalized system. The present invention provides a semiconductor package and a method of manufacturing the same.
도1은 본 발명에 의한 반도체패키지를 도시한 단면도이다.1 is a cross-sectional view showing a semiconductor package according to the present invention.
도2는 본 발명에 의한 반도체패키지를 도시한 사시도이다.2 is a perspective view showing a semiconductor package according to the present invention.
도3a 내지 도3f는 본 발명에 의한 반도체패키지의 제조 방법을 도시한 설명도이다.3A to 3F are explanatory views showing a method for manufacturing a semiconductor package according to the present invention.
도4a 및 도4b는 본 발명에 의한 반도체패키지가 적층된 상태를 도시한 것이다.4A and 4B illustrate a state in which semiconductor packages according to the present invention are stacked.
- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-
100; 본 발명에 의한 반도체패키지100; Semiconductor package according to the present invention
2; 반도체칩 4; 입출력패드2; Semiconductor chip 4; I / O pad
10; 제1회로기판 12; 제1회로기판의 볼랜드10; A first circuit board 12; Borland of the First Circuit Board
14; 제1회로기판의 본드핑거 16; 제1회로기판의 필름14; Bond fingers 16 of the first circuit board; Film of the first circuit board
20; 제2회로기판 22; 제2회로기판의 볼랜드20; Second circuit board 22; Borland of the second circuit board
24; 제2회로기판의 범프랜드 26; 제2회로기판의 필름24; Bumpland 26 of the second circuit board; Film of the second circuit board
30; 도전성와이어 40; 도전성범프30; Conductive wire 40; Conductive Bump
50; 봉지재 60; 도전성볼50; Encapsulant 60; Conductive ball
상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 상면에 다수의 입출력패드가 구비된 반도체칩과; 상기 반도체칩의 하면에 접착되어 있으며, 상면에는 본드핑거를, 하면에는 볼랜드를 포함하는 회로패턴이 형성된 제1회로기판과; 상기 반도체칩의 특정 입출력패드와 상기 제1회로기판의 본드핑거를 전기적으로 접속하는 도전성와이어와; 상기 반도체칩의 상면에 위치되어 있으며, 상면에는 볼랜드를, 하면에는 범프랜드를 포함하는 회로패턴이 형성된 제2회로기판과; 상기 반도체칩의 특정 입출력패드와 상기 제2회로기판의 범프랜드를 접속하는 도전성범프와; 상기 제1회로기판과 제2회로기판 사이에 충진된 봉지재와; 상기 제1회로기판의 각 볼랜드에 융착된 다수의 도전성볼을 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the semiconductor package according to the present invention includes a semiconductor chip having a plurality of input / output pads disposed on an upper surface thereof; A first circuit board bonded to a lower surface of the semiconductor chip, and having a circuit pattern including a bond finger on an upper surface and a ball land on a lower surface thereof; Conductive wires electrically connecting a specific input / output pad of the semiconductor chip and a bond finger of the first circuit board; A second circuit board positioned on an upper surface of the semiconductor chip and having a circuit pattern including a borland on an upper surface and a bump land on a lower surface thereof; A conductive bump connecting the specific input / output pad of the semiconductor chip to the bump land of the second circuit board; An encapsulant filled between the first circuit board and the second circuit board; It characterized in that it comprises a plurality of conductive balls fused to each ball land of the first circuit board.
여기서, 상기 반도체패키지는 상,하로 적어도 2개 이상이 적층되어 이루어질 수 있다. 즉, 상기 반도체패키지는 첫 번째 반도체패키지의 제1회로기판에 형성된 도전성볼이 두 번째 반도체패키지의 제2회로기판의 볼랜드에 융착되어 상호 적층될 수 있다.Here, at least two or more semiconductor packages may be stacked up and down. That is, the semiconductor package may be laminated with each other by conductive balls formed on the first circuit board of the first semiconductor package is fused to the ball land of the second circuit board of the second semiconductor package.
상기 회로기판은 수지층을 중심으로 상,하면에 본드핑거, 범프랜드 및 볼랜드 등의 회로패턴이 형성되고, 상,하면의 회로패턴은 도전성비아홀로 서로 연결된 통상의 인쇄회로기판일 수 있다.The circuit board may include circuit patterns such as bond fingers, bump lands, and borland formed on upper and lower surfaces of the resin layer, and the upper and lower circuit patterns may be conventional printed circuit boards connected to each other by conductive via holes.
또한, 상기 회로기판은 가요성 필름에 본드핑거, 범프랜드 및 볼랜드 등의 회로패턴이 형성된 써킷필름 또는 써킷테이프일 수도 있다.In addition, the circuit board may be a circuit film or a circuit tape on which a circuit pattern such as bond finger, bump land, and borland is formed on the flexible film.
또한 상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지의 제조 방법은 상면에는 본드핑거를, 하면에는 볼랜드를 포함하는 회로패턴이 형성된 제1회로기판을 제공하고, 상기 제1회로기판의 상면에 다수의 입출력패드가 형성된 반도체칩을 접착하는 단계와; 상기 반도체칩의 특정 입출력패드와 제1회로기판의 본드핑거를 도전성와이어로 상호 접속하는 단계와; 상면에는 볼랜드를, 하면에는 범프랜드를 포함하는 회로패턴이 형성된 제2회로기판을 제공하고, 상기 제2회로기판의 범프랜드와 반도체칩의 특정 입출력패드를 도전성범프로 상호 접속하는 단계와; 상기 제1회로기판과 제2회로기판 사이를 봉지재로 충진하는 단계와; 상기 제1회로기판의 각 볼랜드에 도전성볼을 융착하는 단계를 포함하여 이루어진 것을 특징으로 한다.In addition, in order to achieve the above object, a method of manufacturing a semiconductor package according to the present invention provides a first circuit board having a circuit pattern including a bond finger on the upper surface and a borland on the lower surface, and on the upper surface of the first circuit board. Bonding a semiconductor chip having a plurality of input / output pads formed thereon; Interconnecting a specific input / output pad of the semiconductor chip and a bond finger of the first circuit board with conductive wires; Providing a second circuit board having a circuit pattern including a ball land on an upper surface and a bump land on a lower surface thereof, and interconnecting the bump land of the second circuit board and a specific input / output pad of a semiconductor chip with conductive bumps; Filling an encapsulant between the first circuit board and the second circuit board; And fusion bonding the conductive balls to each ball land of the first circuit board.
상기와 같이 하여 본 발명에 의한 반도체패키지 및 그 제조 방법에 의하면 반도체칩의 상,하면에 회로기판을 구비하고 또한 상기 회로기판의 외부로 노출되는 표면(제1회로기판의 하면, 제2회로기판의 상면)에는 도전성볼 및 볼랜드가 형성되어 있음으로써 다수의 반도체패키지가 적층 가능한 구조가 된다. 따라서, 예를 들면 SRAM, DSP, Flash Memory 칩 등을 패키징하고, 이를 다수개 적층할 수 있게 됨으로써 좁은 마더보드상에서 고밀도, 고기능화한 시스템을 구현할 수 있게 된다.According to the semiconductor package according to the present invention and the manufacturing method as described above, the circuit board is provided on the upper and lower surfaces of the semiconductor chip and is exposed to the outside of the circuit board (the lower surface of the first circuit board, the second circuit board). The conductive ball and the ball land are formed on the upper surface of the structure to form a structure in which a plurality of semiconductor packages can be stacked. Thus, for example, by packaging an SRAM, DSP, Flash Memory chip, etc., and stacking a plurality of them, a high density, high performance system can be realized on a narrow motherboard.
이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.
도1은 본 발명에 의한 반도체패키지(100)를 도시한 단면도이고, 도2는 본 발명에 의한 반도체패키지(100)를 도시한 사시도이다.1 is a cross-sectional view showing a semiconductor package 100 according to the present invention, Figure 2 is a perspective view showing a semiconductor package 100 according to the present invention.
도시된 바와 같이 중앙부에는 상면에 다수의 입출력패드(4)가 구비된 반도체칩(2)이 위치되어 있다.As shown in the drawing, a semiconductor chip 2 having a plurality of input / output pads 4 located on an upper surface thereof is positioned.
상기 반도체칩(2)의 하면에는 제1회로기판(10)이 접착제로 접착되어 있다.The first circuit board 10 is bonded to the bottom surface of the semiconductor chip 2 with an adhesive.
상기 제1회로기판(10)은 상면에는 본드핑거(14)를 하면에는 볼랜드(12)를 갖는 회로패턴을 포함하며, 상기 회로패턴은 가요성 필름(16)에 형성되어 상,하면으로 노출된 형태를 한다.The first circuit board 10 includes a circuit pattern having a bond finger 14 on an upper surface and a ball land 12 on a lower surface thereof, and the circuit pattern is formed on the flexible film 16 and exposed to upper and lower surfaces. Form.
여기서 주지된 바와 같이 상기 본드핑거(14) 및 볼랜드(12)를 포함하는 회로패턴은 통상적인 구리 박막이다. 또한 상기 볼랜드(12)에는 금(Au) 또는 은(Ag) 등이 도금될 수 있으며, 상기 볼랜드(12)에도 금(Au), 니켈(Ni) 및 팔라디엄(Pd) 등이 도금될 수 있다.As noted herein, the circuit pattern including the bond finger 14 and the borland 12 is a conventional copper thin film. In addition, gold (Au) or silver (Ag) may be plated on the borland 12, and gold (Au), nickel (Ni), and palladium (Pd) may be plated on the borland 12. .
상기 반도체칩(2)의 특정 입출력패드(4) 바람직하기로는 반도체칩(2)의 상면 둘레에 형성된 입출력패드(4)는 상기 제1회로기판(10)의 본드핑거(14)와 전기적으로 접속되어 있다. 상기 접속 수단으로서는 골드와이어나 알루미늄와이어와 같은 도전성와이어(30)가 바람직하다.Specific input / output pads 4 of the semiconductor chip 2 Preferably, the input / output pads 4 formed around the upper surface of the semiconductor chip 2 are electrically connected to the bond fingers 14 of the first circuit board 10. It is. As the connection means, a conductive wire 30 such as gold wire or aluminum wire is preferable.
상기 반도체칩(2)의 상면에는 상기 제1회로기판(10)의 넓이와 유사한 넓이를갖는 제2회로기판(20)이 위치되어 있다. 상기 제2회로기판(20)은 상면에 볼랜드(22)를, 하면에 범프랜드(24)를 포함하는 회로패턴이 형성되어 있으며, 상기 회로패턴은 가요성 필름(16)에 형성되어 상,하면으로 노출된 형태를 한다. 마찬가지로 상기 볼랜드(22) 및 범프랜드(24)를 포함하는 회로패턴은 구리박막이며, 상기 볼랜드(22) 및 범프랜드(24)에는 금, 니켈 및 팔라디엄 등이 도금될 수 있다.A second circuit board 20 having an area similar to that of the first circuit board 10 is positioned on the top surface of the semiconductor chip 2. The second circuit board 20 has a circuit pattern including a borland 22 on an upper surface and a bump land 24 on a lower surface thereof, and the circuit pattern is formed on the flexible film 16. To form exposed. Similarly, the circuit pattern including the borland 22 and the bumpland 24 is a copper thin film, and the borland 22 and the bumpland 24 may be plated with gold, nickel, and palladium.
또한, 상기 반도체칩(2)의 특정 입출력패드(4)(즉, 상기 도전성와이어(30)와 연결된 것을 제외한 나머지 입출력패드(4))와 상기 제2회로기판(20)의 범프랜드(24)는 도전성범프(40)에 의해 플립칩 방식으로 상호 접속되어 있다. 상기 도전성범프(40)는 바람직하기로 금 또는 솔더 등이 바람직하지만 여기서 그 재질을 한정하는 것은 아니다.In addition, the specific input / output pad 4 of the semiconductor chip 2 (that is, the remaining input / output pad 4 except for being connected to the conductive wire 30) and the bump land 24 of the second circuit board 20. Are interconnected in a flip chip manner by conductive bumps 40. The conductive bumps 40 are preferably gold or solder, but the material is not limited thereto.
계속해서, 상기 제1회로기판(10)과 제2회로기판(20) 사이에는 에폭시몰딩컴파운드 또는 액상봉지재같은 봉지재(50)가 충진되어 반도체칩(2), 도전성와이어(30) 및 도전성범프(40) 등을 외부환경으로부터 보호하고, 반도체패키지(100)가 일정한 형태를 갖도록 되어 있다.Subsequently, an encapsulant 50 such as an epoxy molding compound or a liquid encapsulant is filled between the first circuit board 10 and the second circuit board 20 so that the semiconductor chip 2, the conductive wire 30, and the conductive material are filled. The bumps 40 and the like are protected from the external environment, and the semiconductor package 100 has a certain shape.
또한, 상기 제1회로기판(10)의 각 볼랜드(12)에는 솔더볼과 같은 도전성볼(60)이 융착되어 있음으로써 마더보드에 표면실장이 가능하게 되어 있다.In addition, since the conductive balls 60 such as solder balls are fused to the respective ball lands 12 of the first circuit board 10, surface mounting is possible on the motherboard.
이와 같이 하여, 상기 반도체패키지(100)는 반도체칩(2)을 중심으로 그 상,하면에 제1회로기판(10) 및 제2회로기판(20)이 구비되어 있고, 상기 하면의 제1회로기판(10)에는 도전성볼(60)이 융착되어 있고, 상기 제2회로기판(20)의 상면에는 외부로 오픈된 다수의 볼랜드(22)가 형성되어 있음으로써 다수의반도체패키지(100)를 적층할 수 있게 된다.In this way, the semiconductor package 100 is provided with a first circuit board 10 and a second circuit board 20 on the upper and lower surfaces of the semiconductor package 100, and the first circuit of the lower surface. The conductive ball 60 is fused to the substrate 10, and the plurality of semiconductor packages 100 are stacked by forming a plurality of ball lands 22 that are opened to the outside of the second circuit board 20. You can do it.
여기서, 상기 회로기판은 써킷필름 및 써킷테이프에 한하여 설명하였지만, 이것으로만 한정되는 것은 아니고 딱딱한 수지층을 중심으로 상,하면에 본드핑거, 범프랜드 및 볼랜드 등의 회로패턴이 형성되고, 상,하면의 회로패턴은 도전성비아홀로 상호 연결된 통상적인 인쇄회로기판일 수도 있다.Here, the circuit board has been described with reference to the circuit film and the circuit tape. However, the circuit board is not limited thereto, and circuit patterns such as bond fingers, bump lands, and borland are formed on the upper and lower surfaces of the resin layer. The circuit pattern on the bottom surface may be a conventional printed circuit board interconnected by conductive via holes.
도3a 내지 도3f는 본 발명에 의한 반도체패키지(100)의 제조 방법을 도시한 설명도이다.3A to 3F are explanatory views showing a method of manufacturing the semiconductor package 100 according to the present invention.
먼저 도3a에 도시된 바와 같이, 상면에는 본드핑거(14)를 하면에는 볼랜드(12)를 포함하는 회로패턴이 형성된 제1회로기판(10)을 제공하고, 상기 제1회로기판(10)의 상면에는 다수의 입출력패드(4)가 형성된 반도체칩(2)을 접착제로 접착한다.First, as shown in FIG. 3A, a bond finger 14 is provided on an upper surface thereof, and a first circuit board 10 on which a circuit pattern including a ball land 12 is formed is provided on an upper surface thereof. The semiconductor chip 2 having the plurality of input / output pads 4 formed thereon is bonded to the upper surface with an adhesive.
다음, 도3b에 도시된 바와 같이 상기 반도체칩(2)의 특정 입출력패드(4)와 제1회로기판(10)의 본드핑거(14)를 골드와이어나 알루미늄와이어와 같은 도전성와이어(30)를 이용하여 상호 접속한다.Next, as shown in FIG. 3B, the bond finger 14 of the specific input / output pad 4 of the semiconductor chip 2 and the first circuit board 10 may be formed of a conductive wire 30 such as a gold wire or an aluminum wire. To interconnect.
다음, 도3c에 도시된 바와 같이 반도체칩(2)의 특정 입출력패드(4)(즉, 도전성와이어(30)와 접속되지 않은 다름 입출력패드(4))에 금 또는 솔더로서 도전성범프(40)를 형성한다.Next, as shown in FIG. 3C, the conductive bumps 40 may be formed as gold or solder on a specific input / output pad 4 (that is, another input / output pad 4 not connected to the conductive wire 30) of the semiconductor chip 2. To form.
계속해서, 도3d에 도시된 바와 같이 상기 반도체칩(2)의 상면에 제2회로기판(20)을 제공한다. 즉, 상면에는 볼랜드(22)를 하면에는 범프랜드(24)를 포함하는 회로패턴이 형성된 제2회로기판(20)을 제공하며, 이 제2회로기판(20)의범프랜드(24)와 반도체칩(2)에 형성된 도전성범프(40)를 플립칩 기술을 이용하여 상호 접속시킨다.Subsequently, as shown in FIG. 3D, a second circuit board 20 is provided on the upper surface of the semiconductor chip 2. That is, a second circuit board 20 having a circuit pattern including a bump land 24 is formed on the upper surface of the borland 22, and the bump land 24 and the semiconductor chip of the second circuit board 20 are formed on the upper surface. The conductive bumps 40 formed in (2) are interconnected using flip chip technology.
이어서, 도3e에 도시된 바와 같이 상기 제1회로기판(10)과 제2회로기판(20) 사이에 에폭시몰딩컴파운드 또는 액상봉지재와 같은 봉지재(50)를 충진함으로써 반도체칩(2), 도전성와이어(30), 도전성범프(40) 등이 외부 환경으로부터 보호되도록 하고, 반도체패키지(100)가 소정 형상으로 유지되도록 한다.Subsequently, as shown in FIG. 3E, the semiconductor chip 2 is filled by filling an encapsulant 50 such as an epoxy molding compound or a liquid encapsulant between the first circuit board 10 and the second circuit board 20. The conductive wire 30, the conductive bumps 40, and the like are protected from the external environment, and the semiconductor package 100 is maintained in a predetermined shape.
이어서, 도3f에 도시된 바와 같이 상기 제1회로기판(10)의 각 볼랜드(12)에 솔더볼과 같은 도전성볼(60)을 융착하여, 상기 반도체패키지(100)가 마더보드에 표면 실장 가능하도록 한다.Subsequently, as shown in FIG. 3F, conductive balls 60 such as solder balls are fused to each ball land 12 of the first circuit board 10 so that the semiconductor package 100 may be surface mounted on the motherboard. do.
도4a 및 도4b는 본 발명에 의한 반도체패키지(100)가 적층된 상태를 도시한 것이다.4A and 4B illustrate a state in which semiconductor packages 100 according to the present invention are stacked.
본 발명에 의한 반도체패키지(100)는 반도체칩을 중심으로 그 상,하면에 각각 회로기판이 구비되고, 상기 회로기판중 반도체칩의 상부에 위치하는 회로기판은 상부를 향해 오픈된 볼랜드가 형성되고, 반도체칩의 하부에 위치하는 회로기판은 하부에 다수의 도전성볼이 융착되어 있음으로써 상호 적층 가능한 형태를 한다. 따라서 예를 들면 SRAM이나 DSP칩을 탑재한 반도체패키지 또는 Flash Memory, SRAM, 또는 DSP칩을 탑재한 반도체패키지를 모두 적층하여 하나의 반도체패키지로 통합할 수 있게 됨으로써 고밀도, 고기능화한 시스템을 구현할 수 있게 된다.In the semiconductor package 100 according to the present invention, circuit boards are provided on upper and lower surfaces of a semiconductor chip, respectively, and the circuit boards located above the semiconductor chips are formed with a ball land open upward. The circuit board positioned below the semiconductor chip has a plurality of conductive balls bonded to the bottom thereof to form a stackable structure. Therefore, for example, a semiconductor package containing an SRAM or a DSP chip or a semiconductor package containing a Flash memory, an SRAM, or a DSP chip can be stacked and integrated into a single semiconductor package, thereby realizing a high-density and highly functional system. do.
이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.
따라서, 본 발명에 의한 반도체패키지 및 그 제조 방법에 의하면 반도체칩의 상,하면에 회로기판을 구비하고 또한 상기 회로기판의 외부로 노출되는 표면(제1회로기판의 하면, 제2회로기판의 상면)에는 도전성볼 및 볼랜드가 형성되어 있음으로써 다수의 반도체패키지가 적층 가능한 구조가 되고, 따라서, 예를 들면 SRAM, DSP, Flash Memory 칩 등을 패키징하고, 이를 다수개 적층할 수 있게 됨으로써 좁은 마더보드상에서 고밀도, 고기능화한 시스템을 구현할 수 있게 된다.Therefore, according to the semiconductor package according to the present invention and a method of manufacturing the same, a surface having upper and lower surfaces of the semiconductor chip and a surface exposed to the outside of the circuit board (the lower surface of the first circuit board, the upper surface of the second circuit board ), A conductive ball and a borland are formed to form a structure in which a plurality of semiconductor packages can be stacked. Thus, for example, a SRAM, DSP, Flash Memory chip, etc. can be packaged, and a plurality of them can be stacked, thereby providing a narrow motherboard. High density, high performance systems can be implemented on the
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1999-0065932A KR100406447B1 (en) | 1999-12-30 | 1999-12-30 | semiconductor package and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1999-0065932A KR100406447B1 (en) | 1999-12-30 | 1999-12-30 | semiconductor package and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010058582A true KR20010058582A (en) | 2001-07-06 |
| KR100406447B1 KR100406447B1 (en) | 2003-11-20 |
Family
ID=19633087
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-1999-0065932A KR100406447B1 (en) | 1999-12-30 | 1999-12-30 | semiconductor package and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100406447B1 (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0471297A (en) * | 1990-07-11 | 1992-03-05 | Nippon Chemicon Corp | Multilayer board provided with built-in component |
| JPH05211256A (en) * | 1991-08-28 | 1993-08-20 | Sony Corp | Semiconductor device |
| JPH06268141A (en) * | 1993-03-15 | 1994-09-22 | Hitachi Ltd | Mounting method for electronic circuit device |
| JPH08279570A (en) * | 1995-04-04 | 1996-10-22 | Fujitsu Ltd | Semiconductor device |
| JPH1117070A (en) * | 1997-06-20 | 1999-01-22 | Hitachi Ltd | Semiconductor device |
-
1999
- 1999-12-30 KR KR10-1999-0065932A patent/KR100406447B1/en active IP Right Grant
Also Published As
| Publication number | Publication date |
|---|---|
| KR100406447B1 (en) | 2003-11-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4808408B2 (en) | Multi-chip package, semiconductor device used for the same, and manufacturing method thereof | |
| KR100574947B1 (en) | BGA package, manufacturing method thereof and stacked package comprising the same | |
| US7679178B2 (en) | Semiconductor package on which a semiconductor device can be stacked and fabrication method thereof | |
| KR20010090379A (en) | Semiconductor package | |
| JP2003078106A (en) | Chip-stacked package and its manufacturing method | |
| KR100549311B1 (en) | Semiconductor package | |
| KR20010063236A (en) | Stack package and manufacturing method thereof | |
| KR100401019B1 (en) | semiconductor package and its manufacturing method | |
| KR100406447B1 (en) | semiconductor package and its manufacturing method | |
| KR100401018B1 (en) | attaching method of wafer for semiconductor package | |
| KR100533761B1 (en) | semi-conduSSor package | |
| KR100610916B1 (en) | Semiconductor package | |
| KR100776130B1 (en) | Stacked semiconductor package | |
| KR100610917B1 (en) | Wire bonding structure between semiconductor chip and substrate, and semiconductor package using it, and manufacturing method of the same | |
| KR100650049B1 (en) | Assembly-stacked package using multichip module | |
| KR20050027384A (en) | Chip size package having rerouting pad and stack thereof | |
| KR100708052B1 (en) | Semiconductor package | |
| KR100668939B1 (en) | Board level semiconductor device and its manufacturing method | |
| KR100381839B1 (en) | Semiconductor package | |
| KR100501878B1 (en) | Semiconductor package | |
| KR950005493B1 (en) | Method for manufacturing of semiconductor package | |
| KR20020022268A (en) | Semiconductor package | |
| KR200283421Y1 (en) | Stacked chip ceramic package device and stacked package device stacking the same | |
| KR100633884B1 (en) | Manufacturing method of semiconductor package | |
| KR20030034515A (en) | Semiconductor package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| N231 | Notification of change of applicant | ||
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20121105 Year of fee payment: 10 |
|
| FPAY | Annual fee payment |
Payment date: 20131104 Year of fee payment: 11 |
|
| FPAY | Annual fee payment |
Payment date: 20141104 Year of fee payment: 12 |
|
| FPAY | Annual fee payment |
Payment date: 20151104 Year of fee payment: 13 |
|
| FPAY | Annual fee payment |
Payment date: 20161104 Year of fee payment: 14 |
|
| FPAY | Annual fee payment |
Payment date: 20171102 Year of fee payment: 15 |