JPH08279570A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH08279570A JPH08279570A JP7078961A JP7896195A JPH08279570A JP H08279570 A JPH08279570 A JP H08279570A JP 7078961 A JP7078961 A JP 7078961A JP 7896195 A JP7896195 A JP 7896195A JP H08279570 A JPH08279570 A JP H08279570A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor device
- wiring pattern
- upper substrate
- leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、多ピン化に対応するプ
ラスチック・ボール・グリッド・アレイ（以下Ｐ−ＢＧ
Ａ）型の半導体装置に関する。近年、半導体装置は、高
機能化に伴って端子数が増加する傾向にあるため、端子
間のピッチを広くすることができ、表面実装を可能とし
たＰ−ＢＧＡ型の半導体装置が採用されるようになって
きている。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plastic ball grid array (hereinafter referred to as "P-BG") capable of increasing the number of pins.
The present invention relates to an A) type semiconductor device. In recent years, the number of terminals in semiconductor devices has tended to increase with higher functionality, so a P-BGA type semiconductor device in which the pitch between terminals can be widened and surface mounting is possible is adopted. Is starting to appear.
【０００２】[0002]
【従来の技術】図４は、従来のＰ−ＢＧＡ型半導体装置
を説明するための図であり、図４（ａ）は斜視図、図４
（ｂ）は断面図である。従来の半導体装置は、図４
（ａ）（ｂ）に示すように、配線パターン２３が印刷さ
れたプリント基板２２上に半導体素子２１が搭載され、
半導体素子２１の電極部とプリント基板２２の配線パタ
ーン２３とを電気的に接続するためにワイヤーボンディ
ングが施されている。2. Description of the Related Art FIG. 4 is a diagram for explaining a conventional P-BGA type semiconductor device. FIG. 4 (a) is a perspective view and FIG.
(B) is a sectional view. The conventional semiconductor device is shown in FIG.
As shown in (a) and (b), the semiconductor element 21 is mounted on the printed board 22 on which the wiring pattern 23 is printed,
Wire bonding is performed to electrically connect the electrode portion of the semiconductor element 21 and the wiring pattern 23 of the printed board 22.
【０００３】そして、プリント基板２２全体を覆う封止
樹脂２４によって、半導体素子２１が封止されている。
プリント基板２２は、図４（ｂ）に示すように、配線パ
ターン２３の先端部分に厚さ方向に貫通するスルーホー
ル２６が形成されており、このスルーホール２６に対応
するプリント基板２２下面に外部接続端子となる半田ボ
ール２５が設けられている。The semiconductor element 21 is sealed by a sealing resin 24 that covers the entire printed circuit board 22.
As shown in FIG. 4B, the printed circuit board 22 has a through hole 26 penetrating therethrough in the thickness direction at the tip of the wiring pattern 23. Solder balls 25 that serve as connection terminals are provided.
【０００４】即ち、半導体素子２１の信号は、電極部か
らワイヤー及び配線パターン２３、スルーホール２６を
介して、プリント基板２２下面の半田ボール２５より引
き出される。また、図示していないが、パッケージ強化
を図るために封止樹脂を金属キャップで覆うものもあ
る。That is, the signal of the semiconductor element 21 is extracted from the electrode portion through the wire and the wiring pattern 23 and the through hole 26 from the solder ball 25 on the lower surface of the printed board 22. Further, although not shown, there is also one in which the sealing resin is covered with a metal cap in order to strengthen the package.
【０００５】[0005]
【発明が解決しようとする課題】Ｐ−ＢＧＡ型の半導体
装置におけるプリント基板２２は、ガラスエポキシ等か
ら構成されており、封止樹脂２４の硬化収縮によって反
りが発生し易く、このプリント基板２２の反りにより、
半導体装置を実装基板等に実装した場合に、端部におい
て半田ボール２５と実装基板との接触不良を来すことと
なる。The printed circuit board 22 in the P-BGA type semiconductor device is made of glass epoxy or the like and warps easily due to curing shrinkage of the sealing resin 24. Due to the warp,
When the semiconductor device is mounted on a mounting board or the like, a contact failure between the solder ball 25 and the mounting board will occur at the end portion.
【０００６】このプリント基板２５の反りは、プリント
基板２５の面積が大きくなるほど起こり易くなるため、
反りを防止するためにパッケージサイズが制限されるこ
とになり、搭載される半導体素子２１の端子数もこれに
従って制限される。また、プリント基板２２下面に外部
接続端子となる半田ボール２５が設けられているため、
半導体装置を実装基板等に実装した状態では、半田ボー
ル２５は完全に隠れてしまい、実装後に電気的試験を行
うことができない。The warp of the printed circuit board 25 is more likely to occur as the area of the printed circuit board 25 increases.
The package size is limited in order to prevent warpage, and the number of terminals of the semiconductor element 21 mounted is also limited accordingly. In addition, since the solder balls 25 that serve as external connection terminals are provided on the lower surface of the printed circuit board 22,
When the semiconductor device is mounted on a mounting board or the like, the solder balls 25 are completely hidden and an electrical test cannot be performed after mounting.
【０００７】従って、複数の半導体装置を搭載したプリ
ント基板において、何らかの障害が発生した場合に、半
導体装置個別に動作試験を行うことができず、プリント
基板毎に変更しなければならない。本発明は上記課題を
解決して、大型のパッケージにおいても反りの発生を防
止すると共に、半導体装置実装後において、電気的試験
を可能にすることを目的としている。Therefore, in the case where some trouble occurs in a printed circuit board on which a plurality of semiconductor devices are mounted, it is not possible to carry out an operation test for each semiconductor device, and it is necessary to change each printed circuit board. SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems, prevent warpage even in a large package, and enable an electrical test after mounting a semiconductor device.
【０００８】[0008]
【課題を解決するための手段】上記課題を解決するため
の本発明は、配線パターン７を有するプリント基板２上
に半導体素子１が搭載され、該半導体素子１の電極部と
前記配線パターン７の一端が電気的に接続されると共
に、前記配線パターン７の他端がプリント基板２を貫通
するスルーホールを介して下面へ導出され、この導出部
分に外部接続端子となる導電性ボール５が設けられてな
るボールグリッドアレイ型の半導体装置において、前記
配線パターン７及び導電性ボール５を有し、該配線パタ
ーン７と電気的に接続される半導体素子１が搭載される
下基板２と、該下基板２に対して封止樹脂６により一定
間隔を介して平行に配置される上基板３とを備え、該上
基板３と下基板２間の封止樹脂６内の所定位置には、下
基板２の下面の導電性ボール５と上基板３の上面とを電
気的に接続する柱状のリード４が複数本設けられている
ことを特徴としている。According to the present invention for solving the above-mentioned problems, a semiconductor element 1 is mounted on a printed circuit board 2 having a wiring pattern 7, and an electrode portion of the semiconductor element 1 and the wiring pattern 7 are formed. One end is electrically connected and the other end of the wiring pattern 7 is led out to the lower surface through a through hole penetrating the printed circuit board 2, and a conductive ball 5 serving as an external connection terminal is provided at this leading portion. In the ball grid array type semiconductor device, the lower substrate 2 having the wiring pattern 7 and the conductive balls 5 and on which the semiconductor element 1 electrically connected to the wiring pattern 7 is mounted, and the lower substrate. 2 and the upper substrate 3 which is arranged in parallel with the sealing resin 6 with a constant space therebetween, and the lower substrate 2 is provided at a predetermined position in the sealing resin 6 between the upper substrate 3 and the lower substrate 2. Conductivity on the underside of Columnar leads 4 for electrically connecting the upper surface of the ball 5 and the upper substrate 3 is characterized in that provided plural.
【０００９】[0009]
【作用】上記本発明の半導体装置によれば、封止樹脂６
を介して平行に配置される上下の基板２，３を有すると
共に、この上下の基板間に柱状のリード４が両基板を支
持するように設けられているため、樹脂の硬化収縮によ
る基板の反りが防止される。According to the above semiconductor device of the present invention, the sealing resin 6
Since the upper and lower substrates 2 and 3 are arranged in parallel with each other through the columnar leads 4 and the columnar leads 4 are provided between the upper and lower substrates so as to support both substrates, the warp of the substrates due to the curing shrinkage of the resin. Is prevented.
【００１０】また、柱状のリード４は、下基板２の導電
性ボール５と上基板３の上面とを電気的に接続している
ため、半上基板３の上面に試験用端子を接触させること
によって半導体装置をプリント基板に実装した後であっ
ても、動作試験を行うことが可能となる。Further, since the columnar leads 4 electrically connect the conductive balls 5 of the lower substrate 2 and the upper surface of the upper substrate 3, the test terminals should be brought into contact with the upper surface of the half upper substrate 3. Thus, the operation test can be performed even after the semiconductor device is mounted on the printed board.
【００１１】[0011]
【実施例】以下に本発明の実施例を図面を参照しながら
詳細に説明する。図１及び図２は本発明の第１実施例を
説明するための図であり、図１（ａ）は半導体装置斜視
図、図１（ｂ）は断面図、更に図２は図１（ｂ）の部分
拡大図である。Embodiments of the present invention will be described in detail below with reference to the drawings. 1 and 2 are views for explaining a first embodiment of the present invention. FIG. 1 (a) is a perspective view of a semiconductor device, FIG. 1 (b) is a sectional view, and FIG. ) Is a partially enlarged view of FIG.
【００１２】本実施例の半導体装置は、図１（ａ）に示
すように、表面に配線パターン７が印刷された下基板２
上に半導体素子１が搭載され、半導体素子１を封止する
封止樹脂６を介して上基板３が下基板２に対して平行な
状態で備えられている。図１（ａ）は、封止樹脂６と上
基板３とを一部切り欠いた状態を示しているものであ
り、半導体素子１の電極部と配線パターン７の一端部が
ワイヤーによって電気的に接続されている。また、配線
パターン７の他端部には下基板２と上基板３とを接続す
る柱状のリード４が設けられている。As shown in FIG. 1A, the semiconductor device of this embodiment has a lower substrate 2 having a wiring pattern 7 printed on the surface thereof.
The semiconductor element 1 is mounted on the upper side, and the upper substrate 3 is provided in parallel with the lower substrate 2 via a sealing resin 6 for sealing the semiconductor element 1. FIG. 1A shows a state in which the sealing resin 6 and the upper substrate 3 are partially cut away, and the electrode portion of the semiconductor element 1 and one end portion of the wiring pattern 7 are electrically connected by a wire. It is connected. Further, a columnar lead 4 for connecting the lower substrate 2 and the upper substrate 3 is provided at the other end of the wiring pattern 7.
【００１３】リード４は、図１（ｂ）の断面図に示すよ
うに、下基板２及び上基板３をそれぞれ貫通して、上面
及び下面に導出されるように設けられている。そして、
下面側ではリード４に接触するように、半田ボール５が
形成されている。図２は、リードの詳細構造を説明する
ための第１実施例における半導体装置の部分拡大図であ
る。As shown in the sectional view of FIG. 1B, the leads 4 are provided so as to extend through the lower substrate 2 and the upper substrate 3, respectively, and lead out to the upper surface and the lower surface. And
Solder balls 5 are formed so as to contact the leads 4 on the lower surface side. FIG. 2 is a partially enlarged view of the semiconductor device in the first embodiment for explaining the detailed structure of the leads.
【００１４】下基板２と上基板３とを接続するリード４
は、それぞれの基板を貫通するスルーホール９，９’に
挿入されており、下基板２側では挿入部分が細く形成さ
ており、また、上基板３側に位置するリード先端部分に
は凹部８が形成されている。下基板２のスルーホール９
部分には、一端が半導体素子１の電極部とワイヤーによ
って接続される配線パターン７の他端が延びており、下
面には半田ボール５が設けられている。Leads 4 for connecting the lower substrate 2 and the upper substrate 3
Are inserted into through holes 9 and 9 ′ penetrating the respective substrates, the insertion portion is formed thin on the lower substrate 2 side, and the recess 8 is formed on the lead tip portion located on the upper substrate 3 side. Has been formed. Through hole 9 in lower board 2
The other end of the wiring pattern 7 whose one end is connected to the electrode portion of the semiconductor element 1 by a wire extends to the portion, and the solder ball 5 is provided on the lower surface.
【００１５】本実施例の半導体装置は、まず、配線パタ
ーン７及びスルーホール９を有する下基板２上に半導体
素子１を銀ペースト等を介して搭載した後、半導体素子
１の電極部と配線パターン７の一端部とをワイヤーボン
ディングによって接続する。次に、下基板２のスルーホ
ール９にリード４の一端を挿入すると共に、上基板３の
スルーホール９’とリード４の他端とを位置決め固定す
ることにより、上下の基板２，３がリード４によって接
続された状態とする。In the semiconductor device of the present embodiment, first, the semiconductor element 1 is mounted on the lower substrate 2 having the wiring pattern 7 and the through holes 9 with silver paste or the like, and then the electrode portion of the semiconductor element 1 and the wiring pattern. 7 is connected to one end by wire bonding. Next, by inserting one end of the lead 4 into the through hole 9 of the lower substrate 2 and positioning and fixing the through hole 9 ′ of the upper substrate 3 and the other end of the lead 4, the upper and lower substrates 2 and 3 lead. It is assumed that they are connected by 4.
【００１６】その後、モールド金型にセットした状態と
して、上下の基板２，３間にエポキシ系の封止樹脂を注
入する。この樹脂注入は、半導体装置の３辺を金型で覆
い、開口する辺より注入する、或いは４辺を金型で覆
い、上基板３に予め形成する穴より注入する等の方法に
より行う。更に、金型の代わりに、ポリイミド等からな
る耐熱テープ或いは上基板及び下基板に設ける枠体を用
いることができる。Thereafter, with the mold set, the epoxy type sealing resin is injected between the upper and lower substrates 2 and 3. This resin injection is performed by a method in which three sides of the semiconductor device are covered with a mold and injected from the opening side, or four sides are covered with a mold and injected from a hole previously formed in the upper substrate 3. Further, instead of the mold, a heat-resistant tape made of polyimide or the like or a frame body provided on the upper and lower substrates can be used.
【００１７】最後に、下基板２より下面に突出するリー
ド４を溶融する半田を溜めた半田槽に浸漬する、或いは
ディスペンサーにより半田ペーストを塗布した後熱硬化
させることで、半田ボール５を形成する。本実施例の半
導体装置によれば、半導体素子１が搭載される下基板２
と上基板３とが、リード４によって平行状態に支持さ
れ、その間に樹脂が注入されているため、樹脂の硬化収
縮による基板の反り発生を抑えることができる。Finally, the solder balls 5 are formed by immersing the leads 4 projecting from the lower surface of the lower substrate 2 in a solder bath containing melted solder, or by applying a solder paste with a dispenser and then thermally curing it. . According to the semiconductor device of the present embodiment, the lower substrate 2 on which the semiconductor element 1 is mounted
Since the upper substrate 3 and the upper substrate 3 are supported in parallel by the leads 4 and the resin is injected between them, it is possible to prevent the substrate from warping due to curing shrinkage of the resin.
【００１８】また、下基板２及び上基板３を支持してい
るリード４は、それぞれの基板を貫通して上表面及び下
面に導出されている。そのため、実装基板に実装した後
でも上表面に導出したリード４に試験用プローバ等を接
触させることによって、動作テストを行うことが可能と
なる。更に、半田ボール５とリード４の凹部８とは、凹
部８を僅かに大きくした同一形状にしており嵌合可能と
している。従って、複数の半導体装置を積層状態で実装
することができ、実装密度を向上させることが可能であ
る。Further, the leads 4 supporting the lower substrate 2 and the upper substrate 3 extend through the respective substrates and are led out to the upper surface and the lower surface. Therefore, even after mounting on the mounting board, an operation test can be performed by bringing the test prober or the like into contact with the lead 4 led out to the upper surface. Further, the solder ball 5 and the recess 8 of the lead 4 can be fitted to each other by making the recess 8 slightly larger and having the same shape. Therefore, a plurality of semiconductor devices can be mounted in a stacked state, and the mounting density can be improved.
【００１９】本実施例では、半導体素子１を下基板２上
に搭載しているが、図３の断面図に示す如く、上基板に
半導体素子を搭載することも可能である。図３は、本発
明の第２実施例を示す半導体装置断面図である。本発明
の第２実施例は、図示しない配線パターンが印刷された
上基板１３に半導体素子１１が搭載されて、配線パター
ンと半導体素子１１の電極部とがワイヤーボンディング
によって接続されている。In this embodiment, the semiconductor element 1 is mounted on the lower substrate 2, but it is also possible to mount the semiconductor element on the upper substrate as shown in the sectional view of FIG. FIG. 3 is a sectional view of a semiconductor device showing a second embodiment of the present invention. In the second embodiment of the present invention, the semiconductor element 11 is mounted on the upper substrate 13 on which a wiring pattern (not shown) is printed, and the wiring pattern and the electrode portion of the semiconductor element 11 are connected by wire bonding.
【００２０】上基板１３は、これと平行状態で下基板１
２とリード１４によって支持されており、両基板間に封
止樹脂１６が注入されている。そして、下基板１２のリ
ード４に対応する位置には、外部接続端子となる半田ボ
ール１５が浸漬によって形成されている。本実施例にお
いても、第１実施例と同様、基板の反りを抑えることが
できると共に、実装後の試験が可能になるという効果を
得ることができる。The upper substrate 13 is in parallel with the lower substrate 1
2 and leads 14 and a sealing resin 16 is injected between both substrates. Then, at a position corresponding to the lead 4 of the lower substrate 12, a solder ball 15 serving as an external connection terminal is formed by immersion. Also in this embodiment, as in the first embodiment, it is possible to obtain an effect that the warp of the substrate can be suppressed and a test after mounting becomes possible.
【００２１】[0021]
【効果】以上説明した本発明による半導体装置によれ
ば、上下の基板が柱状のリードによって支持される構造
であるため、半導体素子を搭載するプリント基板を大型
化しても、この基板の反りの発生を防止することができ
る。また、柱状のリードが下基板の導電性ボールと上基
板の上面とを電気的に接続しているため、半上基板３の
上面に試験用端子を接触させることによって半導体装置
を実装基板に実装した後であっても、動作試験を行うこ
とが可能となる。According to the semiconductor device of the present invention described above, since the upper and lower substrates are supported by the columnar leads, even if the printed circuit board on which the semiconductor element is mounted is upsized, the warp of the substrate occurs. Can be prevented. Further, since the columnar leads electrically connect the conductive balls of the lower substrate and the upper surface of the upper substrate, the semiconductor device is mounted on the mounting substrate by bringing the test terminals into contact with the upper surface of the half upper substrate 3. Even after the operation, the operation test can be performed.
【図１】本発明の第１実施例を説明するための半導体装
置斜視図及び断面図である。FIG. 1 is a perspective view and a cross-sectional view of a semiconductor device for explaining a first embodiment of the present invention.
【図２】本発明の第１実施例を説明するための半導体装
置部分断面図である。FIG. 2 is a partial cross-sectional view of a semiconductor device for explaining the first embodiment of the present invention.
【図３】本発明の第２実施例を説明するための半導体装
置断面図である。FIG. 3 is a sectional view of a semiconductor device for explaining a second embodiment of the present invention.
【図４】従来の半導体装置を説明するための斜視図及び
断面図である。FIG. 4 is a perspective view and a cross-sectional view for explaining a conventional semiconductor device.
Claims (3)
板（２）上に半導体素子（１）が搭載され、該半導体素
子（１）の電極部と前記配線パターン（７）の一端が電
気的に接続されると共に、前記配線パターン（７）の他
端がプリント基板（２）を貫通するスルーホールを介し
て下面へ導出され、この導出部分に外部接続端子となる
導電性ボール（５）が設けられてなるボールグリッドア
レイ型の半導体装置において、 前記配線パターン（７）及び導電性ボール（５）を有
し、該配線パターン（７）と電気的に接続される半導体
素子（１）が搭載される下基板（２）と、該下基板
（２）に対して封止樹脂（６）により一定間隔を介して
平行に配置される上基板（３）とを備え、 該上基板（３）と下基板（２）間の封止樹脂（６）内の
所定位置には、下基板（２）の下面の導電性ボール
（５）と上基板（３）の上面とを電気的に接続する柱状
のリード（４）が複数本設けられていることを特徴とす
る半導体装置。1. A semiconductor element (1) is mounted on a printed circuit board (2) having a wiring pattern (7), and an electrode portion of the semiconductor element (1) and one end of the wiring pattern (7) are electrically connected. While being connected, the other end of the wiring pattern (7) is led out to the lower surface through a through hole penetrating the printed board (2), and a conductive ball (5) serving as an external connection terminal is provided at this leading portion. A ball grid array type semiconductor device obtained by mounting the semiconductor element (1) having the wiring pattern (7) and the conductive balls (5) and electrically connected to the wiring pattern (7). A lower substrate (2) and an upper substrate (3) arranged in parallel to the lower substrate (2) with a sealing resin (6) at a constant interval, the upper substrate (3) and Predetermined position in the sealing resin (6) between the lower substrate (2) Is provided with a plurality of columnar leads (4) for electrically connecting the conductive balls (5) on the lower surface of the lower substrate (2) and the upper surface of the upper substrate (3). Semiconductor device.
３を貫通して上基板表面に露出することで、試験用の接
触端子になっていることを特徴とする請求項１記載の半
導体装置。2. The columnar lead (4) functions as a contact terminal for testing by penetrating the upper substrate 3 and being exposed on the surface of the upper substrate. Semiconductor device.
３の表面に露出する部分に凹部（８）が形成され、下基
板（２）の導電性ボール（５）が嵌合可能になっている
ことを特徴とする請求項２記載の半導体装置。3. The columnar lead (4) has a recess (8) formed in a portion exposed on the surface of the upper substrate (3) so that the conductive ball (5) of the lower substrate (2) can be fitted therein. The semiconductor device according to claim 2, wherein:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7078961A JPH08279570A (en) | 1995-04-04 | 1995-04-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7078961A JPH08279570A (en) | 1995-04-04 | 1995-04-04 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08279570A true JPH08279570A (en) | 1996-10-22 |
Family
ID=13676498
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7078961A Withdrawn JPH08279570A (en) | 1995-04-04 | 1995-04-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08279570A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100406447B1 (en) * | 1999-12-30 | 2003-11-20 | 앰코 테크놀로지 코리아 주식회사 | semiconductor package and its manufacturing method |
| CN102208390A (en) * | 2011-05-19 | 2011-10-05 | 中国科学院微电子研究所 | High-density bump substrate and manufacturing method thereof |
| CN102208372A (en) * | 2011-05-19 | 2011-10-05 | 中国科学院微电子研究所 | High-density conducting channel base plate and manufacturing method thereof |
| CN103762206A (en) * | 2014-01-07 | 2014-04-30 | 申宇慈 | Electronic device interconnection body |
| JP2014197597A (en) * | 2013-03-29 | 2014-10-16 | ローム株式会社 | Semiconductor device |
-
1995
- 1995-04-04 JP JP7078961A patent/JPH08279570A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100406447B1 (en) * | 1999-12-30 | 2003-11-20 | 앰코 테크놀로지 코리아 주식회사 | semiconductor package and its manufacturing method |
| CN102208390A (en) * | 2011-05-19 | 2011-10-05 | 中国科学院微电子研究所 | High-density bump substrate and manufacturing method thereof |
| CN102208372A (en) * | 2011-05-19 | 2011-10-05 | 中国科学院微电子研究所 | High-density conducting channel base plate and manufacturing method thereof |
| JP2014197597A (en) * | 2013-03-29 | 2014-10-16 | ローム株式会社 | Semiconductor device |
| CN103762206A (en) * | 2014-01-07 | 2014-04-30 | 申宇慈 | Electronic device interconnection body |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20020604 |