JPS6240749A - Pin grid array - Google Patents

Pin grid array

Info

Publication number
JPS6240749A
JPS6240749A JP18090185A JP18090185A JPS6240749A JP S6240749 A JPS6240749 A JP S6240749A JP 18090185 A JP18090185 A JP 18090185A JP 18090185 A JP18090185 A JP 18090185A JP S6240749 A JPS6240749 A JP S6240749A
Authority
JP
Japan
Prior art keywords
wiring board
pins
pin
grid array
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18090185A
Other languages
Japanese (ja)
Other versions
JPH0533535B2 (en
Inventor
Akira Konishi
小西 昭
Teruo Wakano
輝男 若野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
I Pex Inc
Original Assignee
Dai Ichi Seiko Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Ichi Seiko Co Ltd filed Critical Dai Ichi Seiko Co Ltd
Priority to JP18090185A priority Critical patent/JPS6240749A/en
Priority to EP86108770A priority patent/EP0218796B1/en
Priority to DE8686108770T priority patent/DE3675321D1/en
Priority to US06/880,832 priority patent/US4823234A/en
Priority to KR1019860006161A priority patent/KR870002647A/en
Priority to CN198686105249A priority patent/CN86105249A/en
Publication of JPS6240749A publication Critical patent/JPS6240749A/en
Publication of JPH0533535B2 publication Critical patent/JPH0533535B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the thickness and the cost of a pin grid array by using a circuit board and sealingly molding the board integrally with pins and a heat sink with a mold. CONSTITUTION:The heads of stepped pins 2 are engaged with through holes 7 of a circuit board 1, the pins 2 are calked with the heads 2b of the pins 2 to be secured to the board 1, and a wiring pattern and the pins 2 are simultaneously electrically connected. The board 1 is disposed in a cavity 17 of a lower mold 15, a heat sink 3 is set to coat the hole 5 of the board 1, an upper mold 18 is then moved down to close the molds, heat resistant resin is injected to the cavity 17, sealed and molded to be manufactured.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、ピングリッドアレイに関する。[Detailed description of the invention] (Industrial application field) The present invention relates to pin grid arrays.

(従来の技術) 従来、半導体装置のパッケージとして、デュアルインラ
インパッケージ(以下、DIPという。)が大部分を占
めていたが、最近のLSIチップの高集積化や電子装置
の小型化、高性能化に対する要求の増大により装置のピ
ン数が増大するようになり、DIPではピン数の増加に
限界があるため、最近では、セラミック基板にピンを複
数列立設したピングリッドアレイが開発され、実用に供
されてきている。
(Prior art) Traditionally, dual in-line packages (hereinafter referred to as DIPs) have been the most popular semiconductor device package, but recently, LSI chips have become more highly integrated, and electronic devices have become smaller and more sophisticated. The number of pins in devices has increased due to increasing demands on devices, and since there is a limit to increasing the number of pins in DIP, recently a pin grid array, which has multiple rows of pins on a ceramic substrate, has been developed and put into practical use. It has been provided.

(発明が解決しようとする問題点) しかしながら、従来のピングリッドアレイパッケージは
、セラミック製基板を採用しているため、コストが高く
、しかも基板を大きくすると共に、回路を微細化するこ
とは困難であるという問題がある。このため、プリント
配線基板技術を応用した比較的安価なプラスチック製の
ピングリッドアレイが開発されているが、製造工程での
管理を厳しくしなければ高精度のものが得られず、また
熱伝導を高めるため金属製放熱板を組み込むと、接合工
程や接合部の封止工程など製造工程が増加するなどの問
題があった。
(Problems to be solved by the invention) However, since conventional pin grid array packages use ceramic substrates, they are expensive, and it is difficult to increase the size of the substrate and miniaturize the circuits. There is a problem. For this reason, relatively inexpensive plastic pin grid arrays have been developed using printed wiring board technology, but high precision cannot be obtained without strict control during the manufacturing process. If a metal heat sink was incorporated to increase the heat dissipation, there were problems such as an increase in manufacturing processes such as bonding and sealing of joints.

(問題点を解決するための手段) 本発明は、前記問題を解決する手段として、開口部を有
するプラスチック製ベースフィルムの表面に配線パター
ンを形成してなる配線基板と、該配線基板に立設され前
記配線パターンに接続された複数のピンと、前記配線基
板の開口部を覆うように配線基板上に配置された金属製
放熱板の周縁部とを耐熱性樹脂で封止して一体化してな
ることを特徴とするピングリッドアレイを提供するしの
である。
(Means for Solving the Problems) As a means for solving the above-mentioned problems, the present invention provides a wiring board in which a wiring pattern is formed on the surface of a plastic base film having an opening, and A plurality of pins connected to the wiring pattern and a peripheral edge of a metal heat sink placed on the wiring board so as to cover the opening of the wiring board are sealed and integrated with a heat-resistant resin. Shino provides a pin grid array characterized by:

(作用) 本発明は、配線基板と、ピンと、放熱板とを封入成形し
て−・体化することによりピングリッドアレイの信頼性
を高めると同時に、製造工程の簡略化を図り低コスト化
を図るものであり、プラスチック製のベースフィルムか
らなる配線基板は半導体装置の薄型化に寄与し、放熱板
は放熱板として機能し、配線基板の開口部から露出して
いる放熱板の表面に装着される半導体チップからの熱放
散性を高め、また耐熱性樹脂は配線基板を放熱板及びピ
ンと共に一体に封正し、機械的強度、耐熱衝撃性及び加
工精度の向上、製造工程の簡略化に寄与ずろ。
(Function) The present invention improves the reliability of the pin grid array by encapsulating and molding the wiring board, pins, and heat sink, and at the same time, simplifies the manufacturing process and reduces costs. The wiring board made of a plastic base film contributes to the thinning of semiconductor devices, and the heat sink functions as a heat sink and is attached to the surface of the heat sink exposed through the opening of the wiring board. In addition, the heat-resistant resin seals the wiring board together with the heat sink and pins, contributing to improved mechanical strength, thermal shock resistance, processing accuracy, and simplified manufacturing process. Zuro.

(実施例) 以下、本発明の実施例について添付の図面を参照して説
明する。
(Example) Hereinafter, an example of the present invention will be described with reference to the accompanying drawings.

本発明に係るピングリッドアレイの一実施例を示す図に
おいて、1はポリイミド樹脂、エポキシ樹脂などのプラ
スデック材料製ベースフィルムからなる配線基板、2は
良導電性金属材料からなるピン、3は銅又はアルミニウ
ムなど良熱伝導性金属材料からなる放熱板、4は配線基
板と、ピンと放熱板とを一体に封じ込める封止部で、ポ
リフェニレンザルファイド、エポキシ樹脂などの耐熱性
樹脂から形成されている。
In the diagram showing an embodiment of the pin grid array according to the present invention, 1 is a wiring board made of a base film made of a plus deck material such as polyimide resin or epoxy resin, 2 is a pin made of a highly conductive metal material, and 3 is copper. Alternatively, the heat sink is made of a metal material with good heat conductivity such as aluminum, and 4 is a sealing part that integrally seals the wiring board, the pins, and the heat sink, and is made of a heat-resistant resin such as polyphenylene sulfide or epoxy resin.

配線基板lは、その中央部に開口部5を有し、そのベー
スフィルムの表面に、第2図に示すように、開口部5の
近傍から放射状に伸張した配線パターン6を形成したも
ので、ベースフィルム及び配線パターン6を貫通して複
数の貫通孔7か形成されている。
The wiring board l has an opening 5 in the center thereof, and a wiring pattern 6 extending radially from the vicinity of the opening 5 is formed on the surface of the base film, as shown in FIG. A plurality of through holes 7 are formed through the base film and the wiring pattern 6.

本発明に係るピングリッドアレイは、配線基板lが薄肉
のプラスチックフィルムで形成されているため、配線基
板と配線パターンとの接合強度が低く、そのため配線パ
ターンとピンをハンダ付けしてもその強度は向上せず、
しかもハンダ付けによる面接会では、ハンダ付は加工が
繁雑で、ハンダ付は加工後に洗浄工程が必要になること
から、ピン2の取り付けの容易化を図り、ピン2を確実
に固定するため、貫通孔7の周囲の配線パターン6をリ
ング状に形成する一方、貫通孔7に嵌入されるピン2の
頭部側近傍に大径の段部2aを形成し、頭部2bを配線
基板lの貫通孔7に挿入した後、ハンマーリング等によ
りかしめて、その頭部2bと段部2aとの間に配線基板
■を挟持させることによりピン2を配線基板1に固定す
ると共に、配線パターン6に接続するようにしている。
In the pin grid array according to the present invention, since the wiring board l is formed of a thin plastic film, the bonding strength between the wiring board and the wiring pattern is low, so even if the wiring pattern and the pins are soldered, the strength is low. no improvement,
Moreover, in interviews using soldering, soldering requires complicated processing and requires a cleaning process after processing. While the wiring pattern 6 around the hole 7 is formed in a ring shape, a large-diameter stepped portion 2a is formed near the head side of the pin 2 to be inserted into the through hole 7, and the head 2b is formed to pass through the wiring board l. After inserting into the hole 7, the pin 2 is fixed to the wiring board 1 by caulking with a hammer ring or the like, and the wiring board ■ is held between the head part 2b and the stepped part 2a, and the pin 2 is connected to the wiring pattern 6. I try to do that.

放熱板3は配線基板lの開口部5に面する側に該開口部
5とほぼ同面積の凹所9が形成される一方、周縁部3a
に突起!0が形成され、周縁部3aを配線基板1及びピ
ン2と耐熱性樹脂で封入成形することにより配線基板l
及びピン2と一体化されている。なお、11はスタンド
オフで、ピングリッドアレイをピンソケットやマザー基
板等に装着した際、マザー基板等との間に一定の間隔を
あけるためのもので、ピングリッドアレイの任意の位置
にそれぞれ封止部4と一体成形されている。
The heat dissipation plate 3 has a recess 9 having approximately the same area as the opening 5 on the side facing the opening 5 of the wiring board l, and a peripheral edge 3a.
A protrusion! 0 is formed, and by sealing and molding the peripheral portion 3a with the wiring board 1 and the pins 2 with heat-resistant resin, the wiring board l is formed.
and is integrated with pin 2. In addition, 11 is a standoff, which is used to leave a certain distance between the pin grid array and the mother board when it is attached to a pin socket, mother board, etc., and can be sealed at any position on the pin grid array. It is integrally molded with the stop portion 4.

また、封止部4にはピン2の頭部2bに達する穴I2が
形成されているが、この穴12は封入成形時にピン2を
抑圧固定する可動ピン19により形成される。20は防
湿用保護皮膜で、エポキソ系あるいはポリイミド系樹脂
をコーティングすることにより形成されている。
Further, a hole I2 reaching the head 2b of the pin 2 is formed in the sealing portion 4, and this hole 12 is formed by a movable pin 19 that suppresses and fixes the pin 2 during encapsulation molding. Reference numeral 20 denotes a moisture-proof protective film, which is formed by coating with epoxo-based or polyimide-based resin.

前記構造のピングリッドアレイは次のようにして製造で
きる。即ち、予め用意した段付きのピン2の頭部2bを
配線基板lの貫通孔7に嵌入し、ピン2の頭部2bに振
動やハンマーリングによりピン2をかしめて、配線基板
lにピン2を固定すると同時に配線パターンとピン2と
を電気的に接続する。この配線基板Iは、第3図に示す
ように、下型15のキャビティ17内に配置され、放熱
板3を配線基板lの開口部5を覆うようにセットした後
、上型I8を降下させて型閉めし、耐熱性樹脂をキャビ
ティ17に射出して封入成形することにより製造できる
The pin grid array having the above structure can be manufactured as follows. That is, the stepped head 2b of the pin 2 prepared in advance is inserted into the through hole 7 of the wiring board l, and the pin 2 is crimped onto the head 2b of the pin 2 by vibration or hammering, and the pin 2 is attached to the wiring board l. At the same time, the wiring pattern and pin 2 are electrically connected. As shown in FIG. 3, this wiring board I is placed in the cavity 17 of the lower mold 15, and after setting the heat sink 3 so as to cover the opening 5 of the wiring board I, the upper mold I8 is lowered. It can be manufactured by closing the mold, injecting heat-resistant resin into the cavity 17, and enclosing it.

なお、配線基板の製造は、まずベースフィルムにスリッ
ト加工を施し、脱脂、乾燥後、化学銅メッキの付着を容
易にするためベースフィルムの全面に触媒ペーストを塗
布、乾燥させた後、スタンピング加工し、配線パターン
6を形成すべき部位以外の部位にレジストインキをスク
リーン印刷してマスクし、次いで化学銅メッキ法に上り
銅メッキを施し、該銅メツキ上に電気銅メッキ、電気銀
メッキを積層して配線パターンを形成し、配線パターン
6の表面とレジストインキ層との間に凹凸の無い平滑な
配線基板とするのが好ましいが、公知のフレギシブル印
刷配線基板の製造方法と同様にして製造することもでき
る。
In the manufacturing of wiring boards, the base film is first slit, then degreased and dried. Catalyst paste is applied to the entire surface of the base film to facilitate the adhesion of chemical copper plating. After drying, stamping is performed. , screen print resist ink on areas other than those where the wiring pattern 6 is to be formed to mask them, then apply copper plating using a chemical copper plating method, and layer electrolytic copper plating and electrolytic silver plating on the copper plating. Although it is preferable to form a wiring pattern by using a method of manufacturing a wiring pattern 6 to form a smooth wiring board with no unevenness between the surface of the wiring pattern 6 and the resist ink layer, it is preferable to manufacture the wiring board in the same manner as a known method for manufacturing a flexible printed wiring board. You can also do it.

本発明は、前記実施例に限定されるらのではなく、種々
に変形ずろことかできろ。例えば、前記実施例では、段
付きピン2として一端側に一重の段を有するピンを採用
しているが、これは第4図に示すように、ピン2に段を
二重にあるいは3重以上設け、頭部2b側の段部2aと
頭部2bとの間で配線基板lをかしめる一方、その段部
2aとその下側の段部2a’との間に形成される空間部
2Cに耐熱性樹脂を廻り込ませてピン2の引抜力を一段
と向上させること乙できる。
The present invention is not limited to the embodiments described above, but may be modified in various ways. For example, in the above embodiment, a pin having a single step on one end is used as the stepped pin 2, but as shown in FIG. The wiring board l is caulked between the step 2a on the side of the head 2b and the head 2b, while the space 2C formed between the step 2a and the step 2a' on the lower side is The pulling force of the pin 2 can be further improved by wrapping the heat-resistant resin around it.

また、配線基板lの配線パターン6と反対側の表面に貫
通孔を包囲する金属リングを形成し、該金属リングをし
ベースフィルム及び配線パターン6と共に、ピン2の頭
部と段部2aとの間に挾持させ、ピン2をより強固に取
り付けることができるようにしても良い。
Further, a metal ring surrounding the through hole is formed on the surface of the wiring board l opposite to the wiring pattern 6, and the metal ring is used to connect the head of the pin 2 and the stepped portion 2a together with the base film and the wiring pattern 6. It is also possible to sandwich the pin 2 between them so that the pin 2 can be more firmly attached.

さらに、前記実施例では、配線基板lに一つの開口部5
を形成し、一つの半導体チップを装着できるようにして
いるが、第5図に示すように、二つの開口部5を設ける
か、あるいはそれ以上の数の開口部5を設け、各開口部
5から露出している放熱板3の表面に半導体チップをそ
れぞれ搭載するようにすることムできる。
Furthermore, in the embodiment, one opening 5 is provided in the wiring board l.
However, as shown in FIG. 5, two or more openings 5 are provided, and each opening 5 is Semiconductor chips can be respectively mounted on the surface of the heat sink 3 exposed from the inside.

(発明の効果) 以上の説明から明らかなように、本発明によれば、配線
基板を使用し、金型を用いて配線基板をピン及び放熱板
と一体に封入成形するようにしたので、ピングリッドア
レイの薄型化及び低コスト化を図ることができ、しかも
50μm程度の高寸法精度で信頼性の高いピングリッド
アレイを製造できる。また、封止部と放熱板が配線基板
と一体化されているため、曲げ強度、耐機械的衝撃性及
び耐熱衝撃性に優れ、しかも熱放散性に優れたピングリ
ッドアレイを製造できるなど優れた効果が得られる。
(Effects of the Invention) As is clear from the above description, according to the present invention, a wiring board is used and the wiring board is integrally molded with the pins and the heat sink using a mold. It is possible to reduce the thickness and cost of the grid array, and to manufacture a highly reliable pin grid array with high dimensional accuracy of about 50 μm. In addition, since the sealing part and the heat sink are integrated with the wiring board, it is possible to manufacture pin grid arrays with excellent bending strength, mechanical shock resistance, and thermal shock resistance, as well as excellent heat dissipation properties. Effects can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明に係るピングリッドアレイの断面図、第
2図は本発明に係るピングリッドアレイの製造に使用す
る配線基板の平面図、第3図はその製造過程における封
入成形時の金型の断面説明図、第4図は本発明の他の実
施例を示すピングリッドアレイの部分断面図、第5図は
本発明の他の実施例を示すピングリッドアレイの底面図
である。 1〜配線基板 2〜段付きピン 3〜放熱板 、1〜耐熱性樹脂 5〜開口部 6〜配線パターン 7〜貫通孔 10〜突起 特 許 出 願 人  第−精工株式会社代 理 人 
弁理士  前出 葆ほか2名第3図 第4図 第5図 へ
FIG. 1 is a cross-sectional view of the pin grid array according to the present invention, FIG. 2 is a plan view of a wiring board used in manufacturing the pin grid array according to the present invention, and FIG. 3 is a cross-sectional view of the pin grid array according to the present invention. FIG. 4 is a partial sectional view of a pin grid array showing another embodiment of the invention, and FIG. 5 is a bottom view of the pin grid array showing another embodiment of the invention. 1 ~ Wiring board 2 ~ Stepped pin 3 ~ Heat sink, 1 ~ Heat resistant resin 5 ~ Opening 6 ~ Wiring pattern 7 ~ Through hole 10 ~ Protrusion Patent Applicant Dai-Seiko Co., Ltd. Agent
Patent attorney: Mr. Hajime and 2 others Go to Figure 3, Figure 4, Figure 5

Claims (1)

【特許請求の範囲】[Claims] (1)開口部を有するプラスチック製ベースフィルムの
表面に配線パターンを形成してなる配線基板と、該配線
基板に立設され前記配線パターンに接続された複数のピ
ンと、前記配線基板の開口部を覆うように配線基板上に
配置された金属製放熱板の周縁部とを耐熱性樹脂で封止
して一体化してなることを特徴とするピングリッドアレ
イ。
(1) A wiring board formed by forming a wiring pattern on the surface of a plastic base film having an opening, a plurality of pins erected on the wiring board and connected to the wiring pattern, and an opening in the wiring board. A pin grid array characterized in that it is formed by sealing and integrating with a heat-resistant resin the peripheral edge of a metal heat sink placed on a wiring board so as to cover it.
JP18090185A 1985-08-16 1985-08-16 Pin grid array Granted JPS6240749A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP18090185A JPS6240749A (en) 1985-08-16 1985-08-16 Pin grid array
EP86108770A EP0218796B1 (en) 1985-08-16 1986-06-27 Semiconductor device comprising a plug-in-type package
DE8686108770T DE3675321D1 (en) 1985-08-16 1986-06-27 SEMICONDUCTOR ARRANGEMENT WITH PACK OF PIN PLUG TYPE.
US06/880,832 US4823234A (en) 1985-08-16 1986-07-01 Semiconductor device and its manufacture
KR1019860006161A KR870002647A (en) 1985-08-16 1986-07-28 Semiconductor device and manufacturing method
CN198686105249A CN86105249A (en) 1985-08-16 1986-08-16 Semiconductor device and manufacturing thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18090185A JPS6240749A (en) 1985-08-16 1985-08-16 Pin grid array

Publications (2)

Publication Number Publication Date
JPS6240749A true JPS6240749A (en) 1987-02-21
JPH0533535B2 JPH0533535B2 (en) 1993-05-19

Family

ID=16091288

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18090185A Granted JPS6240749A (en) 1985-08-16 1985-08-16 Pin grid array

Country Status (1)

Country Link
JP (1) JPS6240749A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62189742A (en) * 1986-02-14 1987-08-19 Matsushita Electric Works Ltd Pin grid array
JPS62189743A (en) * 1986-02-14 1987-08-19 Matsushita Electric Works Ltd Wiring circuit unit
JPH01201941A (en) * 1988-02-05 1989-08-14 Citizen Watch Co Ltd Resin sealing pin grid array and manufacture thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62189742A (en) * 1986-02-14 1987-08-19 Matsushita Electric Works Ltd Pin grid array
JPS62189743A (en) * 1986-02-14 1987-08-19 Matsushita Electric Works Ltd Wiring circuit unit
JPH01201941A (en) * 1988-02-05 1989-08-14 Citizen Watch Co Ltd Resin sealing pin grid array and manufacture thereof

Also Published As

Publication number Publication date
JPH0533535B2 (en) 1993-05-19

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