JPH08279571A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH08279571A JPH08279571A JP7083712A JP8371295A JPH08279571A JP H08279571 A JPH08279571 A JP H08279571A JP 7083712 A JP7083712 A JP 7083712A JP 8371295 A JP8371295 A JP 8371295A JP H08279571 A JPH08279571 A JP H08279571A
- Authority
- JP
- Japan
- Prior art keywords
- wiring pattern
- semiconductor chip
- semiconductor device
- chip
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は薄く形成でき、かつ放熱
性に優れる半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which can be formed thin and has excellent heat dissipation.
【０００２】[0002]
【従来の技術】パッケージに半導体チップを搭載した半
導体装置は、実装密度を向上させるため、益々小型化の
要請が強い。図５は、プリント配線基板に半導体チップ
を搭載し、片面モールドした、いわゆるオーバーモール
ドタイプの半導体装置である。１０は樹脂基板、１１は
樹脂基板１０の上面側に形成された配線パターン、１２
は樹脂基板１０の下面側に形成された配線パターンであ
り、両配線パターン１１、１２はスルーホールめっき皮
膜１３を介して接続している。１４は半導体チップであ
り、ダイパッド１５上に固定され、ワイヤ１６により配
線パターン１１と電気的に接続されている。１７ははん
だバンプであり、配線パターン１２に固定され、樹脂基
板下面側に所定の例えばマトリクス状に多数配列されて
いる。１８、１９は保護膜である。半導体チップ１４は
トランスファーモールド等により樹脂２０で封止されて
いる。2. Description of the Related Art A semiconductor device in which a semiconductor chip is mounted on a package has a strong demand for miniaturization in order to improve packaging density. FIG. 5 shows a so-called overmold type semiconductor device in which a semiconductor chip is mounted on a printed wiring board and one side is molded. Reference numeral 10 is a resin substrate, 11 is a wiring pattern formed on the upper surface of the resin substrate 10, and 12 is a wiring pattern.
Is a wiring pattern formed on the lower surface side of the resin substrate 10, and both wiring patterns 11 and 12 are connected via a through-hole plating film 13. A semiconductor chip 14 is fixed on the die pad 15 and is electrically connected to the wiring pattern 11 by a wire 16. Reference numeral 17 is a solder bump, which is fixed to the wiring pattern 12 and is arranged in a predetermined matrix, for example, on the lower surface of the resin substrate. Reference numerals 18 and 19 are protective films. The semiconductor chip 14 is sealed with resin 20 by transfer molding or the like.
【０００３】[0003]
【発明が解決しようとする課題】上記のオーバーモール
ドタイプの半導体装置では片面モールドのため薄型化が
可能となる。しかしながら、樹脂基板１０自体が０．３
〜０．５ｍｍ程度の厚さを有しており、またワイヤ１６
が半導体チップ１４の上方に突出してこのワイヤ１６を
覆って樹脂２０により封止するため、半導体装置全体の
厚さがかなりのものとなり、薄型化の要請に応えられな
くなってきている。また、半導体チップ１４の周辺とな
る部位の樹脂基板１０にスルーホール１３ａを設け、該
スルーホール１３ａの部位から樹脂基体１０の下面側に
配線パターン１２を引き回してはんだバンプ１７を固定
しているため全体の配線が長くなるという問題点があっ
た。さらにはんだバンプ１７を直接スルーホール１３ａ
の部位に固定できないため、図示のごとくスルーホール
の回りにランドを形成して、該ランド上にはんだバンプ
１７を固定するようにしていたので、ランドの分だけエ
リアを広く必要とし、小型化が図れなかった。The above overmold type semiconductor device can be thinned because it is a single-sided mold. However, the resin substrate 10 itself is 0.3
The wire 16 has a thickness of about 0.5 mm.
However, since it protrudes above the semiconductor chip 14 and covers the wire 16 and seals it with the resin 20, the thickness of the entire semiconductor device becomes considerable, and it has become impossible to meet the demand for thinning. Further, since the through hole 13a is provided in the resin substrate 10 at the portion around the semiconductor chip 14, the wiring pattern 12 is drawn from the portion of the through hole 13a to the lower surface side of the resin base 10 to fix the solder bump 17. There is a problem that the entire wiring becomes long. Further, the solder bumps 17 are directly connected to the through holes 13a.
Since the land cannot be fixed to the part of FIG. 3, a land is formed around the through hole as shown in the figure and the solder bump 17 is fixed on the land. I couldn't.
【０００４】そこで、本発明は上記問題点を解決すべく
なされたものであり、その目的とするところは、小型化
ができる半導体装置を提供するにある。Therefore, the present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device which can be miniaturized.
【０００５】[0005]
【課題を解決するための手段】本発明は上記目的を達成
するため次の構成を備える。すなわち、絶縁性フィルム
上に配線パターンが形成され、該配線パターンに半導体
チップがバンプを介して接続されると共に、前記絶縁性
フィルムの反対側の面には外部接続用のバンプが前記配
線パターンに対応して所要の配列で形成されたスルーホ
ールから突出して設けられており、前記半導体チップお
よび前記配線パターンが、前記接続された半導体チップ
の反対側の面を露出させて封止樹脂により封止されてい
ることを特徴としている。前記絶縁性フィルムにはポリ
イミドフィルムを好適に用いることができる。前記封止
樹脂を低圧で射出成形すると好適である。前記バンプは
はんだボールとすることができる。前記露出している半
導体チップ面に放熱用の被覆層を形成することにより薄
さを確保したまま放熱性を向上できる。また前記封止樹
脂に導電性樹脂を用いることにより放熱性と電気的特性
を向上させることができる。The present invention has the following constitution in order to achieve the above object. That is, a wiring pattern is formed on an insulating film, a semiconductor chip is connected to the wiring pattern via a bump, and a bump for external connection is formed on the wiring pattern on the opposite surface of the insulating film. Correspondingly, the semiconductor chip and the wiring pattern are provided so as to project from through holes formed in a required arrangement, and the surface on the opposite side of the connected semiconductor chip is exposed and sealed with a sealing resin. It is characterized by being. A polyimide film can be preferably used as the insulating film. It is preferable to injection-mold the sealing resin at low pressure. The bumps may be solder balls. By forming a heat dissipation coating layer on the exposed surface of the semiconductor chip, heat dissipation can be improved while maintaining a thin thickness. In addition, heat dissipation and electrical characteristics can be improved by using a conductive resin as the sealing resin.
【０００６】[0006]
【作用】図１に示すように、半導体チップ２７を配線パ
ターン２６上にバンプを介して接続し、しかも半導体チ
ップ２７上面側を封止樹脂３２によって覆わず露出させ
るようにしているので、半導体装置全体の厚さを薄く、
かつ軽量化でき、さらに半導体チップ２７の熱放散性を
高めることができる。また、半導体チップ２７をバンプ
を介して接続し、しかも配線パターン２６を介してスル
ーホール２９内に形成したバンプ３１により絶縁性フィ
ルム２５下面側に端子を引き出しているので、配線の長
さを可及的に短くできるメリットがある。さらにバンプ
３１は配線パターン２６により閉塞されたスルーホール
２９内に直接充填して設けられるので、従来のようにス
ルーホール２９の回りにランドを形成する必要がなく、
それだけスペース効率があがり、バンプ３１を密なパタ
ーンで配設でき、したがってまたそれだけ小型化でき
る。As shown in FIG. 1, the semiconductor chip 27 is connected to the wiring pattern 26 via bumps, and the upper surface of the semiconductor chip 27 is exposed without being covered with the sealing resin 32. Thin overall thickness,
In addition, the weight can be reduced, and the heat dissipation of the semiconductor chip 27 can be improved. Further, since the semiconductor chip 27 is connected through the bumps and the terminals are led out to the lower surface side of the insulating film 25 by the bumps 31 formed in the through holes 29 through the wiring patterns 26, the wiring length can be increased. There is a merit that it can be shortened as much as possible. Furthermore, since the bumps 31 are provided by directly filling the through holes 29 closed by the wiring pattern 26, it is not necessary to form lands around the through holes 29 as in the conventional case,
Therefore, the space efficiency is increased, the bumps 31 can be arranged in a dense pattern, and the size can be reduced accordingly.
【０００７】[0007]
【実施例】以下、本発明の好適な実施例を添付図面に基
づいて詳細に説明する。図１において、２５は絶縁性フ
ィルムであり、ポリイミドフィルム等の耐熱性に優れる
フィルムが好適である。２６は絶縁性フィルム２５上に
所要のパターンで形成された配線パターンであり、この
配線パターン上に半導体チップ２７がバンプ２８を介し
てフリップ・チップ接続されている。配線パターン２６
は、銅箔等の金属箔を貼設した絶縁性フィルム（例えば
ＴＡＢテープ）２５の金属箔を所要パターンにエッチン
グすることによって形成できる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings. In FIG. 1, 25 is an insulating film, and a film having excellent heat resistance such as a polyimide film is suitable. Reference numeral 26 is a wiring pattern formed in a desired pattern on the insulating film 25, and a semiconductor chip 27 is flip-chip connected via bumps 28 on this wiring pattern. Wiring pattern 26
Can be formed by etching a metal foil of an insulating film (for example, a TAB tape) 25 having a metal foil such as a copper foil attached thereto into a required pattern.
【０００８】絶縁性フィルム２５の配線パターン２６に
対応する位置にスルーホール２９が形成されている。該
スルーホール２９はエキシマレーザー等により各配線パ
ターン２６に対応して正確に穿設できる。したがってス
ルーホール２９の一端側は配線パターン２６により閉塞
され、他端側は絶縁性フィルム２５の下面側に開口して
いる。絶縁性フィルム２５と半導体チップ２７との間隙
には樹脂３０が満たされる。３１は外部接続用バンプの
一例のはんだバンプであり、スルーホール２９内を満た
して配線パターン２６に電気的に接続され、かつ絶縁性
フィルム２５下面側にボール状に突出している。なお、
はんだバンプ３１は必ずしもボール状に突出していなく
ともよい。またはんだバンプ３１は半導体チップ２７と
反対側となる絶縁性フィルム２５の下面側に所要のパタ
ーン、例えばマトリクス状に配設できる。Through holes 29 are formed in the insulating film 25 at positions corresponding to the wiring patterns 26. The through hole 29 can be accurately formed by using an excimer laser or the like so as to correspond to each wiring pattern 26. Therefore, one end side of the through hole 29 is closed by the wiring pattern 26, and the other end side is opened to the lower surface side of the insulating film 25. The gap between the insulating film 25 and the semiconductor chip 27 is filled with the resin 30. Reference numeral 31 is a solder bump as an example of an external connection bump, which fills the through hole 29 and is electrically connected to the wiring pattern 26, and projects in a ball shape on the lower surface side of the insulating film 25. In addition,
The solder bump 31 does not necessarily have to project in a ball shape. The solder bumps 31 can be arranged in a desired pattern, for example, in a matrix pattern on the lower surface side of the insulating film 25, which is the side opposite to the semiconductor chip 27.
【０００９】３２は封止樹脂であり、半導体チップ２７
の側面および配線パターン２６を覆って設けられてい
る。したがって半導体チップ２７の絶縁性フィルム２５
と反対側となる外表面は露出されている。封止樹脂３２
はポッティング樹脂による無圧成形によってもよいが、
低圧の射出成形によって形成してもよい。低圧の射出成
形は、モールド型のキャビティ内に半導体チップ２７を
前記のように搭載した絶縁性フィルム２５を配置し、キ
ャビティ内に例えば液状樹脂を低圧で射出充填して固化
し、成形するようにすることができる。Reference numeral 32 denotes a sealing resin, which is a semiconductor chip 27.
Is provided so as to cover the side surface and the wiring pattern 26. Therefore, the insulating film 25 of the semiconductor chip 27
The outer surface opposite to is exposed. Sealing resin 32
Can be pressureless molded with potting resin,
It may be formed by low-pressure injection molding. In the low-pressure injection molding, the insulating film 25 on which the semiconductor chip 27 is mounted as described above is arranged in the mold cavity, and the liquid resin is injected and filled in the cavity at a low pressure to be solidified and molded. can do.
【００１０】封止樹脂３２はトランスファーモールドの
ように高圧条件下で成形してもよいが、このような高圧
条件下では、配線パターン２６を銅等の柔らかい金属箔
で形成した場合に図２に示すように配線パターン２６が
スルーホール２９内に樹脂圧によって押し出され変形す
るおそれがあるのである。この点無圧あるいは低圧で封
止樹脂３２を成形することによって配線パターン２６の
変形を防止できる。なお、製造工程においては、はんだ
ボール３１は最後、すなわち封止樹脂３２による樹脂封
止工程後に形成される。またスルーホール２９内壁に
は、はんだの濡れ性を向上させるため銅めっき等のスル
ーホールめっき皮膜３３を形成するようにすると好適で
ある（図３）。The sealing resin 32 may be molded under high pressure conditions such as transfer molding. However, under such high pressure conditions, when the wiring pattern 26 is formed of a soft metal foil such as copper as shown in FIG. As shown, the wiring pattern 26 may be pushed into the through hole 29 by the resin pressure and deformed. In this respect, the deformation of the wiring pattern 26 can be prevented by molding the sealing resin 32 without pressure or with low pressure. In the manufacturing process, the solder balls 31 are formed last, that is, after the resin sealing process using the sealing resin 32. Further, it is preferable to form a through hole plating film 33 such as copper plating on the inner wall of the through hole 29 in order to improve the wettability of the solder (FIG. 3).
【００１１】上記実施例では、前記従来のものに比し
て、半導体チップ２７を配線パターン２６上にフリップ
・チップ接続し、しかも半導体チップ２７上面側を封止
樹脂３２によって覆わず露出させるようにしているの
で、半導体装置全体の厚さを薄く、かつ軽量化でき、さ
らに半導体チップ２７の熱放散性を高めることができ
る。また、半導体チップ２７をフリップ・チップ接続
し、しかも配線パターン２６を介してスルーホール２９
内に形成したはんだバンプ３１により絶縁性フィルム２
５下面側に端子を引き出しているので、配線の長さを可
及的に短くできるメリットがある。さらにはんだバンプ
３１は配線パターン２６により閉塞されたスルーホール
２９内に直接充填して設けられるので、従来のようにス
ルーホール２９の回りにランドを形成する必要がなく、
それだけスペース効率があがり、はんだバンプ３１を密
なパターンで配設でき、したがってまたそれだけ小型化
できる。In the above-described embodiment, the semiconductor chip 27 is flip-chip connected onto the wiring pattern 26, and the upper surface side of the semiconductor chip 27 is exposed without being covered with the sealing resin 32 as compared with the conventional one. Therefore, the thickness of the entire semiconductor device can be reduced and the weight can be reduced, and the heat dissipation of the semiconductor chip 27 can be improved. Further, the semiconductor chip 27 is flip-chip connected, and the through hole 29 is provided via the wiring pattern 26.
The insulating film 2 is formed by the solder bumps 31 formed inside.
5. Since the terminals are drawn out to the lower surface side, there is an advantage that the length of the wiring can be shortened as much as possible. Further, since the solder bumps 31 are provided by directly filling the through holes 29 closed by the wiring pattern 26, it is not necessary to form lands around the through holes 29 unlike the conventional case.
Therefore, the space efficiency is increased, the solder bumps 31 can be arranged in a dense pattern, and accordingly, the size can be reduced.
【００１２】図４は他の実施例を示す。前記実施例と同
じ構成は同一符号を付し、説明を省略する。本実施例で
は、露出している半導体チップ２７の外表面を覆って、
銅ペースト膜等の金属粉と樹脂を混練した金属粉入りペ
ースト膜（放熱性被覆層）３５を形成した。該金属粉入
りペースト膜３５はペーストを印刷し、乾燥することに
よって形成できる。本実施例では、薄さを保ったままさ
らに半導体チップ２７の放熱性を向上させることができ
る。なお、前記各実施例において、封止樹脂３２に銅等
の金属からなるフィラーが添加された導電性樹脂（図示
せず）を用いると半導体装置の放熱性と電気的特性を向
上できる。封止樹脂３２に導電性樹脂を用いる場合、絶
縁性フィルム２５上の配線パターン２６は接地用配線パ
ターンなどの必要な所要部位を除いて保護膜（レジス
ト）で被覆され（図示せず）、導電性樹脂と電気的に絶
縁される。また半導体チップ２７と配線パターン２６の
接続部分（バンプ）は樹脂３０が充填されているので導
電性樹脂と電気的に絶縁される。配線パターン２６のう
ちの、接地用配線パターンを導電性樹脂と接続するよう
にすると、半導体チップ２７を外部から電気的にシール
ドできるので、半導体装置の電気的特性を向上できる。FIG. 4 shows another embodiment. The same components as those in the above-described embodiment are designated by the same reference numerals and the description thereof will be omitted. In this embodiment, by covering the exposed outer surface of the semiconductor chip 27,
A paste film (heat dissipation coating layer) 35 containing a metal powder, such as a copper paste film and a metal powder and a resin, was kneaded. The metal powder-containing paste film 35 can be formed by printing a paste and drying it. In this embodiment, the heat dissipation of the semiconductor chip 27 can be further improved while keeping the thinness. In each of the above-described embodiments, if a conductive resin (not shown) in which a filler made of a metal such as copper is added to the sealing resin 32, heat dissipation and electrical characteristics of the semiconductor device can be improved. When a conductive resin is used as the sealing resin 32, the wiring pattern 26 on the insulating film 25 is covered with a protective film (resist) (not shown) except for the necessary required portions such as the ground wiring pattern, and the conductive pattern is formed. It is electrically insulated from the resin. Further, the connection portion (bump) between the semiconductor chip 27 and the wiring pattern 26 is filled with the resin 30, so that it is electrically insulated from the conductive resin. By connecting the grounding wiring pattern of the wiring pattern 26 to the conductive resin, the semiconductor chip 27 can be electrically shielded from the outside, so that the electrical characteristics of the semiconductor device can be improved.
【００１３】以上本発明につき好適な実施例を挙げて種
々説明したが、本発明はこの実施例に限定されるもので
はなく、発明の精神を逸脱しない範囲内で多くの改変を
施し得るのはもちろんである。Although the present invention has been described in detail with reference to the preferred embodiments, the present invention is not limited to these embodiments, and many modifications can be made without departing from the spirit of the invention. Of course.
【００１４】[0014]
【発明の効果】本発明に係る半導体装置によれば、上述
したように、半導体チップを配線パターン上にバンプを
介して接続し、しかも半導体チップ外表面側を封止樹脂
によって覆わず露出させるようにしているので、半導体
装置全体の厚さを薄く、かつ軽量化でき、さらに半導体
チップの熱放散性を高めることができる。また、半導体
チップをバンプを介して接続し、しかも配線パターンを
介してスルーホール内に形成した外部接続用のバンプに
より絶縁性フィルム下面側に端子を引き出しているの
で、配線の長さを可及的に短くできるメリットがある。
露出された半導体チップの外表面を覆って放熱性被覆層
を形成することによって、薄さを保ったまま放熱性を一
層向上させることができる。さらに、封止樹脂に導電性
樹脂を用いることによって、放熱性、電気的特性を向上
できる。According to the semiconductor device of the present invention, as described above, the semiconductor chip is connected to the wiring pattern via the bump, and the outer surface side of the semiconductor chip is exposed without being covered with the sealing resin. Therefore, the thickness of the entire semiconductor device can be reduced and the weight can be reduced, and the heat dissipation of the semiconductor chip can be improved. In addition, since the semiconductor chip is connected via bumps and the terminals are pulled out to the lower surface side of the insulating film by the external connection bumps formed in the through holes via the wiring pattern, the wiring length can be maximized. There is a merit that it can be shortened.
By forming the heat dissipation coating layer to cover the exposed outer surface of the semiconductor chip, the heat dissipation can be further improved while keeping the thinness. Furthermore, by using a conductive resin as the sealing resin, heat dissipation and electrical characteristics can be improved.
【図１】第１の実施例を示した断面図である。FIG. 1 is a sectional view showing a first embodiment.
【図２】配線パターンの変形状態を示す説明図である。FIG. 2 is an explanatory diagram showing a deformed state of a wiring pattern.
【図３】スルーホール内にめっき皮膜を形成した実施例
の部分断面図である。FIG. 3 is a partial cross-sectional view of an example in which a plating film is formed in a through hole.
【図４】金属粉入りペースト膜（放熱性ペースト膜）を
形成した実施例を示す断面図である。FIG. 4 is a cross-sectional view showing an example in which a paste film containing metal powder (heat dissipation paste film) is formed.
【図５】従来の半導体装置の一例を示す部分断面図であ
る。FIG. 5 is a partial cross-sectional view showing an example of a conventional semiconductor device.
２５ 絶縁性フィルム ２６ 配線パターン ２７ 半導体チップ ２８ バンプ ２９ スルーホール ３０ 樹脂 ３１ はんだバンプ ３２ 封止樹脂 ３３ スルーホールめっき膜 ３５ 放熱性被覆層 25 Insulating Film 26 Wiring Pattern 27 Semiconductor Chip 28 Bump 29 Through Hole 30 Resin 31 Solder Bump 32 Sealing Resin 33 Through Hole Plating Film 35 Heat Dissipative Cover Layer
Claims (6)
され、該配線パターンに半導体チップがバンプを介して
接続されると共に、前記絶縁性フィルムの反対側の面に
は外部接続用のバンプが前記配線パターンに対応して所
要の配列で形成されたスルーホールから突出して設けら
れており、前記半導体チップおよび前記配線パターン
が、前記接続された半導体チップの反対側の面を露出さ
せて封止樹脂により封止されていることを特徴とする半
導体装置。1. A wiring pattern is formed on an insulating film, a semiconductor chip is connected to the wiring pattern via a bump, and a bump for external connection is provided on a surface opposite to the insulating film. The semiconductor chip and the wiring pattern are provided so as to project from through holes formed in a required array corresponding to the wiring pattern, and the opposite surface of the connected semiconductor chip is exposed to expose a sealing resin. A semiconductor device characterized by being sealed by.
あることを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the insulating film is a polyimide film.
ることを特徴とする請求項１または２記載の半導体装
置。3. The semiconductor device according to claim 1, wherein the sealing resin is injection-molded at a low pressure.
特徴とする請求項１、２または３記載の半導体装置。4. The semiconductor device according to claim 1, 2 or 3, wherein the bump is a solder ball.
放熱用被覆層が形成されていることを特徴とする請求項
１、２、３または４記載の半導体装置。5. The semiconductor device according to claim 1, wherein a heat dissipation coating layer is formed on the exposed outer surface of the semiconductor chip.
特徴とする請求項１、２、３、４または５記載の半導体
装置。6. The semiconductor device according to claim 1, wherein the sealing resin is a conductive resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7083712A JPH08279571A (en) | 1995-04-10 | 1995-04-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7083712A JPH08279571A (en) | 1995-04-10 | 1995-04-10 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08279571A true JPH08279571A (en) | 1996-10-22 |
Family
ID=13810123
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7083712A Pending JPH08279571A (en) | 1995-04-10 | 1995-04-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08279571A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08330473A (en) * | 1995-05-31 | 1996-12-13 | Samsung Electron Co Ltd | Printed circuit board with installation groove of solder ball and ball grid array package using it |
| WO1998040914A1 (en) * | 1997-03-13 | 1998-09-17 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
| US6448665B1 (en) | 1997-10-15 | 2002-09-10 | Kabushiki Kaisha Toshiba | Semiconductor package and manufacturing method thereof |
| CN1316620C (en) * | 2003-10-27 | 2007-05-16 | 精工爱普生株式会社 | Semiconductor chip |
| JP2010114355A (en) * | 2008-11-10 | 2010-05-20 | Fujitsu Ltd | Electronic component, method of manufacturing electronic component, and method of manufacturing heat conductive member |
| US8110245B2 (en) | 1999-02-18 | 2012-02-07 | Seiko Epson Corporation | Semiconductor device, mounting substrate and method of manufacturing mounting substrate, circuit board, and electronic instrument |
| KR101255335B1 (en) * | 2005-11-23 | 2013-04-16 | 페어차일드코리아반도체 주식회사 | Semiconductor Package and Method of Fabricating the Same |
-
1995
- 1995-04-10 JP JP7083712A patent/JPH08279571A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08330473A (en) * | 1995-05-31 | 1996-12-13 | Samsung Electron Co Ltd | Printed circuit board with installation groove of solder ball and ball grid array package using it |
| WO1998040914A1 (en) * | 1997-03-13 | 1998-09-17 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
| US7339118B1 (en) | 1997-03-13 | 2008-03-04 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
| US7612295B2 (en) | 1997-03-13 | 2009-11-03 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
| US6448665B1 (en) | 1997-10-15 | 2002-09-10 | Kabushiki Kaisha Toshiba | Semiconductor package and manufacturing method thereof |
| KR100348098B1 (en) * | 1997-10-15 | 2002-12-26 | 가부시끼가이샤 도시바 | Semiconductor package and manufacturing method thereof |
| US8110245B2 (en) | 1999-02-18 | 2012-02-07 | Seiko Epson Corporation | Semiconductor device, mounting substrate and method of manufacturing mounting substrate, circuit board, and electronic instrument |
| CN1316620C (en) * | 2003-10-27 | 2007-05-16 | 精工爱普生株式会社 | Semiconductor chip |
| KR101255335B1 (en) * | 2005-11-23 | 2013-04-16 | 페어차일드코리아반도체 주식회사 | Semiconductor Package and Method of Fabricating the Same |
| JP2010114355A (en) * | 2008-11-10 | 2010-05-20 | Fujitsu Ltd | Electronic component, method of manufacturing electronic component, and method of manufacturing heat conductive member |
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