JPH1174420A - Surface mount chip and manufacture thereof - Google Patents

Surface mount chip and manufacture thereof

Info

Publication number
JPH1174420A
JPH1174420A JP9245926A JP24592697A JPH1174420A JP H1174420 A JPH1174420 A JP H1174420A JP 9245926 A JP9245926 A JP 9245926A JP 24592697 A JP24592697 A JP 24592697A JP H1174420 A JPH1174420 A JP H1174420A
Authority
JP
Japan
Prior art keywords
insulating substrate
electrode
resin
electronic element
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9245926A
Other languages
Japanese (ja)
Other versions
JP3900613B2 (en
Inventor
Akira Koike
晃 小池
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Electronics Co Ltd
Original Assignee
Citizen Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Electronics Co Ltd filed Critical Citizen Electronics Co Ltd
Priority to JP24592697A priority Critical patent/JP3900613B2/en
Publication of JPH1174420A publication Critical patent/JPH1174420A/en
Application granted granted Critical
Publication of JP3900613B2 publication Critical patent/JP3900613B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Led Device Packages (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain an inexpensive device wherein reliability is improved, a circuit sealing frame is not used, a cubic substrate with high dimension accuracy, the cost reduction and the yield rate of the product are improved, and the luminance performance is increased furthermore. SOLUTION: On an insulating substrate 1 wherein an LED-element containing concave part 12 is formed and the solid made of epoxy resin is molded, a pair of upper surface electrodes 2a and 2b, lower-surface electrodes 3a and 3b and side-surface electrodes 4a and 4b connected to the upper and lower-surface electrodes are formed. An LED element 5 is fixed on one upper surface electrode 2a. A bonding wire 6 is connected to the other upper surface electrode 2b. Sealing is performed with sealing resin 8 comprising the epoxy resin. At the bottom surface and the slant surfaces at four surfaces expanding upward, a light reflecting dummy pattern is applied in a vacant space which does not interfere with the upper surface electrodes 2a and 2b, and the upward rising of luminance is achieved. Both the insulating substrate 1 and the sealing resin are epoxy resin, and the linear expansion coefficients agree. Therefore, the separation of the substrate 1 and the resin 8 does not occur. There is no worry of the damage to the LED element 5. Thus, the highly reliable and inexpensive surface- mount chip is obtained.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は携帯電話、FA機
器、OA機器及び一般電子機器に使用される表面実装型
チップ部品及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface mount type chip component used for portable telephones, FA equipment, OA equipment and general electronic equipment, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】近年の電子機器は、高性能化、多機能化
とともに小型化、軽量化を追求している。そのため電子
部品をプリント基板上に実装し、樹脂封止するものが多
い。表面実装型チップ部品の多くは略平行六面体形状を
しており、プリント基板上の配線パターンに半田付け等
の固着手段で接続される。
2. Description of the Related Art In recent years, electronic devices have been pursuing high performance and multiple functions, as well as miniaturization and weight reduction. Therefore, electronic components are often mounted on a printed circuit board and sealed with a resin. Many surface mount chip components have a substantially parallelepiped shape and are connected to a wiring pattern on a printed circuit board by a fixing means such as soldering.

【0003】前記一般的な従来の表面実装型チップ部品
について、図面に基づいてその概要を説明する。
An outline of the general conventional surface mount type chip component will be described with reference to the drawings.

【0004】図7〜図15は、従来の表面実装型チップ
部品及びその製造方法を示し、図7は、ガラスエポキシ
材よりなる集合絶縁基板の部分平面図。図8は、単個の
電極パターン平面図。図9は、LED素子の斜視図。図
10〜図15は、各工程を示す部分斜視図。図16は、
単個の表面実装型チップ部品の斜視図。図21は、図1
6のA−A線断面図である。
FIGS. 7 to 15 show a conventional surface mount chip component and a method of manufacturing the same. FIG. 7 is a partial plan view of a collective insulating substrate made of a glass epoxy material. FIG. 8 is a plan view of a single electrode pattern. FIG. 9 is a perspective view of an LED element. 10 to 15 are partial perspective views showing each step. FIG.
FIG. 2 is a perspective view of a single surface mount chip component. FIG.
FIG. 6 is a sectional view taken along line AA of FIG. 6.

【0005】図16及び図21において、表面実装型チ
ップ部品10について説明する。ガラエポ樹脂材よりな
る絶縁基板1aの上面側に対向する一対の上面電極2
a、2bを設け、該一対の上面電極2a、2bは、それ
ぞれその裏面に下面電極3a、3bと、その側面に、前
記上面電極2a、2b及び下面電極3a、3bと連なる
側面電極(スルーホール電極)4a、4bが形成されて
いる。前記一方の上面電極2aのAuメッキされたダイ
ボンドパターンに導電性接着剤9(銀ペースト)でLE
D素子5の一方の電極をダイポンドする。他方の上面電
極2bのAuメッキされたワイヤーボンドパターンに、
LED素子5の他方の電極をボンディングワイヤー(A
u線)6でワイヤーボンドして接続されている。
Referring to FIGS. 16 and 21, the surface mount type chip component 10 will be described. A pair of upper electrodes 2 opposed to the upper surface of an insulating substrate 1a made of glass epoxy resin material
a, 2b, and the pair of upper electrodes 2a, 2b have side electrodes (through-holes) connected to the lower electrodes 3a, 3b on the back and the upper electrodes 2a, 2b and the lower electrodes 3a, 3b on the side. (Electrodes) 4a and 4b are formed. The Au-plated die bond pattern of the one upper surface electrode 2a is LE-coated with a conductive adhesive 9 (silver paste).
One electrode of the D element 5 is die-pounded. In the Au-plated wire bond pattern of the other upper electrode 2b,
The other electrode of the LED element 5 is connected to a bonding wire (A
(u line) 6 and connected by wire bonding.

【0006】前記絶縁基板1aの上面電極2aに接着さ
れたLED素子5をとり囲むように、液晶ポリマー材で
樹脂成形され、上方に開口した窓部7aを有する下面に
接着剤9aを印刷した回路封止枠7を絶縁基板1aに接
着して一体化している。前記窓部7aの傾斜面7bは、
LED素子5の上面方向の輝度向上の機能を有してい
る。
A circuit formed by resin molding of a liquid crystal polymer material so as to surround the LED element 5 bonded to the upper electrode 2a of the insulating substrate 1a, and printed with an adhesive 9a on a lower surface having a window 7a opened upward. The sealing frame 7 is bonded to and integrated with the insulating substrate 1a. The inclined surface 7b of the window 7a is
It has a function of improving brightness in the upper surface direction of the LED element 5.

【0007】前記LED素子5とボンディングワイヤー
6と、その接続部を保護するために、前記回路封止枠7
の上面と面一になるように、窓部7a内にエポキシ樹脂
よりなる封止樹脂8を注入して、樹脂封止することによ
り、表面実装型チップ部品10が完成される。
[0007] In order to protect the LED element 5, the bonding wire 6, and the connecting portion, the circuit sealing frame 7 is provided.
The surface mount chip component 10 is completed by injecting a sealing resin 8 made of an epoxy resin into the window 7a so as to be flush with the upper surface of the chip and sealing the resin.

【0008】図7〜図15により、前記表面実装型チッ
プ部品10の製造方法について、その概要を説明する。
図7において、集合絶縁基板形成工程は、略四角形状を
したガラスエポキシ樹脂材よりなる上下両面が銅箔張り
された多数個取りする集合絶縁基板1Aは、各列毎に複
数個のスルーホール11をマトリックス状にNC切削等
で加工し、前記集合絶縁基板1Aのスルーホール11の
内面を含む全表面を無電解、電解メッキにより銅メッキ
層を形成する。
Referring to FIGS. 7 to 15, an outline of a method of manufacturing the surface-mounted chip component 10 will be described.
In FIG. 7, the collective insulating substrate forming step is a process of forming a plurality of collective insulating substrates 1A made of a substantially rectangular glass epoxy resin material and having upper and lower surfaces thereof covered with copper foil and having a plurality of through holes 11 for each row. Is processed in a matrix by NC cutting or the like, and a copper plating layer is formed on the entire surface including the inner surface of the through hole 11 of the collective insulating substrate 1A by electroless and electrolytic plating.

【0009】次に、レジストフィルムを貼付し、マスク
を合わせ、露光、現像、エッチング後レジストを剥離す
る。更に、液状レジストを塗付し、マスク合わせ、露
光、現像後、電解メッキによりニッケルメッキ層を形成
し、電解メッキにより金メッキ層を形成する。
Next, a resist film is adhered, a mask is aligned, and the resist is removed after exposure, development and etching. Further, a liquid resist is applied, and after mask alignment, exposure, and development, a nickel plating layer is formed by electrolytic plating, and a gold plating layer is formed by electrolytic plating.

【0010】以上により、集合絶縁基板1Aの上面側に
は、図8(図7の点線円で囲むA部)に示すように、対
向する一対の上面電極2a、2bと、下面側に対向する
一対の図示しない下面電極及び、前記上面電極2a、2
b及び前記下面電極と連なるようにスルーホール電極4
a、4bが形成される。
As described above, on the upper surface side of the collective insulating substrate 1A, as shown in FIG. 8 (part A surrounded by a dotted circle in FIG. 7), a pair of upper surface electrodes 2a and 2b opposed to each other and opposed to the lower surface side. A pair of lower electrodes (not shown) and the upper electrodes 2a, 2a
b and the through-hole electrode 4 so as to be connected to the lower electrode.
a, 4b are formed.

【0011】LED素子5の構成は、図9に示すよう
に、ジャンクション5aを挟み、N層5bとP層5cで
形成されている。LED素子5のダイボンド工程は、図
10に示すように、LED素子5の一方の電極5dを、
集合絶縁基板1Aに形成されている、個々の絶縁基板の
一方の上面電極2aにダイボンディングして導電性接着
剤9等の固着手段で固着する。ワイヤーボンド工程は、
図11において、LED素子5の他方の電極5eを、個
々の絶縁基板の他方の上面電極2bに示すごとくボンデ
ィングワイヤー6で接続する。
As shown in FIG. 9, the structure of the LED element 5 is formed by an N layer 5b and a P layer 5c with a junction 5a interposed therebetween. In the die bonding step of the LED element 5, as shown in FIG.
It is die-bonded to one upper surface electrode 2a of each of the insulating substrates formed on the collective insulating substrate 1A and fixed by a fixing means such as a conductive adhesive 9. The wire bonding process
In FIG. 11, the other electrode 5e of the LED element 5 is connected by a bonding wire 6 as shown on the other upper electrode 2b of each insulating substrate.

【0012】回路封止枠接着工程は、図12及び図13
に示すように、液晶ポリマー材よりなる集合回路封止枠
7Aは、前記集合絶縁基板1A上にダイボンドされたL
ED素子5の位置に合致するように、所定間隔に複数個
の窓部7aが成形されている。前記集合回路封止枠7A
は、その下面に事前に接着剤9a等を印刷しておき、L
ED素子5の周囲を取り囲むように、位置合わせして集
合絶縁基板1Aに接着して一体化する。
FIGS. 12 and 13 show the circuit sealing frame bonding step.
As shown in the figure, a collective circuit sealing frame 7A made of a liquid crystal polymer material is provided on the collective insulating substrate 1A by die bonding.
A plurality of windows 7a are formed at predetermined intervals so as to match the position of the ED element 5. The assembly circuit sealing frame 7A
Is printed with an adhesive 9a or the like in advance on the lower surface thereof,
The ED element 5 is aligned and adhered to the collective insulating substrate 1A so as to surround the periphery of the ED element 5, and integrated.

【0013】樹脂封止工程は、図14に示すように、前
記集合回路封止枠7Aの各窓部7a内に、LED素子5
及びボンディングワイヤー6の接続部を保護するため
に、エポキシ樹脂よりなる封止樹脂8で、集合回路封止
枠7Aの上面と略面一になるように樹脂封止する。表面
実装型チップ部品集合体10Aが完成される。
In the resin sealing step, as shown in FIG. 14, the LED element 5 is inserted into each window 7a of the collective circuit sealing frame 7A.
In order to protect the connection portions of the bonding wires 6, the resin is sealed with a sealing resin 8 made of epoxy resin so as to be substantially flush with the upper surface of the collective circuit sealing frame 7 </ b> A. The surface mount type chip component assembly 10A is completed.

【0014】切断工程は、図15に示すように、表面実
装型チップ部品集合体10Aを、直交する2つのカット
ライン2(X方向のカットラインはスルーホール11上
を通る)に沿ってダイシング等の切断手段で単個に分割
することにより、図16で示す表面実装型チップ部品1
0が完成される。
In the cutting step, as shown in FIG. 15, dicing or the like is performed on the surface-mounted chip component assembly 10A along two orthogonal cut lines 2 (a cut line in the X direction passes over the through hole 11). The surface mounting chip component 1 shown in FIG.
0 is completed.

【0015】図17〜図20は、MID基板よりなる、
従来の他の表面実装型チップ部品及びその製造方法に係
わり、図17は、MID基板よりなる集合絶縁基板の部
分平面図。図18は、単個の電極パターン平面図。図1
9(a)〜(d)は、各工程を示す部分斜視図。図20
は、単個の表面実装型チップ部品の斜視図。図22は、
図20のB−B線断面図である。
FIG. 17 to FIG. 20 each show a MID substrate.
FIG. 17 is a partial plan view of a collective insulating substrate formed of an MID substrate, which relates to another conventional surface-mounted chip component and a method of manufacturing the same. FIG. 18 is a plan view of a single electrode pattern. FIG.
9 (a) to 9 (d) are partial perspective views showing respective steps. FIG.
1 is a perspective view of a single surface mount chip component. FIG.
FIG. 21 is a sectional view taken along line BB of FIG. 20.

【0016】図20及び図22において、MID絶縁基
板1bは液晶ポリマー材よりなり、成形部品と立体的な
三次元回路を一体化させた射出成形回路部品で、上述し
た絶縁基板と回路封止枠の製造プロセスに比べて、回路
形成及び一体化組立が合理化されている。
In FIG. 20 and FIG. 22, the MID insulating substrate 1b is made of a liquid crystal polymer material and is an injection molded circuit component in which a molded component and a three-dimensional three-dimensional circuit are integrated. Circuit formation and integrated assembly are rationalized as compared with the manufacturing process of the above.

【0017】図において、絶縁基板1bには、LED素
子収納凹部12が、すり鉢状に形成されている。前記L
ED素子収納凹部12を含み、上面側に対向する一対の
上面電極2a、2bと、下面側に対向する一対の下面電
極3a、3b及び、前記上面電極2a、2b及び前記下
面電極3a、3bと連なるように側面電極(長穴スルー
ホール電極)4a、4bが形成されている。上述と同様
に、前記一対の上面電極の一方の上面電極2aの底部
に、LED素子5がダイボンドされ、他方の上面電極2
bにAuワイヤ等よりなるボンディングワイヤ6で接続
されている。前記LED素子5の周囲を囲むすり鉢状の
LED素子収納凹部12は、Auメッキされているの
で、LED素子5から発光した光を上面方向に反射し、
集光させるので、輝度向上が図られる。
In the figure, an LED element housing recess 12 is formed in a mortar shape on an insulating substrate 1b. Said L
A pair of upper electrodes 2a and 2b including the ED element housing recess 12 and facing the upper surface, a pair of lower electrodes 3a and 3b facing the lower surface, and the upper electrodes 2a and 2b and the lower electrodes 3a and 3b. Side electrodes (elongated through-hole electrodes) 4a and 4b are formed so as to be continuous. As described above, the LED element 5 is die-bonded to the bottom of one upper electrode 2a of the pair of upper electrodes, and the other upper electrode 2
b is connected by a bonding wire 6 made of an Au wire or the like. Since the mortar-shaped LED element housing recess 12 surrounding the periphery of the LED element 5 is plated with Au, the light emitted from the LED element 5 is reflected in the upper direction,
Since the light is condensed, the brightness is improved.

【0018】上述と同様に、絶縁基板1bのLED素子
収納凹部12に、LED素子5及びボンディングワイヤ
ー6と、その接続部を保護するために、エポキシ樹脂等
の封止樹脂8で封止して、表面実装型チップ部品20が
完成される。
As described above, the LED element 5 and the bonding wire 6 are sealed in the LED element accommodating recess 12 of the insulating substrate 1b with a sealing resin 8 such as epoxy resin in order to protect the connection portion. Thus, the surface mount chip component 20 is completed.

【0019】前記表面実装型チップ部品の製造方法は、
上述した従来方法と同様に、多数個取りする集合基板の
状態で行う。集合絶縁基の構成は、図17に示すような
略四角形状をした、液晶ポリマー材よりなる集合絶縁基
板1Bの各列毎に長穴スルーホール11a及び各列間で
所定間隔に複数個のLED素子収納凹部12を射出成形
で形成した成形品と、図18(図17の点線円で囲むB
部)に示すような、三次元の電極パターンが、一体的に
メッキ処理された構成となっている。
[0019] The method of manufacturing the surface mount type chip component is as follows.
As in the above-described conventional method, the process is performed in a state of a collective substrate from which a large number of pieces are taken. The configuration of the collective insulating group is such that a plurality of LEDs are formed at a predetermined interval between each row of the elongated hole through holes 11a and each row of the collective insulating substrate 1B made of a liquid crystal polymer material having a substantially square shape as shown in FIG. A molded product in which the element accommodating recess 12 is formed by injection molding is shown in FIG. 18 (B surrounded by a dotted circle in FIG. 17).
(3), a three-dimensional electrode pattern is integrally plated.

【0020】各製造工程は、図19において、(a)
は、LED素子5のダイボンド工程、(b)は、ワイヤ
ーボンディング工程、(c)は、樹脂封止工程、(d)
は切断工程を示すものであり、上述した従来技術と同様
であるので説明は省略する。
Each manufacturing process is shown in FIG.
Is a die bonding step of the LED element 5, (b) is a wire bonding step, (c) is a resin sealing step, (d)
Indicates a cutting step, which is the same as the above-described conventional technique, and a description thereof will be omitted.

【0021】図21〜図24は、上述した、エポキシ樹
脂基板及びMID基板の信頼性試験における膨張及び収
縮のメカニズムを示す断面図である。
FIGS. 21 to 24 are sectional views showing the expansion and contraction mechanisms in the reliability test of the epoxy resin substrate and the MID substrate described above.

【0022】図21及び図22は、ガラエポ樹脂基板及
び液晶ポリマー樹脂よりなるMID基板において、充填
されたエポキシ樹脂が膨張する状態を示し、図21で
は、充填した封止樹脂8と絶縁基板1aとは同じエポキ
シ材で相性が良く、相互間の密着性の点でも問題がな
い。しかし、回路封止枠7の材料は充填した封止樹脂8
と異なる液晶ポリマー材であるため、両者の線膨張係数
が少し異なる。また、図22では、立体成形の絶縁基板
1bの材料が液晶ポリマーであるため、充填した封止樹
脂8と材質が異なるため、両者の線膨張係数が少し異な
り、両者の密着性の点で問題がある。充填した封止樹脂
8が膨張すると、図の矢印C方向に樹脂は制約の無い上
方に向かって膨らむ。この時、図21に示すような、封
止樹脂8と回路封止枠7との界面及び、図22に示すよ
うな、封止樹脂8と絶縁基板1b(液晶ポリマー材)と
の界面では、線膨張係数の差からズレが生じ、接着を剥
がすような力が上方に働く。また、ボンディングワイヤ
ー6及びLED素子5にも上方に持ち上げるような力が
働く。
FIGS. 21 and 22 show a state in which the filled epoxy resin expands in the MID substrate made of a glass epoxy resin substrate and a liquid crystal polymer resin. In FIG. 21, the filled sealing resin 8 and the insulating substrate 1a are shown. Are made of the same epoxy material and have good compatibility, and there is no problem in terms of adhesion between them. However, the material of the circuit sealing frame 7 is the filled sealing resin 8.
Since these are different liquid crystal polymer materials, their linear expansion coefficients are slightly different. Further, in FIG. 22, since the material of the three-dimensionally formed insulating substrate 1b is a liquid crystal polymer, the material differs from that of the filled sealing resin 8, so that the two have slightly different coefficients of linear expansion, and there is a problem in the adhesion between the two. There is. When the filled sealing resin 8 expands, the resin expands upward without any restrictions in the direction of arrow C in the figure. At this time, at the interface between the sealing resin 8 and the circuit sealing frame 7 as shown in FIG. 21 and at the interface between the sealing resin 8 and the insulating substrate 1b (liquid crystal polymer material) as shown in FIG. Deviation occurs due to the difference in linear expansion coefficient, and a force for removing the adhesive acts upward. Further, a force for lifting the bonding wire 6 and the LED element 5 is also exerted.

【0023】図23及び図24は、ガラエポ樹脂基板及
び液晶ポリマー樹脂よりなるMID基板において、充填
されたエポキシ樹脂が収縮する状態を示し、上述と同様
に、図23の封止樹脂8(エポキシ樹脂)と回路封止枠
7(液晶ポリマー)、図24の封止樹脂8(エポキシ樹
脂)と絶縁基板1b(液晶ポリマー)と材料が異なるた
め、両者の線膨張係数が少し異なり、両者の密着性の点
で問題がある。充填した封止樹脂8が収縮すると、図の
矢印Dに示すように、樹脂は内部に向かって縮む。この
応力をLED素子5が受けることになる。
FIGS. 23 and 24 show a state in which the filled epoxy resin is shrunk on the glass epoxy resin substrate and the MID substrate made of a liquid crystal polymer resin, and the sealing resin 8 (epoxy resin) shown in FIG. ) And the circuit sealing frame 7 (liquid crystal polymer), and the sealing resin 8 (epoxy resin) and the insulating substrate 1b (liquid crystal polymer) shown in FIG. There is a problem in the point. When the filled sealing resin 8 shrinks, the resin shrinks inward as shown by arrow D in the figure. The LED element 5 receives this stress.

【0024】[0024]

【発明が解決しようとする課題】しかしながら、前述し
た2つの従来の表面実装型チップ部品には次のような問
題点がある。即ち、上述したように、信頼性試験におい
て、温度サイクル試験とか、高温通電試験等の過酷な環
境条件で製品が使用された場合、線膨張係数の小さい、
前記液晶ポリマー材よりなる回路封止枠とか、立体成形
基板は、それほど膨張・収縮しないのに対し、線膨張係
数の大きいエポキシ樹脂よりなる封止樹脂が、大いに膨
張・収縮するので、両者の間にズレを生じる。その結
果、充填樹脂が膨張した場合は、回路封止枠、立体成形
基板の界面で剥離が生じる。また、収縮した場合は、樹
脂の応力が、脆弱なLED素子に加わりLED素子の特
性を劣化させてしまう恐れがある等、表面実装型チップ
部品の信頼性の点で問題があった。
However, the above two conventional surface mount chip components have the following problems. That is, as described above, in a reliability test, when a product is used under severe environmental conditions such as a temperature cycle test or a high-temperature energization test, the coefficient of linear expansion is small,
The circuit sealing frame made of the liquid crystal polymer material or the three-dimensional molded substrate does not expand or shrink so much, whereas the sealing resin made of an epoxy resin having a large linear expansion coefficient expands and shrinks greatly. Causes deviation. As a result, when the filling resin expands, peeling occurs at the interface between the circuit sealing frame and the three-dimensional molded substrate. In addition, when shrinking, there is a problem in the reliability of the surface mount type chip component, for example, the stress of the resin may be applied to the fragile LED element and deteriorate the characteristics of the LED element.

【0025】また、絶縁基板として高価なガラエポ基板
を使用し、絶縁基板に別体の回路封止枠を導電性接着剤
等で一体化するので、金型による回路封止枠の成形、接
着剤の印刷、絶縁基板との一体化工程等を要し、コスト
アップになる。
In addition, since an expensive glass epoxy substrate is used as an insulating substrate, and a separate circuit sealing frame is integrated with the insulating substrate with a conductive adhesive or the like, the molding of the circuit sealing frame using a mold and the adhesive are performed. Printing, integration with an insulating substrate, and the like, which increases costs.

【0026】また、絶縁基板として、高価な立体成形基
板を使用し、成形基板のワイヤーボンディング面が平滑
でないため、ワイヤーボンディング不良が発生し、組立
工程の歩留りに悪影響を及ぼしてしまう等のさまざまな
問題があった。
In addition, since an expensive three-dimensional molded substrate is used as an insulating substrate, and the wire bonding surface of the molded substrate is not smooth, wire bonding failure occurs and adversely affects the yield of the assembling process. There was a problem.

【0027】本発明は上記従来の課題に鑑みなされたも
のであり、その目的は、絶縁基板及び充填する封止樹脂
に、線膨張係数の略同一な材料を使用することにより、
信頼性が向上し、回路封止枠を使用しない、寸法精度の
高い立体成形基板で、製品のコストダウン及び歩留りが
向上し、更に、輝度性能のアップを図った安価な表面実
装型チップ部品及びその製造方法を提供するものであ
る。
The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to use a material having substantially the same linear expansion coefficient for an insulating substrate and a sealing resin to be filled.
A three-dimensional molded substrate with high reliability and improved dimensional accuracy, which does not use a circuit encapsulation frame. An object of the present invention is to provide a manufacturing method thereof.

【0028】[0028]

【課題を解決するための手段】上記目的を達成するため
に、本発明における表面実装型チップ部品は、樹脂材よ
りなる絶縁基板の上面側に対向する一対の上面電極を設
け、該一対の上面電極は、それぞれその裏面に下面電極
と、その側面に、前記上面電極及び前記下面電極と連な
る側面電極を形成して、前記一方の上面電極に電子素子
の一方の電極を、他方の上面電極に前記電子素子の他方
の電極をそれぞれ接続し、樹脂封止してなる表面実装型
チップ部品において、前記絶縁基板及び封止樹脂は共に
エポキシ樹脂材よりなり、前記絶縁基板に形成された電
極面は、エボキシ樹脂の表面にメッキで形成されている
ことを特徴とするものである。
In order to achieve the above object, a surface mount chip component according to the present invention is provided with a pair of upper electrodes facing the upper surface of an insulating substrate made of a resin material. The electrodes each have a lower surface electrode on the back surface, and a side electrode connected to the upper surface electrode and the lower surface electrode on the side surface thereof. One electrode of the electronic element is formed on the one upper surface electrode and the other upper surface electrode. In a surface-mounted chip component connected to the other electrode of the electronic element and resin-sealed, the insulating substrate and the sealing resin are both made of an epoxy resin material, and the electrode surface formed on the insulating substrate is , Formed on the surface of the ethoxy resin by plating.

【0029】また、前記絶縁基板は電子素子収納凹部が
形成された立体成形基板であることを特徴とするもので
ある。
Further, the insulating substrate is a three-dimensional molded substrate in which an electronic element housing concave portion is formed.

【0030】また、前記絶縁基板の電子素子収納凹部に
ダイボンドされた電子素子は、その周囲を前記上面電極
パターンに干渉しない空きスペースに形成された光反射
用のダミーパターンで囲まれていることを特徴とするも
のである。
Further, the electronic device die-bonded to the electronic device housing recess of the insulating substrate is surrounded by a light reflection dummy pattern formed in an empty space which does not interfere with the upper electrode pattern. It is a feature.

【0031】また、前記ダミーパターンは、前記絶縁基
板表面にメッキで形成されていることを特徴とするもの
である。
Further, the dummy pattern is formed on the surface of the insulating substrate by plating.

【0032】また、前記電子素子はLED素子で、前記
絶縁基板はLED素子収納凹部が形成された立体成形基
板で、絶縁基板及び封止樹脂は共にエポキシ樹脂材より
なり、前記絶縁基板に形成された電極面は、エボキシ樹
脂の表面にメッキで形成されていることを特徴とするも
のである。
Further, the electronic element is an LED element, the insulating substrate is a three-dimensional molded substrate having a recess for accommodating the LED element, and both the insulating substrate and the sealing resin are made of an epoxy resin material. The electrode surface is formed by plating the surface of an ethoxy resin.

【0033】また、本発明における表面実装型チップ部
品の製造方法は、エポキシ樹脂よりなる多数個取りする
集合絶縁基板の各列間に長穴スルーホール、及び前記長
穴スルーホールの間で所定の間隔に電子素子収納凹部を
形成し、前記長穴スルーホール内面を含む全表面に銅メ
ッキ層を形成し、メッキレジストをラミネートし、露
光、現像後パターンマスクを形成し、パターンエッチン
グ後、Niメッキ、Auメッキ処理を行い電極パターン
を有する立体成形基板を形成する集合絶縁基板形成工程
と、前記集合絶縁基板の電子素子収納凹部に形成された
一方の上面電極から延びるダイボンドパターン上に、前
記電子素子を導電性接着剤でダイボンドする電子素子ダ
イボンド工程と、前記集合絶縁基板の電子素子収納凹部
に形成された他方の上面電極から延びるワイヤーボンド
パターン上に、電子素子からのボンディングワイヤーを
接続して電気導通をとるワイヤーボンド工程と、前記ボ
ンディングワイヤーと電子素子を保護するために前記電
子素子収納凹部にエポキシ樹脂よりなる封止樹脂を注入
する樹脂封止工程と、前記各工程を経て形成された前記
表面実装型チップ部品集合体を直交する2つのカットラ
インに沿って切断して単個の表面実装型チップ部品に分
割する切断工程とからなることを特徴とするものであ
る。
In the method of manufacturing a surface-mounted chip component according to the present invention, there is provided a method of manufacturing a surface-mounted chip component, the method comprising: An electronic element housing concave portion is formed at intervals, a copper plating layer is formed on the entire surface including the inner surface of the elongated hole, a plating resist is laminated, a pattern mask is formed after exposure and development, and after pattern etching, Ni plating is performed. Forming a three-dimensional molded substrate having an electrode pattern by performing an Au plating process; and forming the electronic element on a die bond pattern extending from one upper surface electrode formed in the electronic element housing recess of the collective insulating substrate. An electronic element die bonding step of die bonding with a conductive adhesive, and the other formed in the electronic element housing recess of the collective insulating substrate. A wire bonding step of connecting a bonding wire from an electronic element to establish electrical continuity on a wire bond pattern extending from a surface electrode; and forming an epoxy resin in the electronic element housing recess to protect the bonding wire and the electronic element. A resin sealing step of injecting a sealing resin, and cutting the surface-mounted chip component assembly formed through each of the steps along two orthogonal cut lines into a single surface-mounted chip component And a cutting step for dividing.

【0034】また、前記電子素子がLED素子であるこ
とを特徴とするものである。
Further, the electronic device is an LED device.

【0035】[0035]

【発明の実施の形態】以下図面に基づいて本発明におけ
る表面実装型チップ部品について説明する。図1は、本
発明の実施の形態である表面実装型チップ部品の斜視図
である。図において、従来技術と同一部材は同一符号で
示す。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A surface mount type chip component according to the present invention will be described below with reference to the drawings. FIG. 1 is a perspective view of a surface mount chip component according to an embodiment of the present invention. In the drawings, the same members as those of the prior art are denoted by the same reference numerals.

【0036】図1において、1は、略平行六面体形状の
エポキシ樹脂等よりなる立体成形した絶縁基板であり、
絶縁基板1には、LED素子収納凹部12の底面にLE
D素子5を固着し、前記底面及び上方に広がる4面の傾
斜面には、上面電極2a、2bと干渉しない空きスペー
スに、上面電極2a、2bと共にAuメッキされたLE
Dの光反射用ダミーパターン13が形成されている。絶
縁基板1の上面側及び傾斜面に対向する一対の上面電極
2a、2bと、下面に下面電極3a、3bと、前記上面
電極2a、2b及び下面電極3a、3bと連なるように
側面電極4a、4bが形成されている。前記一方の上面
電極2aと、その端部のダイボンドパターンは共にAu
メッキされ、ダイボンドパターンには、導電性接着剤9
の固着手段でLED素子5を固着し、前記他方の上面電
極2bと、その端部のワイヤーボンドパターンは共にA
uメッキされ、ワイヤーボンドパターンには、Auワイ
ヤ等よりなるボンディングワイヤ6がワイヤボンディン
グされている。8は、前記絶縁基板1と同材のエポキシ
樹脂等の封止樹脂で、LED素子5と接続部を保護する
ために、絶縁基板1の上面と略面一になるように樹脂封
止されている。以上の構成より表面実装型チップ部品3
0が形成されている。
In FIG. 1, reference numeral 1 denotes a three-dimensionally shaped insulating substrate made of a substantially parallelepiped-shaped epoxy resin or the like.
The insulating substrate 1 has an LE
The D element 5 is fixed, and the bottom surface and the four inclined surfaces extending upward are provided with an Au-plated LE together with the upper surface electrodes 2a, 2b in an empty space that does not interfere with the upper surface electrodes 2a, 2b.
A light reflection dummy pattern 13 of D is formed. A pair of upper electrodes 2a, 2b facing the upper surface side and the inclined surface of the insulating substrate 1, lower electrodes 3a, 3b on the lower surface, and side electrodes 4a connected to the upper electrodes 2a, 2b and the lower electrodes 3a, 3b; 4b is formed. The one upper electrode 2a and the die bond pattern at its end are both Au.
The conductive adhesive 9 is plated and the die bond pattern is
The other upper surface electrode 2b and the wire bond pattern at the end of the LED element 5 are both fixed by A.
A bonding wire 6 made of Au wire or the like is wire-bonded to the u-bonded wire bond pattern. Reference numeral 8 denotes a sealing resin such as an epoxy resin of the same material as the insulating substrate 1, which is resin-sealed so as to be substantially flush with the upper surface of the insulating substrate 1 in order to protect the LED element 5 and the connection portion. I have. With the above configuration, the surface mount chip component 3
0 is formed.

【0037】図2〜図6により、前記表面実装型チップ
部品30の製造方法について説明する。図2及び図4に
おいて、集合絶縁基板形成工程は、略四角形状をしたエ
ポキシ樹脂よりなる上下両面が銅箔張りされた多数個取
りする集合絶縁基板1Cに、所定の間隔で各列毎に複数
個の長穴スルーホール11A及び各列間で所定間隔に複
数個のLED素子収納凹部12が形成される立体成形基
板である。前記集合絶縁基板1Cの全表面を無電解メッ
キにより銅メッキ層を形成し、裏面レジストシルク印
刷、エッチング(メッキ密着性向上)、キャタリスト
(Ni無電解のためPb,Sn触媒担持)、アクセレー
ター(活性化処理)、レジスト露光(レジスト硬化)、
レジスト剥離、無電解Niメッキ、レジスト剥離、電気
Niメッキ、Auメッキフラッシュ+Auメッキ、水洗
いの各工程を経てエポキシ樹脂からなる立体成形の集合
絶縁基板が形成される。
A method of manufacturing the surface mount chip component 30 will be described with reference to FIGS. 2 and 4, the collective insulating substrate forming step includes a plurality of collective insulating substrates 1C made of a substantially rectangular epoxy resin and having upper and lower surfaces both of which are covered with copper foil. This is a three-dimensional molded substrate in which a plurality of long hole through holes 11A and a plurality of LED element housing recesses 12 are formed at predetermined intervals between rows. A copper plating layer is formed on the entire surface of the collective insulating substrate 1C by electroless plating, backside resist silk printing, etching (improvement of plating adhesion), catalyst (supporting Pb and Sn catalyst for Ni electroless), accelerator (Activation treatment), resist exposure (resist curing),
Through the steps of resist peeling, electroless Ni plating, resist peeling, electric Ni plating, Au plating flash + Au plating, and washing with water, a three-dimensionally formed collective insulating substrate made of epoxy resin is formed.

【0038】集合絶縁基板1Cの上面側には、図3(図
2の点線円で囲むC部)に示すように、LED素子収納
凹部12の傾斜面及び底部に延びる、対向する一対の上
面電極2a、2bと、前記LED素子収納凹部12の底
面及び底面周囲4面の傾斜面に、上面電極2a、2bと
干渉しない空きスペースに、Auメッキで形成された光
反射用のダミーパターン13が形成されている。下面側
には対向する一対の図示しない下面電極及び、前記上面
電極2a、2b及び前記下面電極と連なる側面電極4
a、4bが形成されている。
As shown in FIG. 3 (part C surrounded by a dotted circle in FIG. 2), a pair of opposed upper electrodes extending on the inclined surface and the bottom of the LED element housing recess 12 are provided on the upper surface side of the collective insulating substrate 1C. Light reflecting dummy patterns 13 formed by Au plating are formed on the 2a and 2b, and on the inclined surfaces of the bottom surface of the LED element accommodating recess 12 and the four peripheral surfaces of the bottom surface, in empty spaces that do not interfere with the upper electrodes 2a and 2b. Have been. On the lower surface side, a pair of lower electrodes (not shown) facing each other, and a side electrode 4 connected to the upper electrodes 2a and 2b and the lower electrode.
a, 4b are formed.

【0039】図5において、LED素子ダイボンド工程
及びワイヤーボンド工程は、図4(a)に示すLED素
子5を、個々のLED素子収納凹部12内の底面に延び
る一方の上面電極2aの端部であるダイボンドパターン
に導電性接着剤9で固着する。他方の上面電極2bの端
部であるワイヤーボンドパターンにはLED素子5から
ボンディングワイヤー6で接続する。
In FIG. 5, in the LED element die bonding step and the wire bonding step, the LED element 5 shown in FIG. 4A is attached to the end of one upper electrode 2a extending to the bottom surface in each LED element accommodating recess 12. It is fixed to a certain die bond pattern with a conductive adhesive 9. The LED element 5 is connected to the wire bond pattern, which is the end of the other upper surface electrode 2b, by a bonding wire 6.

【0040】図6における樹脂封止工程及び切断工程
は、前記LED素子収納凹部12内に、LED素子5及
びボンディングワイヤー6の接続部を保護するために、
集合絶縁基板1Cと同材のエポキシ樹脂の封止樹脂8
で、集合絶縁基板1Cの上面と略面一になるように樹脂
封止することにより表面実装型チップ部品集合体30A
が形成される。切断工程は、前記表面実装型チップ部品
集合体30Aを、直交する2つのカットライン2のX、
Y(X方向のカットランは長穴スルーホール11A上を
通る)に沿ってスライシング又はダイシング等の切断手
段で単個に分割することにより、図1で示す表面実装型
チップ部品30が完成される。
The resin sealing step and the cutting step in FIG. 6 are performed to protect the connection between the LED element 5 and the bonding wire 6 in the LED element housing recess 12.
Epoxy resin sealing resin 8 of the same material as the collective insulating substrate 1C
Then, the surface mounting type chip component assembly 30A is sealed with resin so as to be substantially flush with the upper surface of the collective insulating substrate 1C.
Is formed. In the cutting step, the surface mount type chip component assembly 30A is divided into two orthogonal cut lines 2 by X,
The surface mount type chip component 30 shown in FIG. 1 is completed by dividing into single pieces by cutting means such as slicing or dicing along Y (the cut run in the X direction passes over the elongated hole 11A). .

【0041】[0041]

【発明の効果】以上説明したように、本発明によれば、
表面実装型チップ部品において、立体成形基板及び封止
樹脂は共に同じエポキシ材のため、線膨張係数が同じな
ので、膨張・収縮の際に、基板と充填樹脂が共に、伸び
縮し、基板と樹脂の境目が剥がれる恐れがない。また、
LED素子への応力の心配もなく、製品寿命の点で効果
が極めて大きく、信頼性が向上する。
As described above, according to the present invention,
In the surface mount type chip parts, the three-dimensional molded substrate and the sealing resin are the same epoxy material, and therefore have the same linear expansion coefficient. There is no danger of the boundary being peeled off. Also,
There is no fear of stress on the LED element, the effect is extremely large in terms of product life, and the reliability is improved.

【0042】また、立体成形基板では、電極パターンと
それらの電極パターンと干渉しない空きスペースに、光
反射用のダミーパターンを同時に形成できるので、余計
な工程を掛けず、上面方向への輝度アップを図ることが
できる。
In the three-dimensional molded substrate, the dummy pattern for light reflection can be simultaneously formed in the electrode pattern and the empty space which does not interfere with the electrode pattern. Therefore, the brightness in the upper surface direction can be increased without extra steps. Can be planned.

【0043】また、従来のように、回路封止枠を使用し
ないので、金型が不要となり、更に、回路封止枠への接
着剤の印刷、これを基板と一体化する作業も不要とな
る。また、従来のMID基板が抱えていた、基板の悪い
品質(ワイヤーボンディング面が平滑でない)に起因す
る組立工程の歩留りダウンが解消される。
Further, unlike the conventional case, since no circuit sealing frame is used, a mold is not required, and further, an operation of printing an adhesive on the circuit sealing frame and integrating the same with a substrate is also unnecessary. . In addition, the reduction in the yield of the assembly process caused by the poor quality of the substrate (the wire bonding surface is not smooth) which the conventional MID substrate has is solved.

【0044】また、製造方法において、集合状態の絶縁
基板に安価なエポキシ樹脂材を使用して寸法精度の高い
立体成形基板を作り、多数個取りするので、信頼性に優
れた表面実装型チップ部品を安価に大量に製造すること
ができる。
Further, in the manufacturing method, a three-dimensional molded substrate having high dimensional accuracy is formed by using an inexpensive epoxy resin material for an insulated substrate in a collective state, and a large number of pieces are formed. Can be mass-produced inexpensively.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態に係わる表面実装型チップ
部品の斜視図である。
FIG. 1 is a perspective view of a surface mount chip component according to an embodiment of the present invention.

【図2】本発明の製造方法を示す集合絶縁基板の部分平
面図である。
FIG. 2 is a partial plan view of a collective insulating substrate showing a manufacturing method of the present invention.

【図3】図2の点線円C部の電極パターンを示す平面図
である。
FIG. 3 is a plan view showing an electrode pattern of a portion indicated by a dotted circle C in FIG. 2;

【図4】LED素子と図2の集合絶縁基板の部分斜視図
である。
FIG. 4 is a partial perspective view of the LED element and the collective insulating substrate of FIG. 2;

【図5】図4のLED素子を固着するダイボンド及びワ
イヤーボンド工程を示す集合絶縁基板の部分斜視図であ
る。
FIG. 5 is a partial perspective view of the collective insulating substrate showing a die bonding step and a wire bonding step for fixing the LED element of FIG. 4;

【図6】図5に封止樹脂を注入する樹脂封止及び切断工
程を示す表面実装型チップ部品集合体の部分斜視図であ
る。
FIG. 6 is a partial perspective view of the surface mount type chip component assembly showing a resin sealing and cutting step of injecting a sealing resin into FIG. 5;

【図7】従来の表面実装型チップ部品の製造方法を示す
集合絶縁基板の部分平面図である。
FIG. 7 is a partial plan view of a collective insulating substrate showing a conventional method of manufacturing a surface mount chip component.

【図8】図7の点線円A部の電極パターンを示す平面図
である。
FIG. 8 is a plan view showing an electrode pattern of a dotted circle A part in FIG. 7;

【図9】LED素子の斜視図である。FIG. 9 is a perspective view of an LED element.

【図10】図7にLED素子を固着するダイボンド工程
を示す集合絶縁基板の部分斜視図である。
FIG. 10 is a partial perspective view of the collective insulating substrate showing a die bonding step of fixing the LED elements to FIG.

【図11】図10にワイヤをワイヤーボンディングする
ワイヤーボンド工程を示す集合絶縁基板の部分斜視図で
ある。
FIG. 11 is a partial perspective view of the collective insulating substrate showing a wire bonding step of wire bonding wires in FIG.

【図12】図11の集合絶縁基板に回路封止枠接着工程
を示す部分斜視図である。
FIG. 12 is a partial perspective view showing a step of bonding a circuit sealing frame to the collective insulating substrate of FIG. 11;

【図13】図12の一体化された集合絶縁基板の部分斜
視図である。
FIG. 13 is a partial perspective view of the integrated collective insulating substrate of FIG.

【図14】図13に封止樹脂を注入する樹脂封止工程を
示す表面実装型チップ部品集合体の部分斜視図である。
FIG. 14 is a partial perspective view of the surface-mounted chip component assembly showing a resin sealing step of injecting a sealing resin into FIG.

【図15】図14のカッティングラインに沿って単個の
表面実装型チップ部品に切断する切断工程を示す部分斜
視図である。
FIG. 15 is a partial perspective view showing a cutting step of cutting into single surface mount chip components along the cutting line of FIG. 14;

【図16】従来の表面実装型チップ部品を示す斜視図で
ある。
FIG. 16 is a perspective view showing a conventional surface mount chip component.

【図17】従来の他の表面実装型チップ部品の製造方法
を示す集合絶縁基板の部分平面図である。
FIG. 17 is a partial plan view of a collective insulating substrate showing another conventional method of manufacturing a surface mount chip component.

【図18】図17の点線円B部の電極パターンを示す平
面図である。
FIG. 18 is a plan view showing an electrode pattern of a portion indicated by a dotted circle B in FIG. 17;

【図19】LED素子ダイボンド工程、ワイヤーボンド
工程、樹脂封止工程、切断工程を示す集合絶縁基板の部
分斜視図である。
FIG. 19 is a partial perspective view of the collective insulating substrate showing an LED element die bonding step, a wire bonding step, a resin sealing step, and a cutting step.

【図20】従来の他の表面実装型チップ部品を示す斜視
図である。
FIG. 20 is a perspective view showing another conventional surface mount chip component.

【図21】従来の表面実装型チップ部品の信頼性試験に
おける膨張のメカニズムを示す図16のA−A線断面図
である。
FIG. 21 is a sectional view taken along the line AA of FIG. 16 showing a mechanism of expansion in a reliability test of a conventional surface mount chip component.

【図22】従来の表面実装型チップ部品の信頼性試験に
おける膨張のメカニズムを示す図20のB−B線断面図
である。
FIG. 22 is a cross-sectional view taken along the line BB of FIG. 20, illustrating a mechanism of expansion in a reliability test of a conventional surface mount chip component.

【図23】従来の表面実装型チップ部品の信頼性試験に
おける収縮のメカニズムを示す図16のA−A線断面図
である。
FIG. 23 is a cross-sectional view taken along the line AA of FIG. 16 showing a contraction mechanism in a reliability test of a conventional surface mount chip component.

【図24】従来の表面実装型チップ部品の信頼性試験に
おける収縮のメカニズムを示す図20のB−B線断面図
である。
FIG. 24 is a cross-sectional view taken along the line BB of FIG. 20, illustrating a shrinkage mechanism in a reliability test of a conventional surface mount chip component.

【符号の説明】[Explanation of symbols]

1 絶縁基板 1C 集合絶縁基板 2a、2b 上面電極 3a、3b 下面電極 4a、4b 側面電極 5 LED素子 6 ボンディングワイヤ 8 封止樹脂 9 導電性接着剤 11A 長穴スルーホール 12 LED素子収納凹部 13 ダミーパターン 30 表面実装型チップ部品 30A 表面実装型チップ部品集合体 DESCRIPTION OF SYMBOLS 1 Insulating substrate 1C Collective insulating substrate 2a, 2b Upper electrode 3a, 3b Lower electrode 4a, 4b Side electrode 5 LED element 6 Bonding wire 8 Sealing resin 9 Conductive adhesive 11A Slot through hole 12 LED element storage recess 13 Dummy pattern 30 Surface Mount Chip Component 30A Surface Mount Chip Assembly

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 樹脂材よりなる絶縁基板の上面側に対向
する一対の上面電極を設け、該一対の上面電極は、それ
ぞれその裏面に下面電極と、その側面に、前記上面電極
及び前記下面電極と連なる側面電極を形成して、前記一
方の上面電極に電子素子の一方の電極を、他方の上面電
極に前記電子素子の他方の電極をそれぞれ接続し、樹脂
封止してなる表面実装型チップ部品において、前記絶縁
基板及び封止樹脂は共にエポキシ樹脂材よりなり、前記
絶縁基板に形成された電極面は、エボキシ樹脂の表面に
メッキで形成されていることを特徴とする表面実装型チ
ップ部品。
1. A pair of upper electrodes facing each other on an upper surface of an insulating substrate made of a resin material, wherein each of the pair of upper electrodes has a lower electrode on its back surface, and the upper electrode and the lower electrode on its side surfaces. A surface mounting chip formed by forming a side electrode connected to the first upper electrode and connecting the one electrode of the electronic element to the one upper electrode and the other electrode of the electronic element to the other upper electrode, respectively, and sealing with a resin. In the component, the insulating substrate and the sealing resin are both made of an epoxy resin material, and an electrode surface formed on the insulating substrate is formed by plating a surface of an ethoxy resin. .
【請求項2】 前記絶縁基板は電子素子収納凹部が形成
された立体成形基板であることを特徴とする請求項1記
載の表面実装型チップ部品。
2. The surface-mounted chip component according to claim 1, wherein said insulating substrate is a three-dimensional molded substrate having an electronic element housing recess formed therein.
【請求項3】 前記絶縁基板の電子素子収納凹部にダイ
ボンドされた電子素子は、その周囲を前記上面電極パタ
ーンに干渉しない空きスペースに形成された光反射用の
ダミーパターンで囲まれていることを特徴とする請求項
1記載の表面実装型チップ部品。
3. An electronic device die-bonded to an electronic device housing recess of the insulating substrate, the periphery of which is surrounded by a light reflection dummy pattern formed in an empty space which does not interfere with the upper electrode pattern. The surface-mounted chip component according to claim 1, wherein:
【請求項4】 前記ダミーパターンは、前記絶縁基板表
面にメッキで形成されていることを特徴とする請求項3
記載の表面実装型チップ部品。
4. The method according to claim 3, wherein the dummy pattern is formed on the surface of the insulating substrate by plating.
Surface mount type chip parts as described.
【請求項5】 前記電子素子はLED素子で、前記絶縁
基板はLED素子収納凹部が形成された立体成形基板
で、絶縁基板及び封止樹脂は共にエポキシ樹脂材よりな
り、前記絶縁基板に形成された電極面は、エボキシ樹脂
の表面にメッキで形成されていることを特徴とする請求
項1記載の表面実装型チップ部品。
5. The electronic element is an LED element, the insulating substrate is a three-dimensional molded substrate having a recess for accommodating an LED element formed therein, and both the insulating substrate and the sealing resin are made of an epoxy resin material. 2. The surface-mounted chip component according to claim 1, wherein the electrode surface is formed by plating the surface of an ethoxy resin.
【請求項6】 エポキシ樹脂よりなる多数個取りする集
合絶縁基板の各列間に長穴スルーホール、及び前記長穴
スルーホールの間で所定の間隔に電子素子収納凹部を形
成し、前記長穴スルーホール内面を含む全表面に銅メッ
キ層を形成し、メッキレジストをラミネートし、露光、
現像後パターンマスクを形成し、パターンエッチング
後、Niメッキ、Auメッキ処理を行い電極パターンを
有する立体成形基板を形成する集合絶縁基板形成工程
と、前記集合絶縁基板の電子素子収納凹部に形成された
一方の上面電極から延びるダイボンドパターン上に、前
記電子素子を導電性接着剤でダイボンドする電子素子ダ
イボンド工程と、前記集合絶縁基板の電子素子収納凹部
に形成された他方の上面電極から延びるワイヤーボンド
パターン上に、電子素子からのボンディングワイヤーを
接続して電気導通をとるワイヤーボンド工程と、前記ボ
ンディングワイヤーと電子素子を保護するために前記電
子素子収納凹部にエポキシ樹脂よりなる封止樹脂を注入
する樹脂封止工程と、前記各工程を経て形成された前記
表面実装型チップ部品集合体を直交する2つのカットラ
インに沿って切断して単個の表面実装型チップ部品に分
割する切断工程とからなることを特徴とする表面実装型
チップ部品の製造方法。
6. An elongated hole through hole is formed between each row of a plurality of collective insulating substrates made of epoxy resin, and an electronic element housing recess is formed at a predetermined interval between the elongated hole through holes. Form a copper plating layer on the entire surface including the inner surface of the through hole, laminate a plating resist, expose,
After the development, a pattern mask is formed. After pattern etching, Ni plating and Au plating are performed to form a three-dimensional molded substrate having an electrode pattern. An electronic element die bonding step of die bonding the electronic element with a conductive adhesive on a die bond pattern extending from one upper electrode, and a wire bond pattern extending from the other upper electrode formed in the electronic element housing recess of the collective insulating substrate. A wire bonding step of connecting a bonding wire from an electronic element to establish electrical continuity, and injecting a sealing resin made of epoxy resin into the electronic element housing recess to protect the bonding wire and the electronic element. A sealing step and the surface-mounted chip component formed through the above steps Two method of manufacturing a surface mount type chip components, characterized by comprising a cutting step of dividing by cutting along a cut line to a single number of surface-mounted chip component perpendicular coalescence.
【請求項7】 前記電子素子がLED素子であることを
特徴とする請求項5記載の表面実装型チップ部品の製造
方法。
7. The method according to claim 5, wherein the electronic element is an LED element.
JP24592697A 1997-08-28 1997-08-28 Surface mount type chip component and manufacturing method thereof Expired - Lifetime JP3900613B2 (en)

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Application Number Priority Date Filing Date Title
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JPH1174420A true JPH1174420A (en) 1999-03-16
JP3900613B2 JP3900613B2 (en) 2007-04-04

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Country Link
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