JPH1117070A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH1117070A JPH1117070A JP9163737A JP16373797A JPH1117070A JP H1117070 A JPH1117070 A JP H1117070A JP 9163737 A JP9163737 A JP 9163737A JP 16373797 A JP16373797 A JP 16373797A JP H1117070 A JPH1117070 A JP H1117070A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor device
- wiring board
- semiconductor
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子を樹脂
により回路基板に接続されたＣＯＢ(chip on board)構
造の特にＦＣＡ(flip chip attach)構造を持つ半導体の
実装構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a COB (chip on board) structure in which a semiconductor element is connected to a circuit board by a resin, and more particularly to a semiconductor mounting structure having an FCA (flip chip attach) structure.
【０００２】[0002]
【従来の技術】従来の樹脂封止型半導体装置は、封止す
る樹脂の硬化収縮によって基板に反りが発生していた。
そこで特開平８−２７９５７０号（図２）公報に示され
るように、上基板と下基板をリードによって接続し、そ
の間に充填される樹脂の硬化収縮による反りの発生を制
御する方法が提案されていた。2. Description of the Related Art In a conventional resin-encapsulated semiconductor device, a substrate is warped due to curing shrinkage of a resin to be encapsulated.
Therefore, as disclosed in Japanese Patent Application Laid-Open No. 8-279570 (FIG. 2), a method has been proposed in which an upper substrate and a lower substrate are connected by leads, and the generation of warpage due to curing shrinkage of a resin filled therebetween is controlled. Was.
【０００３】[0003]
【発明が解決しようとする課題】従来技術では、リード
を複数配置することによって、配線基板の反りの発生を
機械的に防止していた。しかし、この方法では多数のリ
ードを平行に配置しなければ効果が得られず、さらにリ
ードが電極同士を結ぶ配線を兼ねているため接続不良が
生じ半導体装置の不良となっていた。In the prior art, warping of the wiring board was mechanically prevented by arranging a plurality of leads. However, in this method, an effect cannot be obtained unless a large number of leads are arranged in parallel, and furthermore, since the leads also serve as wiring for connecting the electrodes, a connection failure occurs, resulting in a semiconductor device failure.
【０００４】[0004]
【課題を解決するための手段】配線基板上の半導体素子
を樹脂によって封止した場合、配線基板が樹脂の収縮に
より反りが発生する。これは配線基板が樹脂の収縮に耐
えきれないため起こる。そこで半導体素子を中心に樹脂
と配線基板を対称に配置することにより、樹脂の硬化収
縮による力が等しく釣り合うようにした半導体装置をに
ある。When a semiconductor element on a wiring board is sealed with a resin, the wiring board is warped due to shrinkage of the resin. This occurs because the wiring board cannot withstand the shrinkage of the resin. Therefore, there is a semiconductor device in which a resin and a wiring board are symmetrically arranged around a semiconductor element so that forces due to curing and shrinkage of the resin are equally balanced.
【０００５】[0005]
【発明の実施の形態】図１に本発明の形態の１例を示
す。突起電極１４を具備した半導体素子１１は下配線基
板１２に下樹脂１５によって接続されている。半導体素
子１１と下配線基板１２との電気的な接続は、突起電極
１４と突起電極と対向に配置された電極（図示せず）に
よって行われている。FIG. 1 shows an embodiment of the present invention. The semiconductor element 11 having the protruding electrode 14 is connected to the lower wiring board 12 by the lower resin 15. The electrical connection between the semiconductor element 11 and the lower wiring board 12 is made by a protruding electrode 14 and an electrode (not shown) arranged opposite to the protruding electrode.
【０００６】半導体素子の上面には下樹脂１５と同質の
上樹脂１６が配置され、上配線基板１３に機械的に接続
されている。上樹脂１６の厚さは下樹脂１５と同等に配
置した。図示してはいないが樹脂の厚さを同じにするた
め半導体素子の突起電極と同じ高さの突起電極を上基板
１３に配置した。本半導体装置は半導体装置１１の最も
広い面の範囲内において半導体素子１１を中心に、対称
に樹脂，配線基板等の接続部材が配置されている。本形
態をとることにより半導体装置の配線基板に反りの発生
を抑制できる。An upper resin 16 of the same quality as the lower resin 15 is disposed on the upper surface of the semiconductor element, and is mechanically connected to the upper wiring board 13. The thickness of the upper resin 16 was the same as that of the lower resin 15. Although not shown, a projection electrode having the same height as the projection electrode of the semiconductor element was arranged on the upper substrate 13 in order to make the thickness of the resin the same. In the present semiconductor device, connection members such as a resin and a wiring board are symmetrically arranged around the semiconductor element 11 within the range of the widest surface of the semiconductor device 11. According to this embodiment, warpage of the wiring substrate of the semiconductor device can be suppressed.
【０００７】図３に本発明の形態の他の１例を示す。突
起電極１４を具備した複数の半導体素子１１は１つの下
配線基板１２に下樹脂１５によって接続されている。下
樹脂１５同士はチップ間に表面実装部品（図示せず）を
配置するために半導体素子１１個別に配置してある。上
樹脂１６は複数の半導体素子１１上に下樹脂１５の厚さ
と同じ厚さを配置し上基板１３に接続してある。上樹脂
１６の厚さを下樹脂１５の厚さと同じにするために、上
基板１３に半導体素子１１に具備した突起電極１４と同
等の突起電極（図示せず）を配置した。FIG. 3 shows another example of the embodiment of the present invention. The plurality of semiconductor elements 11 having the protruding electrodes 14 are connected to one lower wiring board 12 by the lower resin 15. The lower resins 15 are individually arranged on the semiconductor elements 11 in order to arrange surface mounting components (not shown) between chips. The upper resin 16 has the same thickness as the lower resin 15 on the plurality of semiconductor elements 11 and is connected to the upper substrate 13. In order to make the thickness of the upper resin 16 the same as the thickness of the lower resin 15, a bump electrode (not shown) equivalent to the bump electrode 14 provided on the semiconductor element 11 is arranged on the upper substrate 13.
【０００８】本半導体装置は半導体素子１１の最も広い
面の範囲内において半導体素子１１を中心に対称に樹
脂、配線基板棟の接続部材を配置した。本形態をとるこ
とにより半導体装置の配線基板に反りの発生が抑制でき
る。In this semiconductor device, the resin and the connecting members of the wiring board building are arranged symmetrically with respect to the semiconductor element 11 within the widest surface of the semiconductor element 11. According to this embodiment, warpage of the wiring substrate of the semiconductor device can be suppressed.
【０００９】図４に本発明の形態の他の１例を示す。突
起電極１４を具備した複数の半導体素子１１は１つの下
基板１２に下樹脂１５によって接続されている。下樹脂
１５と上樹脂１６はお互いの高さを同一にするためにフ
ィルム状の樹脂を使用し高さを均一にした。上基板１３
は上樹脂１６上に下基板１２と平行に配置してある。FIG. 4 shows another example of the embodiment of the present invention. The plurality of semiconductor elements 11 having the protruding electrodes 14 are connected to one lower substrate 12 by a lower resin 15. The lower resin 15 and the upper resin 16 are made of a film-like resin so that the heights of the lower resin 15 and the upper resin 16 are the same, and the heights are made uniform. Upper substrate 13
Are arranged on the upper resin 16 in parallel with the lower substrate 12.
【００１０】図５に本発明の形態の他の１例を示す。突
起電極１４を具備した高さの異なる半導体素子１１は、
１つの下基板１２に下樹脂１５により接続されている。
半導体素子１１はそれぞれ高さが違うため半導体素子１
１上の上樹脂１６の高さが異なる。このため上に配置し
た上基板１３もチップ毎に配置してある。FIG. 5 shows another example of the embodiment of the present invention. The semiconductor elements 11 having different heights having the protruding electrodes 14 are:
It is connected to one lower substrate 12 by a lower resin 15.
Since the semiconductor elements 11 have different heights, the semiconductor elements 1
The height of the upper resin 16 on the top 1 differs. For this reason, the upper substrate 13 disposed above is also disposed for each chip.
【００１１】上樹脂１６の高さを下樹脂１５と同じにす
るために上基板１３に半導体素子１１と同じ突起電極１
４と同等の突起電極（図示せず）を配置した。本半導体
装置は半導体素子１１の最も広い面の範囲内において半
導体素子１１を中心に対称に樹脂、配線基板棟の接続部
材を配置した。本形態をとることにより半導体装置の配
線基板に反りが発生することはない。In order to make the height of the upper resin 16 the same as that of the lower resin 15, the same projection electrode 1 as the semiconductor element 11 is formed on the upper substrate 13.
A bump electrode (not shown) equivalent to No. 4 was arranged. In this semiconductor device, the resin and the connection member of the wiring board building are arranged symmetrically around the semiconductor element 11 within the widest surface of the semiconductor element 11. According to this embodiment, the wiring substrate of the semiconductor device does not warp.
【００１２】[0012]
【発明の効果】半導体素子を中心に半導体装置の部材が
対称に配置されることにより、原因となる樹脂の硬化収
縮が半導体素子の上下両面で起こる。この結果、半導体
装置の上下両面に発生する力は釣り合っているため半導
体装置に反りは発生しない。By symmetrically arranging the members of the semiconductor device around the semiconductor element, shrinkage of the resin which causes the curing occurs on the upper and lower surfaces of the semiconductor element. As a result, since the forces generated on both the upper and lower surfaces of the semiconductor device are balanced, the semiconductor device does not warp.
【図１】本発明の実施例の１例である半導体装置の模式
断面図。FIG. 1 is a schematic cross-sectional view of a semiconductor device which is an example of an embodiment of the present invention.
【図２】従来の半導体装置の模式断面図。FIG. 2 is a schematic cross-sectional view of a conventional semiconductor device.
【図３】本発明の実施例の他の１例である半導体装置の
模式断面図。FIG. 3 is a schematic sectional view of a semiconductor device as another example of the embodiment of the present invention.
【図４】本発明の実施例の他の１例である半導体装置の
模式断面図。FIG. 4 is a schematic sectional view of a semiconductor device as another example of the embodiment of the present invention.
【図５】本発明の実施例の他の１例である半導体装置の
模式断面図。FIG. 5 is a schematic sectional view of a semiconductor device as another example of the embodiment of the present invention.
１…半導体素子、 ２…下基板、３…上基板、４…リー
ド、６…封止樹脂、１１…半導体装置、１２…下回路基
板、１３…上回路基板、１４…突起電極、１５…下樹
脂、 １６…上樹脂。DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Lower board, 3 ... Upper board, 4 ... Lead, 6 ... Sealing resin, 11 ... Semiconductor device, 12 ... Lower circuit board, 13 ... Upper circuit board, 14 ... Projection electrode, 15 ... Lower Resin, 16 ... Upper resin.
Claims (6)
電極と対向した電極を具備した配線基板と前記半導体素
子と前記配線基板の間に樹脂を配置している半導体装置
において、前記半導体素子を中心にチップの最も広い面
の範囲内において対称となるように配置された樹脂及び
配線基板を配置することを特徴とする半導体装置。1. A semiconductor device comprising: a semiconductor element having a protruding electrode; a wiring board having an electrode facing the protruding electrode; and a semiconductor device having a resin disposed between the semiconductor element and the wiring board. A semiconductor device, comprising a resin and a wiring substrate arranged symmetrically at the center within the range of the widest surface of the chip.
ている樹脂には導電性フィラーが混入されている半導体
装置。2. The semiconductor device according to claim 1, wherein a conductive filler is mixed in the resin disposed.
記突起電極と対向した電極を具備した配線基板と前記複
数の半導体素子と前記配線基板の間に樹脂を配置してい
る半導体装置において、前記複数の半導体素子を中心に
各チップの最も広い面の範囲内において対称となるよう
に配置された樹脂及び配線基板を配置することを特徴と
する半導体装置。3. A semiconductor device comprising: a plurality of semiconductor elements provided with protruding electrodes; a wiring board provided with electrodes facing the protruding electrodes; and a resin device disposed between the plurality of semiconductor elements and the wiring board. A semiconductor device, wherein a resin and a wiring board are arranged so as to be symmetrical within the range of the widest surface of each chip around the plurality of semiconductor elements.
ている樹脂には導電性フィラーが混入されている半導体
装置。4. The semiconductor device according to claim 3, wherein a conductive filler is mixed in the resin disposed.
５は下基板１２全面を覆い、上樹脂１６は上基板１３全
面を覆うように配置されている半導体装置。5. The semiconductor device according to claim 3, wherein the lower resin
Reference numeral 5 denotes a semiconductor device that covers the entire lower substrate 12 and the upper resin 16 covers the entire upper substrate 13.
６及び上基板１３はチップ毎に分離している半導体装
置。6. The semiconductor device according to claim 3, wherein the upper resin
6 and the upper substrate 13 are semiconductor devices separated for each chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9163737A JPH1117070A (en) | 1997-06-20 | 1997-06-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9163737A JPH1117070A (en) | 1997-06-20 | 1997-06-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1117070A true JPH1117070A (en) | 1999-01-22 |
Family
ID=15779725
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9163737A Pending JPH1117070A (en) | 1997-06-20 | 1997-06-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1117070A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100406447B1 (en) * | 1999-12-30 | 2003-11-20 | 앰코 테크놀로지 코리아 주식회사 | semiconductor package and its manufacturing method |
| JP2010186763A (en) * | 2009-02-10 | 2010-08-26 | Sharp Corp | Semiconductor module |
| US8207619B2 (en) | 2009-03-27 | 2012-06-26 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| JP2018154092A (en) * | 2017-03-21 | 2018-10-04 | 株式会社リコー | Method for manufacturing three-dimensional molded article and method for making data of three-dimensional molded article |
-
1997
- 1997-06-20 JP JP9163737A patent/JPH1117070A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100406447B1 (en) * | 1999-12-30 | 2003-11-20 | 앰코 테크놀로지 코리아 주식회사 | semiconductor package and its manufacturing method |
| JP2010186763A (en) * | 2009-02-10 | 2010-08-26 | Sharp Corp | Semiconductor module |
| JP4700114B2 (en) * | 2009-02-10 | 2011-06-15 | シャープ株式会社 | Semiconductor module |
| US8207619B2 (en) | 2009-03-27 | 2012-06-26 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| US8404517B2 (en) | 2009-03-27 | 2013-03-26 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| JP2018154092A (en) * | 2017-03-21 | 2018-10-04 | 株式会社リコー | Method for manufacturing three-dimensional molded article and method for making data of three-dimensional molded article |
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