WO2020237630A1

WO2020237630A1 - Chip packaging structure and circuit structure

Info

Publication number: WO2020237630A1
Application number: PCT/CN2019/089544
Authority: WO
Inventors: 张童龙
Original assignee: 华为技术有限公司
Priority date: 2019-05-31
Filing date: 2019-05-31
Publication date: 2020-12-03
Also published as: CN113906556A

Abstract

A chip packaging structure and a circuit structure, which is used for reducing the stress born by solder balls (90) provided between the chip packaging structure and a PCB (30), thereby improving the reliability of the solder ball (90). The chip packaging structure comprises: a package carrier (20), at least one chip (10), and a heat-dissipation component (40). The at least one chip (10) is fixed on the package carrier (20). The heat-dissipation component (40) comprises a heat-dissipation cover (401) and a support portion (402). The heat-dissipation cover (401) is fastened on a top (10b) of the at least one chip (10). The support portion (402) is fixedly connected to the heat-dissipation cover (401), and is fixedly attached to a side portion (20c) of the package carrier (20). The support portion (402) extends from the side portion (20c) of the package carrier (20) to a bottom (20b) thereof, and exceeds the surface of the bottom (20b) thereof.

Description

Chip packaging structure and circuit structure

Technical field

This application relates to the field of chip packaging, in particular to a chip packaging structure and a circuit structure.

Background technique

Ball grid array (BGA) packaging products are an important electronic packaging product. The components of BGA package products include: heat dissipation cover, chip, package carrier and printed circuit board (PCB). Among them, the heat dissipation cover is used to dissipate the heat generated by the chip in the working process to the external environment. The heat dissipation cover is supported on the package carrier, and the enclosed space can accommodate the chip. The package carrier is electrically connected to the chip and connects electrical signals. Pass to the PCB.

In the prior art, the package carrier and the PCB are connected by solder balls. The solder balls bear all the weight of the package carrier and other structures connected to it. As the chip package structure increases and the chip size increases, the package carrier and The stress between PCBs is correspondingly increased, and the reliability of solder balls is reduced, which may not meet the requirements of reliability and chip service life.

Summary of the invention

The present application provides a chip packaging structure and a circuit structure, which can reduce the stress borne by the solder balls arranged between the package carrier and the PCB, thereby improving the reliability of the solder balls.

In a first aspect, the present application provides a chip packaging structure, including: a package carrier, at least one chip, and a heat dissipation component; the at least one chip is fixed on the package carrier; the heat dissipation component includes a heat dissipation cover and a support part , Wherein the heat dissipation cover is buckled on the top of the at least one chip, the support portion is fixedly connected to the heat dissipation cover, and is fixedly mounted on the side of the package carrier, and the support portion is along The side portion of the package carrier extends to the bottom of the package carrier and exceeds the bottom surface of the package carrier.

With reference to the first aspect, in a first alternative embodiment, the support portion is fixed on the printed circuit board PCB.

In combination with the first aspect or the first optional implementation manner of the first aspect, in a second optional implementation manner, the package carrier is fixed on the PCB.

With reference to the first aspect and any one of the first or second optional implementation manners of the first aspect, in a third optional implementation manner of the first aspect of the present application, the support portion includes: at least One first support portion and at least one second support portion; each first support portion of the at least one first support portion is fixedly connected to the heat dissipation cover; each first support portion of the at least one second support portion The two supporting parts are fixedly connected to one first supporting part of the at least one first supporting part, and each second supporting part of the at least one second supporting part extends along the side of the package carrier. The bottom of the package carrier extends and exceeds the bottom surface of the package carrier.

In combination with the third optional implementation manner of the first aspect, in the fourth optional implementation manner of the first aspect of the present application, each of the at least one second support portion is fixed in the printing On the circuit board PCB.

In combination with the first aspect and any one of the first to fourth optional implementation manners of the first aspect, in the fifth optional implementation manner of the first aspect of the present application, the packaging carrier and the A rewiring layer RDL or a substrate intermediate layer interposer is also arranged between at least one chip.

With reference to the first aspect and any one of the first to fifth optional implementation manners of the first aspect, in the sixth optional implementation manner of the first aspect of the present application, each of the at least one chip The top of each chip is also provided with a heat dissipation glue layer, and the heat dissipation cover is in contact with the heat dissipation glue layer.

In combination with the first aspect and any one of the first to sixth optional implementation manners of the first aspect, in the seventh optional implementation manner of the first aspect of the present application, it further includes: a plastic package, so The plastic package is wrapped around the side wall of each chip in the at least one chip, and is used to fix the at least one chip.

With reference to the first aspect and any one of the first to seventh optional implementation manners of the first aspect, in an eighth optional implementation manner of the first aspect of the present application, the packaging carrier is a substrate.

In a second aspect, the present application provides a chip packaging structure, including: a package carrier, at least one chip, and a fixing component; the at least one chip is fixed on the package carrier; the fixing component includes a reinforcing ring and a supporting part , Wherein the supporting portion is fixedly connected to the reinforcing ring and is fixedly attached to the side portion of the package carrier, and the supporting portion extends along the side portion of the package carrier to the bottom of the package carrier , And beyond the bottom surface of the package carrier.

With reference to the second aspect, in the first optional implementation of the second aspect of the present application, the support portion is fixed on the printed circuit board PCB.

In combination with the second aspect and the first optional implementation manner of the second aspect, in a second optional implementation manner of the second aspect of the present application, the package carrier is fixed on the PCB.

With reference to the second aspect and any one of the first to second optional implementation manners of the second aspect, in a third optional implementation manner of the second aspect of the present application, the support portion includes: at least One first support portion and at least one second support portion; each first support portion of the at least one first support portion is fixedly connected to the reinforcing ring; each first support portion of the at least one second support portion The two supporting portions are fixedly connected to one of the at least one first supporting portion, and are fixedly mounted on the side portion of the package carrier. Each second supporting portion of the at least one second supporting portion The supporting portion extends along the side of the package carrier to the bottom of the package carrier and exceeds the bottom surface of the package carrier.

In combination with the second aspect and any one of the first to third optional implementation manners of the second aspect, in the fourth optional implementation manner of the second aspect of the present application, the at least one second support Each of the second supporting parts of the parts is fixed on the printed circuit board PCB.

With reference to the second aspect and any one of the first to fourth optional implementation manners of the second aspect, in a fifth optional implementation manner of the second aspect of the present application, the packaging carrier is a substrate.

In a third aspect, the present application provides a chip packaging structure, including: a packaging carrier, at least one chip, and a reinforcement ring; the upper surface of the packaging carrier is opposite to the active surface of the at least one chip; The lower surface is opposite to the upper surface of the PCB; the reinforcing ring is connected to the upper surface of the package carrier, and along the first direction, the projection of the reinforcing ring in the plane where the upper surface of the package carrier is located exceeds all For the upper surface of the package carrier, the first direction is perpendicular to the plane where the upper surface of the package carrier is located.

With reference to the third aspect, in the first optional implementation of the third aspect of the present application, a redistribution layer RDL or liner is further provided between the upper surface of the package carrier and the active surface of the at least one chip. The bottom middle layer interposer.

With reference to the third aspect and the first optional implementation manner of the third aspect, in a second optional implementation manner of the third aspect of the present application, the packaging carrier is a substrate.

In a fourth aspect, the present application provides a circuit structure, including the chip packaging structure and the printed circuit board PCB described in the first to third aspects above, wherein the support portion in the chip packaging structure is fixed on the On the PCB, the package carrier in the chip package structure is fixed on the PCB, and is electrically connected to the PCB for signal transmission.

The chip packaging structure provided by the embodiments of the present application includes: a packaging carrier, at least one chip, and a heat dissipation component. The at least one chip is fixed on the packaging carrier. The heat dissipation component includes a heat dissipation cover and a supporting portion. Connected, the support part is fixedly connected with the heat dissipation cover, and is fixedly mounted on the side part of the package carrier, and the support part extends along the side part of the package carrier to the bottom of the package carrier and exceeds the bottom surface of the package carrier. Since the support part of the heat dissipation component exceeds the bottom surface of the package carrier and can be fixed on the PCB, the support part can bear part of the weight of the chip package structure, and then share a part of the multiple solder balls arranged between the chip package structure and the PCB The stress reduces the stress borne by the multiple solder balls, thereby improving the reliability of the multiple solder balls.

Description of the drawings

Figure 1 is a schematic cross-sectional view of a chip packaging structure;

2 is a schematic cross-sectional view of a chip packaging structure provided by an embodiment of the application;

3 is a top view of a chip packaging structure provided by an embodiment of the application;

4 is a schematic cross-sectional view of a chip packaging structure provided by an embodiment of the application;

5a is a schematic cross-sectional view of a chip packaging structure provided by an embodiment of the application;

5b is a schematic cross-sectional view of a chip packaging structure provided by an embodiment of the application;

6a is a schematic cross-sectional view of a chip packaging structure provided by an embodiment of the application;

6b is a schematic cross-sectional view of a chip packaging structure provided by an embodiment of the application

7a is a schematic cross-sectional view of a chip packaging structure provided by an embodiment of the application;

7b is a schematic cross-sectional view of a chip packaging structure provided by an embodiment of the application;

FIG. 8 is a schematic cross-sectional view of a chip packaging structure;

9 is a schematic cross-sectional view of a chip packaging structure provided by an embodiment of the application;

10 is a top view of a chip packaging structure provided by an embodiment of the application;

11 is a schematic cross-sectional view of a chip packaging structure provided by an embodiment of the application;

FIG. 12 is a top view of a chip packaging structure provided by an embodiment of the application;

FIG. 13 is a schematic cross-sectional view of a chip packaging structure provided by an embodiment of the application.

Detailed ways

The present application provides a chip packaging structure, which can reduce the stress borne by the solder balls arranged between the package carrier and the PCB, thereby improving the reliability of the solder balls.

The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, without having to use To describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments described herein can be implemented in an order other than the content illustrated or described herein. In addition, the terms "including" and "having" and any variations of them are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to the clearly listed Those steps or units may include other steps or units that are not clearly listed or are inherent to these processes, methods, products, or equipment.

Certain words are used in the description and claims to refer to specific components. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. This specification and claims do not use differences in names as the way of interval components, but use differences in functions of components as the criteria for distinction.

The technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are only a part of the embodiments of this application, not all of them. The following specific embodiments can be combined with each other, and the same or similar content will not be repeated in different embodiments. It should also be noted that the length, width, and height (or thickness) of the various components shown in the embodiments of the present application are only exemplary descriptions, and are not limited to the chip packaging structure described in the present application.

Figure 1 is a schematic cross-sectional view of a chip packaging structure. 1, the chip packaging structure includes: a heat dissipation cover 401, a chip 10, a packaging carrier 20, and a heat dissipation adhesive layer 70. The heat dissipation adhesive layer 70 is provided between the heat dissipation cover 401 and the top of the chip 10 for emitting the chip 10 and other structures. The heat is transferred to the heat dissipation cover 401, the chip 10 is fixed on the package carrier 20, and the heat dissipation cover 401 in FIG. 1 is buckled on the top of the chip 10. The bottom surface 20b of the package carrier 20 is fixed on the top surface 30a of the PCB 30 through a plurality of solder balls 90.

In the structure shown in FIG. 1, the multiple solder balls 90 bear the full weight of the chip package structure. As the chip package structure increases and the chip size increases, the stress between the package carrier 20 and the PCB 30 is also corresponding. The increase in size reduces the reliability of the solder ball 90, which may not meet the requirements of reliability and chip service life.

In order to solve the above technical problems, the present application provides a chip packaging structure. Referring to FIG. 2, FIG. 2 is a schematic cross-sectional view of a chip packaging structure provided by an embodiment of the application. 2, the chip packaging structure shown in FIG. 2 includes a chip 10, a packaging carrier 20, a heat dissipation assembly 40, a connecting member 50, a plastic package 60, a heat dissipation adhesive layer 70 and a primer 80.

It should be noted that although the number of chips 10 shown in the figure is two, in actual applications, the number of chips 10 included in the chip packaging structure may be one or more, which is not limited here.

2, the chip 10 includes a top and a bottom. The bottom surface 10a and the top surface 10b of the chip 10 are opposite to each other. For a flat panel, the relationship between the two planes facing away from the flat panel can be called opposing. The chip is a flat plate. Therefore, the bottom surface 10a and the top surface 10b of the chip are two planes that deviate from each other in the chip 10.

It should be noted that although the active surface of the chip 10 in FIG. 2 is the bottom surface 10a, in practical applications, the active surface can be set to face the package carrier 20, or it can be set to face the package carrier 20, namely The active surface of the chip 10 may be the bottom surface 10a shown in FIG. 2 or the top surface 10b, which is not limited in this application.

Referring to FIG. 2, in the embodiment of the present application, in order to make the bottom surface 10 a or the top surface 10 b between the multiple chips 10 lie on the same plane, the multiple chips 10 may be fixed by a plastic package 60. Optionally, the plastic package 60 may wrap the sidewalls of multiple chips for fixing multiple chips 10. Optionally, the plastic package 60 may be formed by pouring a powdered thermoplastic material or a liquid thermoplastic material on the sidewall of the chip. For example, the thermoplastic material may be, but not limited to, a thermoplastic resin.

It should be noted that although the plastic package 60 shown in FIG. 2 wraps a part of the side wall of the chip 10, and the plastic package 60 does not wrap the bottom surface 10 a and the bottom surface 10 b of the chip 10. In practical applications, the plastic encapsulation body 60 can wrap all the sidewalls of the chip 10, as long as the plastic encapsulation body 60 can fix the chip 10, and this application will not be exhaustive.

Although not shown in FIG. 2, multiple pads may be provided on the bottom surface 10 a of the chip 10. In the embodiment of the present application, a plurality of solder balls 90 are arranged on the plurality of pads, and each of the plurality of pads is connected to the top surface 20a of the package carrier 20 through a solder ball 90, thereby realizing the chip 10 Electrical connection with the package carrier 20.

It should be noted that in an actual product, each of the multiple pads may also be connected to the top surface 20a of the package carrier 20 through metal bumps or other structures, which is not limited in this application.

It should be noted that in actual products, the active surface of the chip may face away from the package carrier 20, that is, the top surface 10b of the chip 10 shown in FIG. 2 may be the active surface. At this time, the chip 10 can be jumped The wire is directly connected to the top surface 20a of the package carrier 20, which is not limited in this application.

Referring to FIG. 2, the chip packaging structure may include a primer 80, which is added between the package carrier 20 and the chip 10, or between each chip of a plurality of chips 10. The primer may be a specially designed epoxy, which is used to fill the gap between the package carrier 20 and the chip 10 or between the individual chips of the plurality of chips 10 and to wrap the plurality of solder balls 90. The primer 80 can control the pressure at the solder joint caused by the thermal expansion difference between the chip 10 and the package carrier 20. The primer 80 can absorb pressure, thereby reducing the pressure on the plurality of solder balls 90, thereby prolonging the life of the package structure.

The packaging carrier 20 in the embodiment of the present application may be a packaging substrate, and the packaging substrate may include multiple metal wiring layers. For example, the packaging substrate may include two metal wiring layers, and the two metal wiring layers are arranged on the packaging substrate. On the top surface 20a and the bottom surface 20b, the two metal wiring layers can be connected to each other through a plurality of plated through holes. It should be understood that the package carrier 20 may include multiple metal wiring layers, for example, four or six layers. In another embodiment, the package carrier may be a lead frame.

In the embodiment of the present application, the package carrier 20 may be fixed on the PCB 30. As shown in FIG. 2, the bottom surface 20b of the package carrier 20 faces the top surface 30a of the PCB 30, and the bottom surface 20b of the package carrier 20 can pass through The plurality of solder balls 90 are electrically connected to the top surface 30a of the PCB 30.

2, the chip packaging structure provided by the present application includes a heat dissipation assembly 40. Specifically, the heat dissipation assembly 40 includes a heat dissipation cover 401 and a supporting portion 402. The heat dissipation cover 401 is buckled on the top of the chip 10, and the heat dissipation cover 401 and The top surface 20a of the package carrier 20 is connected, and the support portion 402 is fixedly connected to the heat dissipation cover 401, and is fixedly mounted on the side portion 20c of the package carrier 20. The support portion 402 extends along the side portion 20c of the package carrier 20 toward the end of the package carrier 20. The bottom extends beyond the bottom surface 20b of the package carrier 20.

In the embodiment of the present application, the opening of the heat dissipation cover 401 faces the package carrier 20, its inner surface is connected with the heat dissipation adhesive layer 70, and its edge side 40a is connected with the top surface 20a of the package carrier 20.

In the embodiment of the present application, the support portion 402 is fixedly connected to the outer surface of the heat dissipation cover 401, and is fixedly attached to the side portion 20c of the package carrier 20. The support portion 402 extends along the side portion 20c of the package carrier 20 to the side of the package carrier 20. The bottom extends beyond the bottom surface 20b of the package carrier 20.

In an embodiment, the supporting portion 402 is fixed on the PCB 30, as shown in FIG. 2, the supporting portion 402 is connected to the top surface 30a of the PCB 30.

It should be noted that the support portion 402 can be integrally formed with the heat dissipation cover 401, and the division in FIG. 2 is only an illustration, and the structural division between the support portion 402 and the heat dissipation cover 401 is not limited to the illustration in FIG. As long as the edge side 40 a of the heat dissipation cover 401 is connected to the top surface 20 a of the package carrier 20, and the support portion 402 is connected to the outer surface of the heat dissipation cover 401 and extends to the bottom of the package carrier 20. For example, in one division, the support portion 402 may include the first support portion 4021 and the second support portion 4022 as shown in FIG. 2, and in another division, the heat dissipation cover 401 may include The heat dissipation cover 401 and the first support portion 4021, the support portion 402 may include a second support portion 4022 as shown in FIG. 2.

Referring to FIG. 3, FIG. 3 is a top view of a chip packaging structure provided by an embodiment of the application, in which the same numerals represent similar layers, components or regions. The viewing angle in FIG. 3 is the direction in which the active surface of the chip in FIG. 2 faces, that is, the direction perpendicular to the plane where the upper surface of the package carrier 20 is located. Although not shown in FIG. 3, along the viewing angle direction in FIG. 3, the projection of the heat dissipation cover 401 approximately or completely coincides with the top surface 20 a of the package carrier 20. It can be seen from FIG. 3 that the projection of the supporting portion 402 in the viewing angle direction in FIG. 3 exceeds the heat dissipation cover 401, that is, the projection of the supporting portion 402 in the viewing angle direction in FIG. 3 exceeds the top surface 20 a of the package carrier 20. The specific structure of the supporting portion 402 will be described in the following embodiments, and will not be repeated here.

The following discusses how the supporting portion 402 is connected to the top surface 30a of the PCB 30 during the manufacturing process of the chip packaging structure. In one implementation, metal surface treatment can be performed on the bottom of the support portion 402 in advance, and pads can be provided, and pads can also be provided on the corresponding positions of the PCB 30, and then the support portion 402 and the top of the PCB 30 can be completed by solder paste. Connection of surface 30a.

The chip packaging structure provided by the embodiment of the present application includes: a packaging carrier 20, at least one chip 10 and a heat dissipation assembly 40. At least one chip 10 is fixed on the packaging carrier 20. The heat dissipation assembly 40 includes a heat dissipation cover 401 and a supporting portion 402, wherein, The supporting portion 402 is fixedly connected to the heat dissipation cover 401, and is fixedly attached to the side portion 20c of the package carrier 20. The supporting portion 402 extends along the side portion 20c of the package carrier 20 to the bottom of the package carrier 20 and extends beyond the bottom of the package carrier 20. The bottom surface 20b. Since the support portion 401 of the heat dissipation component 40 extends beyond the bottom surface 20b of the package carrier 20 and can be fixed on the PCB 30, the support portion 401 can bear a part of the weight of the chip package structure, and is set between the chip package structure and the PCB 30 The plurality of solder balls 90 share part of the stress, which reduces the stress borne by the plurality of solder balls 90, thereby improving the reliability of the plurality of solder balls 90.

In the actual application process, the pads on the bottom surface 10a of the chip 10 and the pads on the top surface 20a of the package carrier 20 may not be directly aligned, resulting in that the solder balls 90 cannot be simultaneously with the pads on the bottom surface 10a of the chip 10 and the package. The corresponding pads on the top surface 20a of the carrier 20 are in contact with each other, thereby making it impossible to connect the chip 10 and the package carrier 20 through solder balls. Or, in another case, the number of chips 10 is too large, the connection complexity between the chips 10 is too high, and the structure of the package carrier 20 is too complicated.

In order to solve these problems, refer to FIG. 4, which is a schematic cross-sectional view of a chip package structure provided by an embodiment of the application, in which the same number symbols represent similar layers, components or regions. Different from the embodiment shown in FIG. 2, in FIG. 4, a connecting member 50 is further provided between the top surface 20a of the package carrier 20 and the bottom surface 10a of the at least one chip 10, wherein the connecting member 50 may specifically be Redistribution layer (RDL) or interposer of the substrate.

The pads on the active surface of each chip 10 in at least one chip 10 can be connected to the redistribution layer RDL or the interposer of the substrate intermediate layer through solder balls 90, and the connection of the rewiring layer RDL or the interposer of the substrate intermediate layer can be connected through solder balls 90 It is connected to the top surface 20 a of the package carrier 20.

Among them, the interposer of the substrate intermediate layer can be an interposer made of silicon material, wherein the upper and lower sides of the interposer have wiring, and the wiring on the upper and lower sides is connected through silicon through holes. The RDL can be a multilayer metal wiring, and there is an organic insulating material (such as PI, etc.) between each layer of wiring. The interconnection between the individual chips 10 of the multiple chips 10 can be realized through the redistribution layer RDL or the substrate intermediate layer interposer, and the interconnection between at least one chip 10 and the package carrier 20 can also be realized through the redistribution layer RDL or the substrate intermediate layer interposer. Connection. In the embodiment of the present application, optionally, a primer 80 may be filled between the connecting component 50 and the packaging carrier 20.

Next, the specific structure of the heat dissipation assembly 40 is further described.

1. Regarding the support portion 402.

2, the support portion 402 may include: at least one first support portion 4021 and at least one second support portion 4022, wherein each first support portion 4021 of the at least one first support portion 4021 is fixedly connected to the heat dissipation cover 401 .

In the schematic diagram of FIG. 2, the side surface of the heat dissipation cover 401 extends along the top surface 20 a of the package carrier 20 and away from the center of the top surface 20 a to form a first support portion 4021.

In another embodiment, only a part of the side surface of the heat dissipation cover 401 may be extended. Referring to FIG. 6a, FIG. 6a is a schematic cross-sectional view of a chip packaging structure provided by an embodiment of the application. In the schematic diagram of FIG. 6a, a part of the side surface of the heat dissipation cover 401 extends along the top surface 20a of the package carrier 20 and away from the center of the top surface 20a to form the first support portion 4021. 6b, FIG. 6b is a schematic cross-sectional view of a chip packaging structure provided by an embodiment of the application. Different from FIG. 6a, the chip packaging structure in FIG. 6b further includes a connecting member 50. For a detailed description of the connecting member 50, refer to The description of the embodiment corresponding to FIG. 4 will not be repeated here.

It should be noted that although it is not shown in FIG. 2, the number of the first supporting portion 4021 may be one or more. Referring to FIG. 3, the supporting portion 402 shown in FIG. 3 is the first supporting portion 4021. At this time, The number of the first supporting portion 4021 is one, and the first supporting portion 4021 is a square ring. Referring to FIG. 5a, FIG. 5a is a top view of another chip package structure. As shown in FIG. 5a, at this time, the number of the first supporting portions 4021 is four, which are respectively arranged at the four corners of the heat dissipation cover 401. It should be noted that the first support portion 4021 shown in FIG. 3 and FIG. 5a is only an illustration, as long as it can satisfy that each first support portion 4021 of the at least one first support portion 4021 is connected to the heat dissipation cover 401, The projection of the at least one first supporting portion 4021 in the plane where the top surface 20a of the package carrier 20 is located is beyond the top surface 20a of the package carrier 20. In practice, it can be selected according to requirements, which is not limited here.

In the embodiment of the present application, each second support portion 4022 of the at least one second support portion 4022 is connected to one first support portion 4021 of the at least one first support portion 4021, and each of the at least one second support portion 4022 The second supporting portion 4022 is fixedly attached to the side portion 20c of the package carrier 20, extends along the side portion 20c of the package carrier 20 to the bottom of the package carrier 20, and exceeds the bottom surface 20b of the package carrier 20.

In an embodiment, the second supporting portion 4022 may be formed by extending the entire lower surface of the first supporting portion 4021 downward, as shown in FIG. 3. At this time, the first supporting portion 4021 and the second supporting portion 4021 The supporting portion 4022 completely overlaps in the viewing angle of FIG. 3. In another embodiment, the second supporting portion 4022 may be formed by extending a portion of the lower surface of the first supporting portion 4021 downward, as shown in FIG. 5a. At this time, the first supporting portion 4021 and the second supporting portion 4021 The two supporting parts 4022 do not completely overlap in the viewing angle of FIG. 3.

It should be noted that the number of the second support portion 4022 may be one or more, as shown in FIG. 5a. At this time, the number of the first support portion 4021 is four, which are respectively provided on the heat dissipation cover 401. Four corners, the number of the second support portions 4022 is four, and each first support portion 4021 corresponds to a second support portion 4022, that is, each first support portion extends a second support portion 4022 toward the bottom of the package carrier 20 .

In an embodiment, each first supporting portion may extend a plurality of second supporting portions 4022 toward the PCB 30. Referring to FIG. 5b, FIG. 5b is a top view of another chip package structure, in which the same numerals represent similar layers, components or regions. As shown in FIG. 5a, at this time, the number of the first support portion 4021 is one, the number of the second support portion 4022 is four, and the second support portion 4022 is respectively disposed at the four corners of the first support portion 4021.

In an embodiment, each second support portion 4022 of the at least one second support portion 4022 is fixed on the PCB 30.

It should be noted that the number and shape of the second support portions 4022 shown in FIGS. 3, 5a, and 5b are merely illustrative, as long as it satisfies each second support portion 4022 in at least one second support portion 4022. Connected to one first support portion 4021 of the at least one first support portion 4021, and each second support portion 4022 of the at least one second support portion 4022 extends toward the bottom of the package carrier 20 and exceeds the bottom surface of the package carrier 20 20b is sufficient. In practice, you can choose according to your needs, and it is not limited here.

2. Regarding the heat dissipation cover 401.

Referring to FIG. 2, the heat dissipation cover 401 shown in FIG. 2 has an inverted N-shaped ring with an opening on one side in a cross-sectional shape along a plane perpendicular to the package carrier 20. In another embodiment, referring to FIG. 7a, FIG. 7a is a schematic cross-sectional view of a chip packaging structure provided by an embodiment of the application. The heat dissipation cover 401 shown in FIG. 7a is positioned along a vertical plane with the packaging carrier 20. The cross-sectional shape of is a trapezoidal ring with one side open. Referring to Fig. 7b, Fig. 7b is a schematic cross-sectional view of a chip package structure provided by an embodiment of the application. The difference from Fig. 7a is that the chip package structure in Fig. 7b further includes a connecting member 50. For a detailed description of the connecting member 50, please refer to The description of the embodiment corresponding to FIG. 4 will not be repeated here.

FIG. 8 is a schematic cross-sectional view of a chip packaging structure. Referring to FIG. 8, the chip packaging structure includes: a reinforcing ring 111, a chip 10 and a packaging carrier 20. A lower surface 111a of the reinforcing ring 111 is connected to the top surface 20a of the package carrier 20, wherein the reinforcing ring 111 is used to reduce warpage. The bottom surface 20b of the package carrier 20 is fixed to the top surface 30a of the PCB 30 by a plurality of solder balls 90.

In the structure shown in FIG. 8, the multiple solder balls 90 bear the full weight of the chip package structure. As the chip package structure increases and the chip size increases, the stress between the chip package structure and the PCB 30 is also corresponding. The increase in size reduces the reliability of the solder ball 90, which may not meet the requirements of reliability and chip service life.

In order to solve the above technical problems, the present application provides a chip packaging structure. Referring to FIG. 9, FIG. 9 is a schematic cross-sectional view of a chip packaging structure provided by an embodiment of the application. Referring to FIG. 9, the chip packaging structure shown in FIG. 9 includes: a packaging carrier 20, at least one chip 10 and a fixing component 11.

The chip 10 is fixed on the package carrier 20. The fixing assembly 11 includes a reinforcing ring 111 and a supporting portion 112. The reinforcing ring 111 is connected to the top surface 20a of the package carrier 20, and the supporting portion 112 is fixedly connected to the reinforcing ring 111 and is fixed. Mounted on the side portion 20c of the package carrier 20, the supporting portion 112 extends along the side portion 20c of the package carrier 20 to the bottom of the package carrier 20 and exceeds the bottom surface 20b of the package carrier 20.

For the specific description of the chip 10 and the connection manner between the chip 10 and the package carrier 20, reference may be made to the description in the embodiment corresponding to FIG. 2, which will not be repeated here.

In the embodiment of the present application, it may further include a plastic encapsulation body 60. The encapsulation body 60 may wrap the sidewalls of multiple chips for fixing a plurality of chips 10. For a detailed description of the plastic encapsulation body 60, refer to the description in the corresponding embodiment in FIG. 2 , I won’t repeat it here.

Referring to FIG. 9, the chip packaging structure may further include a primer 80, which is added between the package carrier 20 and the chip 10, or between each chip of the plurality of chips 10. For the specific description of the primer 80, please refer to the description in the embodiment corresponding to FIG. 2, which will not be repeated here.

The packaging carrier 20 in the embodiment of the present application may be a packaging substrate. For the specific description of the packaging carrier 20, refer to the description in the embodiment corresponding to FIG. 2, which will not be repeated here.

9, the chip packaging structure provided by the present application includes: a fixing assembly 11, specifically, the fixing assembly 11 includes a reinforcing ring 111 and a supporting portion 112, wherein the reinforcing ring 111 is connected to the top surface 20a of the package carrier 20, and the supporting portion 112 It is fixedly connected to the reinforcing ring 111 and fixedly attached to the side portion 20c of the package carrier 20. The support portion 112 extends along the side portion 20c of the package carrier 20 to the bottom of the package carrier 20 and exceeds the bottom surface 20b of the package carrier 20 .

As shown in FIG. 9, the supporting portion 112 is fixedly connected to the outer surface of the reinforcing ring 111.

It should be noted that the support portion 112 can be integrally formed with the reinforcement ring 111, and the division in FIG. 9 is only an illustration, and the structural division between the support portion 112 and the reinforcement ring 111 is not limited to the illustration in FIG. 9. As long as the support portion 112 is connected to the outer surface of the reinforcement ring 111 and extends to the bottom of the package carrier 20 along the side portion 20c of the package carrier 20. For example, in one division, the support portion 112 may include a first support portion 1121 and a second support portion 1122 as shown in FIG. 9, and in another division, the reinforcement ring 111 may include as shown in FIG. 9 The reinforcing ring 111 and the first support portion 1121, the support portion 112 may include a second support portion 1122 as shown in FIG. 9.

Referring to FIG. 10, FIG. 10 is a top view of a chip package structure provided by an embodiment of the application, in which the same numerals represent similar layers, components or regions. The viewing angle in FIG. 10 is the direction in which the active surface of the chip in FIG. 9 faces, that is, the direction perpendicular to the plane where the upper surface of the package carrier 20 is located. Although not shown in FIG. 10, along the viewing angle direction in FIG. 10, the projection of the reinforcing ring 111 approximately or completely coincides with the top surface 20 a of the package carrier 20. It can be seen from FIG. 10 that the projection of the support portion 112 in the viewing angle direction in FIG. 10 exceeds the reinforcement ring 111, that is, the projection of the support portion 402 in the viewing angle direction in FIG. 10 exceeds the top surface 20 a of the package carrier 20. The specific structure of the supporting portion 112 will be described in the following embodiments, and will not be repeated here.

The chip packaging structure provided by the embodiment of the present application includes: a package carrier 20, at least one chip 10, and a fixing component 11, at least one chip 10 is fixed on the package carrier 20, and the fixing component 11 includes a reinforcing ring 111 and a supporting portion 112, wherein, The supporting portion 112 is fixedly connected to the reinforcing ring 111, and is fixedly attached to the side portion 20c of the package carrier 20. The supporting portion 112 extends along the side portion 20c of the package carrier 20 to the bottom of the package carrier 20 and extends beyond the bottom of the package carrier 20. The bottom surface 20b. Since the supporting portion 112 of the fixing assembly 11 extends beyond the bottom surface 20b of the packaging carrier 20 and can be connected to the PCB 30, the supporting portion 112 can bear a part of the weight of the chip packaging structure, thereby providing a lot of space between the chip packaging structure and the PCB 30. Each solder ball 90 shares a part of the stress, which reduces the stress borne by the multiple solder balls 90, thereby improving the reliability of the multiple solder balls 90.

11, FIG. 11 is a schematic cross-sectional view of a chip packaging structure provided by an embodiment of the application. In this embodiment, a connection is also provided between the top surface 20a of the package carrier 20 and the bottom surface 10a of at least one chip 10 The component 50, wherein the connecting component 50 may specifically be a redistribution layer (RDL) or a substrate intermediate layer interposer. For the specific description of the connecting component 50, refer to the description of the embodiment corresponding to FIG. 4, which will not be repeated here.

In an embodiment of the present application, the supporting portion 112 may include: at least one first supporting portion 1121 and at least one second supporting portion 1122. Each first support portion 1121 of the at least one first support portion 1121 is connected to the reinforcing ring 111; each second support portion 1122 of the at least one second support portion 1122 is connected to one of the at least one first support portion 1121 A support portion 1121 is fixedly connected and fixedly attached to the side portion 20c of the package carrier 20. The support portion 112 extends along the side portion 20c of the package carrier 20 to the bottom of the package carrier 20 and exceeds the bottom surface 20b of the package carrier 20 .

In an embodiment, each of the at least one second support portion 1122 is fixed on the PCB 30.

In an embodiment, each first support portion 1121 may extend a plurality of second support portions 1122 toward the PCB 30. 12, FIG. 12 is a top view of a chip packaging structure, as shown in FIG. 12, at this time the number of the first support portion 1121 is one, the number of the second support portion 1122 is four, and the second support portion The 1122 is respectively arranged at the four corners of the first supporting portion 1121.

For the description of the support portion 112, reference may be made to the description of the support portion 402 in the above-mentioned embodiment, which will not be repeated here.

Referring to FIG. 13, FIG. 13 is a schematic cross-sectional view of a chip packaging structure provided by an embodiment of the application. The chip packaging structure in this embodiment includes: a packaging carrier 20, at least one chip 10 and a reinforcing ring 111.

For the description of the package carrier 20 and the at least one chip 10, reference may be made to the above-mentioned embodiments, and details are not repeated here.

In the embodiment of the present application, the reinforcing ring 111 is connected to the top surface 20a of the package carrier 20, and along the first direction, the projection of the reinforcing ring 11 in the plane where the top surface 20a of the package carrier 20 is located exceeds the top surface 20a of the package carrier 20 , The first direction is perpendicular to the plane where the top surface 20a of the package carrier 20 is located.

In the embodiment of the present application, compared to the prior art where the projection of the reinforcing ring 111 on the top surface 20a of the package carrier 20 does not exceed the top surface 20a of the package carrier 20, the thickness of the reinforcing ring 111 is increased, which can reduce The package warpage of the small chip improves the package reliability.

Optionally, a rewiring layer RDL or a substrate intermediate layer interposer is also provided between the top surface 20a of the package carrier 20 and the active surface 10b of the at least one chip 10.

Optionally, the package carrier 20 is a substrate.

The present application also provides a circuit structure, including the chip packaging structure described in any one of the above embodiments and the PCB 30, wherein the supporting portion in the chip packaging structure is fixed on the PCB 30, and the packaging carrier 20 in the chip packaging structure is fixed On the PCB 30, and through the electrical connection with the PCB 30, signal transmission is realized.

As mentioned above, the above embodiments are only used to illustrate the technical solutions of the present application, not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, a person of ordinary skill in the art should understand that: The technical solutions recorded in the embodiments are modified, or some of the technical features are equivalently replaced; these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

A chip packaging structure, characterized by comprising: a packaging carrier, at least one chip and a heat dissipation component;

The at least one chip is fixed on the package carrier;

The heat dissipation assembly includes a heat dissipation cover and a supporting part, wherein:

The heat dissipation cover is snap-fitted on the top of the at least one chip, the support portion is fixedly connected to the heat dissipation cover and is fixedly mounted on the side of the package carrier, and the support portion is along the package The side portion of the carrier extends toward the bottom of the package carrier and exceeds the bottom surface of the package carrier.
The chip packaging structure of claim 1, wherein the supporting portion is fixed on a printed circuit board (PCB).
The chip packaging structure according to claim 1 or 2, wherein the packaging carrier is fixed on the PCB.
The chip packaging structure according to any one of claims 1 to 3, wherein the supporting portion comprises: at least one first supporting portion and at least one second supporting portion;

Each of the at least one first support portion is fixedly connected to the heat dissipation cover;

Each second support portion of the at least one second support portion is fixedly connected to one first support portion of the at least one first support portion, and each second support portion of the at least one second support portion The portion extends along the side of the package carrier to the bottom of the package carrier and exceeds the bottom surface of the package carrier.
4. The chip packaging structure of claim 4, wherein each of the at least one second support portion is fixed on a printed circuit board (PCB).
The chip packaging structure according to any one of claims 1 to 5, wherein a redistribution layer RDL or a substrate intermediate layer interposer is further provided between the packaging carrier and the at least one chip.
The chip packaging structure according to any one of claims 1 to 6, wherein a heat dissipation adhesive layer is further provided on the top of each chip in the at least one chip, and the heat dissipation cover is in contact with the heat dissipation adhesive layer.
The chip packaging structure according to any one of claims 1 to 7, further comprising: a plastic encapsulation body, the plastic encapsulation body is wrapped around the side wall of each chip in the at least one chip for fixing the at least one chip A chip.
The chip packaging structure according to any one of claims 1 to 8, wherein the packaging carrier is a substrate.
A chip packaging structure, which is characterized by comprising: a packaging carrier, at least one chip and a fixing component;

The at least one chip is fixed on the package carrier;

The fixing assembly includes a reinforcing ring and a supporting part, wherein the supporting part is fixedly connected to the reinforcing ring, and is fixedly attached to the side of the packaging carrier, and the supporting part is along the side of the packaging carrier. The side portion extends to the bottom of the package carrier and exceeds the bottom surface of the package carrier.
10. The chip packaging structure of claim 10, wherein the supporting portion is fixed on a printed circuit board (PCB).
The chip package structure according to claim 10 or 11, wherein the package carrier is fixed on the PCB.
The chip packaging structure according to any one of claims 10 to 12, wherein the supporting portion comprises: at least one first supporting portion and at least one second supporting portion;

Each of the at least one first support portion is fixedly connected to the reinforcement ring;

Each of the at least one second support portion is fixedly connected to one of the at least one first support portion, and is fixedly attached to the side of the package carrier, so Each of the at least one second support portion extends along the side of the package carrier to the bottom of the package carrier and exceeds the bottom surface of the package carrier.
The chip package structure according to claim 13, wherein each of the at least one second support portion is fixed on a printed circuit board (PCB).
The chip packaging structure according to any one of claims 10 to 14, wherein the packaging carrier is a substrate.
A circuit structure, characterized by comprising the chip packaging structure and PCB according to any one of claims 1 to 15, wherein the supporting part in the chip packaging structure is fixed on the PCB, and the chip packaging The package carrier in the structure is fixed on the PCB, and is electrically connected with the PCB to realize signal transmission.