KR20010048581A - Method for forming a contact hole of a semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a contact hole of a semiconductor device is provided to minimize a defect and to improve reliability, by forming the contact hole in which a partial region of the surface of the semiconductor substrate is completely etched. CONSTITUTION: A spacer(48) is formed on a gate electrode and the sidewall of the gate electrode of a semiconductor substrate(40). An interlayer dielectric(52) is formed on the semiconductor substrate by using an oxide material. The interlayer dielectric formed in a contact hole region for connecting a storage electrode of a capacitor or bit line is anisotropically dry-etched to expose a part of the spacer. The interlayer dielectric etched to a depth that a part of the spacer is exposed, is wet-etched to an end where the semiconductor substrate is exposed.

Description

Method for forming contact hole in semiconductor device {METHOD FOR FORMING A CONTACT HOLE OF A SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device in which contact holes are formed by continuously performing dry etching and wet etching.

Recent semiconductor devices have a design rule of 0.15 mu m. Accordingly, in order to satisfy the design rule, the contact hole must have an aspect ratio of 2 or more. Therefore, the width of the contact hole (CD) is reduced, and an interlayer dielectric (ILD) that forms the contact hole is formed thick.

As the process margin is more difficult to secure when forming the contact hole, a self align contact (hereinafter referred to as 'SAC') which mainly secures the spacer formed on the sidewall of the gate electrode as the process margin is mainly used. Perform.

Since the spacer is secured as a process margin, this is also referred to as a shoulder margin.

1 is a cross-sectional view of a semiconductor device in which a conventional contact hole is formed.

Referring to FIG. 1, gate electrodes 17 are formed on a semiconductor substrate 10. The gate electrodes 17 have a structure in which the polysilicon layer 12, the tungsten silicide 14, and the silicon nitride layer 16 are sequentially stacked. Spacers 18 are formed on sidewalls of the gate electrodes 17. The spacer 18 is here formed using silicon nitride.

In addition, a diffusion region 20 is formed on the surface of the semiconductor substrate 10. The diffusion region 20 is formed in the region between the gate electrodes 17.

An interlayer insulating layer 22 is formed on the semiconductor substrate 10 having the spacers 18 formed on sidewalls of the gate electrodes 17 and the gate electrodes 17. Here, the interlayer insulating layer 22 is formed to a thickness of 12,000 kPa using oxide.

A contact hole through which the surface of the semiconductor substrate 10 is partially exposed is formed by the interlayer insulating layer 22. The surface of the semiconductor substrate 10 between the gate electrodes 17 is exposed by the formation of the contact hole.

In the SAC process for forming the contact hole, an etching selectivity of the interlayer insulating layer 22 and the spacer 18 is used. As a result, the interlayer insulating layer 22 is selectively etched. That is, the interlayer insulating layer 22 is etched using the etch selectivity while the spacer 18 is secured with shoulder margin.

In the SAC process, an oxide, which is a material constituting the interlayer insulating layer 22, and silicon nitride, a material constituting the spacer 18, have an etching selectivity of about 5 to 7: 1. The SAC process is anisotropic dry etching using plasma.

However, when the interlayer insulating layer 22 is etched by the etching selectivity, the oxide of the interlayer insulating layer 22 is not etched, as shown by A of FIG. 1, and is formed on the diffusion region 20 of the semiconductor substrate 10. Partially remains.

Accordingly, in order to increase the etching selectivity, etching may be performed under the condition of a polymer plasma, but a polymer is formed on the oxide of the interlayer insulating layer 22 to prevent etching. Therefore, as described above, the oxide of the interlayer insulating layer 22 is partially etched and remains partially on the diffusion region 20 of the semiconductor substrate 10.

This acts as a cause of disturbing the electrical connection of the electrode layer (not shown) in contact with the diffusion region 20 in the semiconductor substrate 10.

Therefore, there is a problem that the reliability of the semiconductor device is lowered by the occurrence of the defects described above.

An object of the present invention is to provide a method for forming a contact hole in a semiconductor device for forming a contact hole which completely exposes a desired region.

1 is a cross-sectional view illustrating a semiconductor device in which a conventional contact hole is formed.

2 is a cross-sectional view illustrating a semiconductor device in which a contact hole is formed according to an embodiment of the present invention.

3A to 3G are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10, 40: semiconductor substrate

12, 42: polysilicon layer

14, 44: tungsten silicide

16, 46 silicon nitride layer

17, 47: gate electrode

18, 48: spacer

20, 50: diffusion region

22, 52, 52a, 52b; Interlayer insulation layer

54; Photoresist layer

54a: photoresist pattern

According to an aspect of the present invention, there is provided a method of forming a contact hole in a semiconductor device, the method including: forming an interlayer insulating layer using an oxide on a gate electrode and a semiconductor substrate with spacers formed on sidewalls of the gate electrode; Anisotropically dry etching the interlayer insulating layer formed in the contact hole region for connecting the storage electrode or the bit line to a depth at which a portion of the spacer is exposed, and using the interlayer insulating layer dry-etched to the depth. And wet etching to an end point to which the surface of the semiconductor substrate is exposed.

The interlayer insulating layer is preferably formed to a thickness of 8,000 to 22,000 Å to form a contact hole having two or more aspect ratios.

The dry etching may use an etching gas in which C _x F _y is mixed, and the wet etching may use an etching solution in which HF is mixed.

Therefore, the dry etching and the wet etching may be continuously performed to form a contact hole in which a desired region is completely exposed.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

2 is a cross-sectional view illustrating a semiconductor device in which a contact hole is formed, and FIGS. 3A to 3G are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to an embodiment of the present invention. to be.

Referring to FIG. 2, gate electrodes 47 are formed on the semiconductor substrate 40. The gate electrodes 47 have a structure in which a polysilicon layer 42, a tungsten silicide 44, and a silicon nitride layer 46 are sequentially stacked.

Spacers 48 are formed on sidewalls of the gate electrodes 47. Here, the spacer 48 is formed using silicon nitride.

A diffusion region 50, which is a source / drain region, is formed on a surface portion of the semiconductor substrate 40. The diffusion region 50 is formed in the region between the gate electrodes 47.

An interlayer insulating layer 52 is formed on the semiconductor substrate 40 on which the gate electrodes 47 and the spacers 48 are formed, and contact holes are formed to expose the diffusion region 50 of the semiconductor substrate. The interlayer insulating layer 52 is formed using an oxide.

A method of manufacturing a semiconductor device having a contact hole as described above is as follows.

Referring to FIG. 3A, gate electrodes 47 and spacers 48 are formed on the illustrated semiconductor substrate 40. A diffusion region 50 is formed in the surface portion of the semiconductor substrate 40.

The gate electrodes 47, the spacers 48, and the diffusion regions 50 are formed as follows. First, the polysilicon layer 42 is formed on the semiconductor substrate 40 by performing a chemical vapor deposition process.

Subsequently, a chemical vapor deposition process is performed to deposit tungsten on the polysilicon layer 42, and then heat treatment is performed to form the tungsten as tungsten silicide 44. Subsequently, a chemical vapor deposition process is performed to form the silicon nitride layer 46 on the tungsten silicide 44.

The gate electrodes 47 are formed on the semiconductor substrate 40 by performing a conventional photolithography process using a photoresist layer (not shown) as an etching mask.

Subsequently, ion implantation using the gate electrodes 47 as an ion implantation mask is performed to shallowly implant ions into the semiconductor substrate 40, and then heat treatment is performed.

The heat treatment is to activate ions and to compensate for lattice defects of the semiconductor substrate 40 due to the implantation of ions.

Subsequently, a chemical vapor deposition process is performed to deposit silicon nitride on the semiconductor substrate 40 on which the gate electrodes 47 are formed to form a silicon nitride layer (not shown), followed by the semiconductor substrate 40. The silicon nitride layer is etched back until the surface of is exposed. Accordingly, spacers 48 made of silicon nitride are formed on sidewalls of the gate electrodes 47.

Subsequently, ion implantation using the gate electrodes 47 having the spacers 48 formed thereon as an ion implantation mask is performed to implant ions deeply into the semiconductor substrate 40, and then heat treatment is performed.

As described above, the heat treatment is to activate the ions and to compensate for the lattice defect of the semiconductor substrate 40 due to the implantation of the ions.

Accordingly, the diffusion region 50, which is a source / drain region, is formed in the semiconductor substrate 40, and the diffusion region 50 is formed of a lightly doped drain (LDD) structure.

Referring to FIG. 3B, an interlayer insulating layer 52a is formed on the semiconductor substrate 40 on which the gate electrodes 47 and the spacers 48 are formed.

Here, the interlayer insulating layer 52a is formed with a chemical vapor deposition method to a thickness of 8,000 to 22,000 kPa, in order to satisfy the design rule of 0.15㎛.

Referring to FIG. 3C, a photoresist layer 54 is formed by applying a photoresist on the interlayer insulating layer 52a by spin-coating.

Referring to FIG. 3D, the photoresist layer 54 is formed into the photoresist pattern 54a by performing a photolithography process of alignment, exposure, and development.

Referring to FIG. 3E, an etching process using the photoresist pattern 54a as an etching mask is performed. In the etching process, the oxide of the interlayer insulating layer 52b formed in the contact hole region for connecting the storage electrode or the bit line of the capacitor is etched only to a depth where the surface of the semiconductor substrate 40 is not exposed. . The depth at which the surface of the semiconductor substrate 40 is not exposed may be limited to a point where the spacer 48 is first exposed.

At this time, the etching is anisotropic dry etching using the etching gas mixed with the C _x F _y gas. Accordingly, the etching selectivity of the oxide, which is a material constituting the interlayer insulating layer 52b, and the silicon nitride, constituting the spacer 48, is secured to about 5 to 7: 1. Thus, when performing the anisotropic dry etching, no etching by-products such as polymers are produced.

Referring to FIG. 3F, an endpoint of the surface of the semiconductor substrate 40 is exposed using the photoresist pattern 54a as an etch mask as an oxide of the anisotropic dry etched interlayer insulating layer 52. Etch until As a result, a contact hole for connecting the storage electrode or the bit line of the capacitor is formed.

At this time, the etching is a wet etching using an etchant mixed with HF.

Therefore, a contact hole for connecting the storage electrode or the bit line of the capacitor is formed by continuously performing the dry etching and the wet etching. That is, the dry etching and the wet etching are continuously performed in the SAC process for forming the contact hole.

Referring to FIG. 3G, the photoresist pattern 54a used as the etching mask is completely removed by a plasma using an oxygen group.

Therefore, a contact hole may be formed in which a portion of the surface of the semiconductor substrate 40 is completely exposed.

Here, the contact hole is formed by continuously performing dry etching and wet etching. In this case, the oxide of the interlayer insulating layer 52 may be minimized in the region where the contact hole is formed due to the low etching selectivity or the polymer. .

Accordingly, the electrode layer (not shown) and the like contacting the diffusion region 50 exposed by the formation of the contact hole are electrically connected smoothly.

This can be actively applied to the manufacture of a recent semiconductor device in which the width CD of the contact hole is reduced and the thickness of the interlayer insulating layer ILD forming the contact hole becomes thick.

Therefore, by forming a contact hole in which a part of the surface of the semiconductor substrate is completely exposed, thereby minimizing defects, the reliability of the semiconductor device is improved.

Although the present invention has been described in detail only with respect to the described embodiments, it will be apparent to those skilled in the art that various modifications and variations are possible within the technical scope of the present invention, and such modifications and modifications are within the scope of the appended claims.

Claims (3)

Forming an interlayer insulating layer using an oxide on a gate electrode and a semiconductor substrate having spacers formed on sidewalls of the gate electrode; Anisotropically dry etching the interlayer insulating layer formed in the contact hole region for connecting the storage electrode or the bit line of the capacitor to a depth at which a portion of the spacer is exposed; And And wet-etching the interlayer insulating layer etched to a depth at which a portion of the spacer is exposed to an end point to which the surface of the semiconductor substrate is exposed. The method of claim 1, wherein the interlayer insulating layer is formed to a thickness of 8,000 to 22,000 kPa. The method of claim 1, wherein the dry etching uses an etching gas containing C _× F _y , and the wet etching uses an etching solution containing HF.