KR19990001327A - Manufacturing Method of Semiconductor Device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, the method including forming an interlayer insulating layer on a semiconductor substrate on which a transistor including a gate electrode and a diffusion region is formed, and excluding a portion corresponding to the diffusion region on the interlayer insulating layer. Forming a photoresist covering the remaining portion; and forming a polymer residue on the groove and the side surface of the groove by etching the interlayer insulating layer to a predetermined depth d by using the photoresist as a mask. And forming a contact hole having a size smaller than that of the groove by etching the bottom surface of the groove of the interlayer insulating layer using the photoresist and the residue as a mask so that the diffusion region is exposed. And removing the photoresist and the residue. Therefore, since the separate etch stop layer is not formed, the process is simple and the aspect ratio of the contact hole can be reduced.

Description

Manufacturing Method of Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a self align contact hole.

As the semiconductor device is highly integrated, the cell area is reduced, so that the alignment margin during the photo process is reduced. Therefore, the contact hole for forming the storage electrode of the bit line or the capacitor is formed by the self-aligned contact method so that the gate is not exposed.

1A to 1C are process diagrams showing a method for manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1A, a transistor is formed on a P-type semiconductor substrate 11. The transistor forms a gate oxide film 13 on the semiconductor substrate 11, sequentially deposits polycrystalline silicon and silicon oxide doped with impurities on the gate oxide film 13, and then patterns the gate electrode 15 and a pattern. The cap oxide layer 17 is formed.

The sidewall oxide film 21 is formed on the side surfaces of the gate electrode 15 and the cap oxide layer 17, and the exposed portion of the semiconductor substrate 11 is formed by using the cap oxide layer 17 and the side wall oxide film 21 as a mask. N-type impurities are doped at high concentration to form a diffusion region 19 used as a source and a drain region.

Referring to FIG. 1B, silicon nitride is deposited on the semiconductor substrate 11 on which the transistor is formed by chemical vapor deposition (hereinafter, referred to as CVD) to form an etch stop layer 23. A thick silicon oxide is deposited on the etch stop layer 23 by CVD to form an interlayer insulating layer 25.

Then, the photoresist 27 is coated on the interlayer insulating layer 25, and then exposed and developed to pattern the exposed portions corresponding to the diffusion regions 19. Using the photoresist 27 as a mask, the contact hole 29 is formed by anisotropically etching the interlayer insulating layer 25 so that the etch stop layer 23 is exposed. At this time, since the etch stop layer 23 is different from the interlayer insulating layer 25 and the etching selectivity, the etch stop layer 23 prevents the cap oxide layer 17 and the sidewall oxide layer 21 from being etched and thus the size of the contact hole 29. Can be increased.

Referring to FIG. 1C, an exposed portion of the etch stop layer 23 is anisotropically etched using the photoresist 27 as a mask to complete the contact hole 29 exposing the diffusion region 19. At this time, the cap oxide layer 17 and the sidewall oxide film 21 are not etched because the etch stop layer 23 and the etching selectivity are different from each other. Therefore, the contact hole 29 is an etch stop layer because the etch stop layer 23 on the diffusion region 19 is self-aligned and removed without exposing the gate 15 by the cap oxide layer 17 and the sidewall oxide film 21. It is possible to increase the exposed surface area of (23). Then, the remaining photoresist 27 is removed.

As described above, the semiconductor device manufacturing method according to the related art prevents the cap oxide layer and the sidewall oxide layer from being etched when the interlayer insulating layer is etched by the etch stop layer formed on the semiconductor substrate to cover the cap oxide layer and the sidewall oxide layer. A large contact hole is formed, and an exposed portion of the etch stop layer is anisotropically etched to expose the diffusion region, so that the etch stop layer on the diffusion region is self-aligned and removed without exposing the gate when completing the contact hole. The surface area exposed can be increased.

However, the conventional method of manufacturing a semiconductor device has to form an etch stop layer in order to form a self-aligning contact hole, which not only complicates the process but also increases the aspect ratio of the contact hole.

Accordingly, it is an object of the present invention to provide a method for manufacturing a semiconductor device which can simplify the process and reduce the aspect ratio of the self-aligning contact hole because no separate etch stop layer is formed.

A method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises the steps of forming an interlayer insulating layer on a semiconductor substrate on which a transistor including a gate electrode and a diffusion region is formed; Forming a photoresist that covers the remaining portions except for the corresponding portions; and etching the interlayer insulating layer to a predetermined depth d by using the photoresist as a mask to form a polymer on the groove and the side of the groove. Forming a residue, and forming a contact hole having a smaller size than the groove by etching the bottom surface of the groove of the interlayer insulating layer to expose the diffusion region using the photoresist and the residue as a mask; And a step of removing the photoresist and the residue.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1A to C are process drawings showing a method of manufacturing a semiconductor device according to the prior art.

2A to C are process drawings showing a method of manufacturing a semiconductor device according to the present invention.

Explanation of symbols on the main parts of the drawings

31: semiconductor substrate 33: gate oxide film

35: gate electrode 37: cap oxide layer

39: diffusion region 41: side wall oxide film

43: interlayer insulating layer 45: photoresist

47: Hmm 49: The remains

51: contact hole

2A to 2D are process charts showing the manufacturing method of the semiconductor device according to the present invention.

Referring to FIG. 2A, a transistor including a gate 35 and a diffusion region 39 is formed on a P-type semiconductor substrate 31. The transistor forms a gate oxide film 33 on the semiconductor substrate 31, and polycrystalline silicon and silicon oxide doped with impurities on the gate oxide film 33 are referred to as chemical vapor deposition (hereinafter, referred to as CVD). The gate electrode 35 and the cap oxide layer 37 are formed by sequentially depositing and patterning the same by using a) method.

Silicon oxide is deposited on the semiconductor substrate 31 to cover the gate electrode 35 and the cap oxide layer 37 by CVD, and then etched back by a reactive ion etching (hereinafter referred to as RIE) method. A sidewall oxide film 41 is formed on the side of the electrode 35 and the cap oxide layer 37. An N type is formed on the exposed portion of the semiconductor substrate 31 by using the cap oxide layer 37 and the side wall oxide film 41 as a mask. Dopants are heavily doped to form diffusion regions 39 used as source and drain regions.

In the above, before the sidewall oxide film 41 is formed, the low concentration region used as the LDD (Lightly Doped Drain) region is formed by doping the semiconductor substrate 31 at low concentration using the cap oxide layer 37 as a mask. It may be formed.

Referring to FIG. 2B, a silicon oxide, an undoped silicate glass (USG), or a borophosphosilicate glass (BPSG) is CVD to cover the cap oxide layer 37 and the sidewall oxide layer 41 on the semiconductor substrate 31 on which the transistor is formed. Or by depositing SOG (Spin On Glass) to form an interlayer insulating layer 43 having a thickness of about 0.3 to 2 μm.

After the photoresist 45 is applied on the interlayer insulating layer 43, the photoresist 45 is exposed and developed to be patterned to expose the portion corresponding to the diffusion region 39. Using the photoresist 45 as a mask, the interlayer insulating layer 43 is anisotropically etched in one step by a predetermined depth d so as not to expose the cap oxide layer 37 and the sidewall oxide film 41 to form the grooves 47. do.

In the above, when the interlayer insulating layer 43 is anisotropically etched in one step to form the grooves 47, etching is performed using energy of about 1000 to 2500 W using an etching gas including C ₄ F ₈ . At this time, the C ₄ F ₈ gas is separated into a C ₂ F ₆ gas or C ₃ F ₈ gas and carbon (C), the separated C ₂ F ₆ gas or C ₃ F ₈ gas to the interlayer insulating layer 43 After etching, the carbon C reacts with the etched side of the interlayer insulating layer 43, that is, the side of the groove 47, to form a polymer residue 49.

Referring to FIG. 2C, the diffusion region is anisotropically etched in one step of the interlayer insulating layer 43 using the photoresist 45 and the residue 49 as a mask to form the groove 47 in two steps. The contact hole 51 exposing the 39 is formed.

In the above, an etching gas including a C ₂ F ₆ gas or a C ₃ F ₈ gas for etching the interlayer insulating layer 43 when the contact hole 51 is formed by anisotropically etching the interlayer insulating layer 43 in two steps. Etch with 1000 ~ 2500W energy using. At this time, the residue 49 formed on the side surface of the groove 47 is not removed, and only the interlayer insulating layer 43 is etched. The surface area of the diffusion region 39 which is etched and exposed in two steps is exposed to the residue 49. This becomes smaller than the size of the groove 47. Therefore, even if the size of the diffusion region 39 exposed by the contact hole 51 is smaller than the exposure limit, the contact hole 51 can be formed without exposing the gate 35.

Then, the photoresist 45 remaining on the interlayer insulating layer 43 and the residue 49 formed on the side surface of the interlayer insulating layer 43 are removed by reacting with O ₂ gas.

As described above, according to the present invention, after forming the interlayer insulating layer without forming a separate etch stop layer on the semiconductor substrate, the interlayer insulating layer corresponding to the diffusion region is formed at a predetermined depth where the cap oxide layer and the sidewall oxide film are not exposed. d) Anisotropically etch in one step using an etching gas containing C ₄ F ₈ as much as 1000 ~ 2500W to form a groove and at the same time, form a polymer residue on the side of the groove. Subsequently, the anisotropically etched portion of the interlayer insulating layer in one step is anisotropically etched in two steps to prevent the cap oxide layer and the sidewall oxide film from being removed by the residue formed on the side of the groove. Contact holes can be formed that expose diffusion regions smaller than the limit.

Therefore, the present invention does not form a separate etch stop layer, the process is simple and has the advantage of reducing the aspect ratio of the contact hole.

Claims (4)

Forming an interlayer insulating layer on the semiconductor substrate on which the transistor including the gate electrode and the diffusion region is formed; Forming a photoresist on the interlayer insulating layer, except for a portion corresponding to the diffusion region; Etching the interlayer insulating layer to a predetermined depth (d) by using the photoresist as a mask to form a polymer-like residue on the groove and the side of the groove; Forming a contact hole having a size smaller than that of the groove by etching the bottom surface of the groove of the interlayer insulating layer using the photoresist and the residue as a mask to expose the diffusion region; And removing the photoresist and the residue. The method according to claim 1, A method for manufacturing a semiconductor device, wherein the interlayer insulating layer is etched with energy of 1000 to 2500 W using an etching gas including C ₄ F ₈ . The method according to claim 1, And etching the interlayer dielectric layer with energy of about 1000 to 2500 watts using an etching gas including a C ₂ F ₆ gas or a C ₃ F ₈ gas. The method according to claim 1, 10. A method of manufacturing a semiconductor device, wherein the photoresist and the residue are removed by reacting with O ₂ gas.