KR20010046615A - Fabricating method of capacitor - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor is provided to increase the capacitance of the capacitor and achieve the simplification of process by using polysilicon of high depositing speed as the lower electrode of the capacitor. CONSTITUTION: Device for DRAM, a word line(3), a bit line(6) and a contact(8) for the lower electrode of a capacitor are formed on semiconductor substrate(1) in turns. An insulating film(9) is formed on the whole substrate. Next, by etching selectively the region on which the capacitor is to form, the contact(8) is exposed. The doped polysilicon is deposited the whole substrate to form the lower electrode of the capacitor. The insulating film(9) is exposed by etching the doped polysilicon, and the exposed insulating film(9) is removed to isolate electrically the neighboring capacitor. The rapid thermal process is performed on the doped polysilicon, so that a silicon surface-enlarging region(22) is formed. A dielectric film(13) is formed on the whole substrate, and the upper electrode of the capacitor is formed.

Description

Capacitor Manufacturing Method {FABRICATING METHOD OF CAPACITOR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor, and more particularly, to a method of manufacturing a capacitor suitable for increasing the capacitance of a capacitor applied to a semiconductor DRAM and simplifying a process.

In general, in order to increase the capacitance of a capacitor, a dielectric material having a large dielectric constant and a thin film should be formed to have a large surface area.

However, in order to increase the capacitance when the deposition thickness of the dielectric film becomes thinner than the limit value, it is recently applied to a semiconductor DRAM by applying a dielectric material having a high dielectric constant or increasing the surface area of the dielectric film.

In this case, in order to apply a dielectric material having a large dielectric constant, it is most effective to maximize the surface area of the dielectric film because the problem of modifying the entire process conventionally applied according to characteristics such as deposition and etching of the dielectric material is most effective. This can be called. If described in detail with reference to the cross-sectional view of Figures 1a to 1h attached to the conventional method for manufacturing a capacitor as follows.

First, FIG. 1A selectively selects an element (not shown) and a word line 3 applied to a DRAM on a semiconductor substrate 1 on which an isolation region 2 is formed, and an interlayer insulating film 4 and 5. The lower electrode contacts 8 of the capacitors are selectively connected to other specific areas of the device through the bit line 6 and the interlayer insulating film 7 connected to the specific areas of the device, and are generally known through well-known processes. It can be formed, and because it does not have a great meaning in the present specification it is out of the question.

As shown in FIG. 1B, an insulating film 9 is formed on the structure, and then selectively etched to expose the contact 8 in the region where the capacitor is to be formed through a photolithography process.

Then, as shown in FIG. 1C, the amorphous silicon 10 doped with the lower electrode material of the capacitor is deposited on the upper surface of the resultant in which the contact 8 is exposed.

As shown in FIG. 1D, the doped amorphous silicon 10 is selectively etched to expose the insulating film 9 formed between the contacts 8, and then the exposed insulating film 8 is removed to form an adjacent capacitor. Electrically isolate the lower electrode.

As shown in FIG. 1E, SiH ₄ gas is flowed in the high vacuum reactor on the doped amorphous silicon 10 to form the silicon nucleus 11.

As shown in FIG. 1F, the doped amorphous silicon 10 in which the silicon nucleus 11 is formed is subjected to high vacuum heat treatment to form a surface area enhanced silicon (SAES) 12. At this time, the silicon surface enlarged region 12 is formed by the migration of silicon atoms, and increases the surface area of the capacitor lower electrode, resulting in an increase in capacitance.

As shown in FIG. 1G, a silicon nitride film (Si ₃ N ₄ , 13) is formed of a dielectric material of a capacitor on the surface of the resultant product in which the silicon surface enlarged region 12 is formed.

As shown in FIG. 1H, polysilicon 14 doped with the upper electrode material of the capacitor is deposited on the resultant product on which the silicon nitride film 13 is formed to complete the manufacture of the capacitor.

However, in the conventional method of manufacturing a capacitor as described above, in order to perform a silicon surface enlargement process, amorphous silicon must be deposited on the lower electrode to allow the silicon atoms to move, and at the temperature and time of the impurity content of amorphous silicon and high vacuum heat treatment Accordingly, the surface area of the lower electrode does not grow as much as desired or excessively grows to obtain a desired capacitance, or the lower electrode of an adjacent capacitor is short-circuited.

The present invention has been made to solve the conventional problems as described above, an object of the present invention is to increase the capacitance, simplify the process, and to provide a method of manufacturing a capacitor easy to control the process.

1A to 1H are cross-sectional views showing a conventional method of manufacturing a capacitor.

Figures 2a to 2g is a cross-sectional view showing an embodiment of the present invention.

*** Explanation of symbols for main parts of drawing ***

21: Doped polysilicon 22: Silicon surface enlargement area

A method of manufacturing a capacitor for achieving the object of the present invention as described above is to sequentially form the bottom electrode contacts of the device, word line, bit line and capacitor applied to the DRAM through a general manufacturing process on the semiconductor substrate; ; Forming an insulating film on the resultant and then selectively etching an area where a capacitor is to be formed to expose the contact; Depositing doped polysilicon having fine and uniform grain into the bottom electrode material of the capacitor on the resulting exposed contact; Selectively etching the doped polysilicon to expose the insulating film, and then removing the exposed insulating film to electrically isolate adjacent capacitors; Rapidly thermally treating the doped polysilicon to form a silicon surface enlargement region; And forming a dielectric film on the surface of the resultant product on which the silicon surface enlarged region is formed, and then forming an upper electrode.

Referring to the cross-sectional view of the procedure shown in Figures 2a to 2g attached to a method for manufacturing a capacitor according to the present invention as an embodiment as follows.

First, since the process of FIGS. 2A and 2B is the same as that of FIGS. 1A and 1B, a detailed description thereof will be omitted.

Then, as shown in FIG. 2C, a doped polysilicon 21 having fine and uniform grains is deposited as the lower electrode material of the capacitor on the upper surface of the result of the contact 8 is exposed. At this time, the doped polysilicon 21 is deposited at a temperature of 550 ~ 600 ℃ to have a fine and uniform grain, and to perform a subsequent heat treatment at a temperature of 600 ~ 700 ℃ to control the fine and uniform grain Can be considered

As shown in FIG. 2D, the doped polysilicon 21 is selectively etched to expose the insulating film 9 formed between the contacts 8, and then the exposed insulating film 8 is removed to form an adjacent capacitor. Electrically isolate the lower electrode.

As shown in FIG. 2E, the doped polysilicon 21 is rapidly heat treated to form a silicon surface enlargement region 22. In this case, the rapid heat treatment is performed by the following formula (1) or formula (1) below near the grain boundry of the doped polysilicon 21 when H ₂ gas is flowed in the chamber at a temperature in the range of 300 to 500 ° C. lower than the silane decomposition temperature. A reaction product such as 2 is generated to form a silicon surface enlargement region 22 on the surface of the doped polysilicon 21.

SiH _4g ↑

Si ₂ H _4g ↑

2F, a silicon nitride film 13 is formed of a dielectric material of a capacitor on the surface of the resultant product in which the silicon surface enlarged region 22 is formed.

As shown in FIG. 2G, polysilicon 14 doped with the upper electrode material of the capacitor is deposited on the resultant product on which the silicon nitride film 13 is formed to complete the manufacture of the capacitor.

The method of manufacturing a capacitor according to the present invention as described above may omit a process of forming a separate silicon nucleus, and the reaction of Formula 1 or Formula 2 is dominant, so that a uniform reaction occurs and control of the process is easy. In addition, the surface area is larger than that of the related art, and process variables can be reduced to secure process margins, thereby increasing capacitance and contributing to process simplification, and minimizing defects in capacitors. As polysilicon having a high deposition rate is applied instead of amorphous silicon as a lower electrode, the amount of expensive reaction gas is reduced, thereby reducing costs and improving mass productivity.

Claims (4)

Sequentially forming lower electrode contacts of devices, word lines, bit lines, and capacitors applied to the DRAM through a general manufacturing process on the semiconductor substrate; Forming an insulating film on the resultant and then selectively etching an area where a capacitor is to be formed to expose the contact; Depositing doped polysilicon having fine and uniform grain as a lower electrode material of the capacitor on the resultant exposed contact; Selectively etching the doped polysilicon to expose the insulating film, and then removing the exposed insulating film to electrically isolate adjacent capacitors; Rapidly heat treating the doped polysilicon to form a silicon surface enlargement region; And forming a dielectric film on the surface of the resultant product on which the silicon surface enlarged region is formed, and then forming an upper electrode. The method of claim 1, wherein the doped polysilicon is deposited at a temperature of 550 ~ 600 ℃. The method of claim 1 or 2, further comprising the step of forming the doped polysilicon and then heat treating at a temperature of 600 ~ 700 ℃. The method of claim 1, wherein the rapid heat treatment is performed while flowing H ₂ gas in a temperature range of 300 to 500 ° C. in the chamber.