KR100217902B1 - Method of forming polysilicon layer of semiconductor device - Google Patents
Method of forming polysilicon layer of semiconductor device Download PDFInfo
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- KR100217902B1 KR100217902B1 KR1019950048745A KR19950048745A KR100217902B1 KR 100217902 B1 KR100217902 B1 KR 100217902B1 KR 1019950048745 A KR1019950048745 A KR 1019950048745A KR 19950048745 A KR19950048745 A KR 19950048745A KR 100217902 B1 KR100217902 B1 KR 100217902B1
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- Prior art keywords
- polysilicon layer
- amorphous silicon
- forming
- semiconductor device
- layer
- Prior art date
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 28
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 17
- 239000010703 silicon Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000010438 heat treatment Methods 0.000 claims description 9
- 239000007789 gas Substances 0.000 claims description 8
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 2
- 229910001882 dioxygen Inorganic materials 0.000 claims description 2
- 230000002159 abnormal effect Effects 0.000 abstract description 2
- 230000000694 effects Effects 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
본 발명은 실리콘 기판상에 형성된 비정질 실리콘층을 결정화된 폴리실리콘층으로 변화하는 반도체 소자의 폴리실리콘층을 형성하는 방법을 제공하는 것으로, 상기 비정질 실리콘층을 적은량의 O2가스 분위기에서 열처리하여 비정상적인 그레인의 성장을 억제하므로써 소자의 수율을 향상시킬 수 있는 효과가 있다.The present invention provides a method of forming a polysilicon layer of a semiconductor device that changes the amorphous silicon layer formed on the silicon substrate into a crystallized polysilicon layer, wherein the amorphous silicon layer is heat-treated in a small amount of O 2 gas atmosphere to be abnormal. There is an effect that the yield of the device can be improved by suppressing grain growth.
Description
제1(a)도 내지 제1(c)도는 종래 반도체 소자의 폴리실리콘층 형성방법을 설명하기 위한 소자의 단면도.1 (a) to 1 (c) are cross-sectional views of a device for explaining a method of forming a polysilicon layer of a conventional semiconductor device.
제2(a)도 내지 제2(c)도는 본 발명에 따른 반도체 소자의 폴리실리콘층 형성방법을 설명하기 위한 소자의 단면도.2 (a) to 2 (c) are cross-sectional views of a device for explaining a method for forming a polysilicon layer of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 및 11 : 실리콘 기판 2 및 12 : 비정질 실리콘층1 and 11: silicon substrate 2 and 12: amorphous silicon layer
2A,2B, 12B, 및 12A : 폴리실리콘층 3B : 그레인 불순물2A, 2B, 12B, and 12A: polysilicon layer 3B: grain impurity
본 발명은 반도체 소자의 폴리실리콘층 형성방법에 관한 것으로, 특히 실리콘기판상에 균일하게 결정화된 폴리실리콘층을 형성하기 위한 반도체 소자의 폴리실리콘층 형성방법에 관한 것이다.The present invention relates to a method for forming a polysilicon layer of a semiconductor device, and more particularly, to a method for forming a polysilicon layer of a semiconductor device for forming a polysilicon layer uniformly crystallized on a silicon substrate.
일반적으로 반도체 소자의 게이트 전극, 배선 및 캐패시터의 전하저장전극등에 불순물을 주입하거나 또는 불순물이 주입된 폴리실리콘을 사용하게 되는데, 현재 0.35㎛의 소자에서는 듀얼 게이트(Dual Gate) 용 전극층으로 비정질 실리콘이 사용된다.In general, polysilicon implanted with impurities or impurity is implanted into gate electrodes, wirings, and charge storage electrodes of capacitors. In the current 0.35㎛ device, amorphous silicon is used as an electrode layer for dual gates. Used.
비정질 실리콘은 증착후 결정화되지 않은 상태에서 열처리를 실시하여 결정화된 실리콘으로 변화되는데, 제1(a)도 내지 제1(c)도를 참조하여 종래의 반도체 소자의 폴리실리콘층 형성방법을 설명하면 다음과 같다.Amorphous silicon is changed to crystallized silicon by performing heat treatment in a non-crystallized state after deposition. Referring to FIGS. 1 (a) to 1 (c), a method of forming a polysilicon layer of a conventional semiconductor device will be described. As follows.
제1(a)도는 실리콘 기판(1) 상부에 비정질 실리콘층(2)을 형성한 상태의 단면도이다. 비정질 실리콘층(2)은 결정화가 이루어지지 않아 바운더리(Boundary)도 거의 형태만을 가지는 상태의 구조를 가지게 된다.FIG. 1A is a cross-sectional view of the amorphous silicon layer 2 formed on the silicon substrate 1. The amorphous silicon layer 2 does not crystallize, and thus has a structure in which a boundary has almost only a shape.
제1(b)도는 형성된 비정질 실리콘층(2)을 열처리하여 결정화된 폴리실리콘층(2A)으로 변형시킨 상태의 단면도이다. 비정질 실리콘층(2)은 열처리 공정을 거치면서 바운더리(Boundary)와 바운더리 사이에 형성된 핵에 의해서 서서히 윤곽이 형성되어 결정화된 구조로 변화되는데, 이때 결정화되는 과정에서 비정질 실리콘의 성질에 따라 비정질 실리콘은 비정상적으로 큰 그레인(Grain)(3A)이 폴리실리콘층(2A)내에서 부분적으로 발생된다.FIG. 1 (b) is a cross-sectional view of the amorphous silicon layer 2 formed as a result of being transformed into a polysilicon layer 2A crystallized by heat treatment. The amorphous silicon layer 2 is gradually contoured by a nucleus formed between the boundary and the boundary to undergo a heat treatment process to change into a crystallized structure. Abnormally large grains 3A are partially generated in the polysilicon layer 2A.
제1(c)도는 실리콘 기판(1)상의 소정 부분에 폴리실리콘층(2B)을 형성한 상태의 단면도이다. 이때 그레인(3A)은 완전히 제거되지 않고 그레인 불순물(3B)로서 실리콘 기판(1)상에 남게 된다.FIG. 1C is a cross-sectional view of a state in which the polysilicon layer 2B is formed on a predetermined portion on the silicon substrate 1. At this time, the grain 3A is not completely removed and remains on the silicon substrate 1 as the grain impurity 3B.
상기와 같은 공정으로 형성된 폴리실리콘층은 후속 공정시 그레인 불순물(3B)로 인하여 소자의 특성 및 신뢰성을 저하시키는 원인이 되고, 또한 절연 특성을 열화시키는 등의 문제점이 있다.The polysilicon layer formed by the above process causes the deterioration of the characteristics and the reliability of the device due to the grain impurities 3B in the subsequent process, and also has the problem of deteriorating the insulation characteristics.
따라서, 본 발명은 실리콘 기판상에 형성된 비정질 실리콘층을 균일하게 결정화된 폴리실리콘층으로 변화하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 폴리실리콘층 형성방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a polysilicon layer of a semiconductor device which can solve the above-mentioned disadvantages by changing the amorphous silicon layer formed on a silicon substrate into a uniformly crystallized polysilicon layer.
상술한 목적을 달성하기 위한 본 발명은 실리콘 기판상에 비정질 실리콘층을 형성하는 단계와, 상기 실리콘 기판상에 형성된 비정질 실리콘층을 산소 가스 분위기에서 열처리 공정을 실시하여 결정화시켜 폴리실리콘층을 형성하는 단계와, 상기 폴리실리콘층을 패터닝하는 단계로 이루어지는 것을 특징으로 한다.The present invention for achieving the above object is to form a polysilicon layer by forming an amorphous silicon layer on a silicon substrate, and crystallizing the amorphous silicon layer formed on the silicon substrate by performing a heat treatment process in an oxygen gas atmosphere And patterning the polysilicon layer.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2(a)도 내지 제2(c)도는 본 발명에 따른 반도체 소자의 폴리실리콘층 형성방법을 설명하기 위한 소자의 단면도이다.2 (a) to 2 (c) are cross-sectional views of a device for explaining a method of forming a polysilicon layer of a semiconductor device according to the present invention.
제2(a)도는 실리콘 기판(11) 상부에 비정질 실리콘층(12)을 형성한 상태의 단면도이다. 비정질 실리콘층(12)은 실리콘 기판(11)상에 SiH4가스를 소오스 가스로 480 내지 530℃의 온도로 증착하며, SiH4가스량은 튜브의 일측에는 50 내지 70SCCM을 공급하고, 튜브의 타측에는 130 내지 150SCCM을 공급한다.FIG. 2A is a cross-sectional view of the amorphous silicon layer 12 formed on the silicon substrate 11. The amorphous silicon layer 12 deposits SiH 4 gas on the silicon substrate 11 as a source gas at a temperature of 480 to 530 ° C., and the amount of SiH 4 gas supplies 50 to 70 SCCM to one side of the tube, and Supply 130 to 150 SCCM.
제2(b)도는 실리콘 기판(11)상에 형성된 비정질 실리콘층(12)을 적은 량의 O2가스 분위기하에서 열처리한 상태의 단면도이다.FIG. 2B is a cross-sectional view of the amorphous silicon layer 12 formed on the silicon substrate 11 in a state of being heat-treated under a small amount of O 2 gas atmosphere.
이때 비정질 실리콘층(12)을 열처리 공정으로 결정화하는 과정에서 비정질 실리콘에 압력을 가하여 비정상적인 그레인(3A)이 생기는 것을 억제하고 균일하게 결정화된 폴리실리콘층(12A)을 형성한다.At this time, in the process of crystallizing the amorphous silicon layer 12 by a heat treatment process, pressure is applied to the amorphous silicon to prevent abnormal grain 3A from occurring and uniformly crystallized polysilicon layer 12A is formed.
열처리 공정은 620 내지 650℃의 온도로 3 내지 4시간동안 실시한다. 그리고 O2가스량은 300 내지 500SCCM 정도 사용한다.The heat treatment process is carried out for 3 to 4 hours at a temperature of 620 to 650 ℃. The amount of O 2 gas is about 300 to 500 SCCM.
제2(c)도는 실리콘 기판(11)상의 소정 부분에 폴리실리콘층(12B)을 형성한 상태의 단면도이다.FIG. 2C is a cross-sectional view of a state in which the polysilicon layer 12B is formed on a predetermined portion on the silicon substrate 11.
상술한 바와 같이 본 발명에 의하면 실리콘 기판상에 형성된 비정질 실리콘층을 열처리 공정에 의해 균일하게 결정화된 폴리실리콘층으로 변화시키므로써 후속 공정시 SiO2및 폴리실리콘간의 인터페이스 특성의 향상, 마스크 작업시 디파인 불량을 방지, 식각 공정시 층의 디파인 증대 효과, 금속선의 쇼트 현상 방지 등의 탁월한 효과가 있다.As described above, according to the present invention, the amorphous silicon layer formed on the silicon substrate is changed into a polysilicon layer uniformly crystallized by a heat treatment process, thereby improving the interface characteristics between SiO 2 and polysilicon in a subsequent process, and difine during masking. There is an excellent effect of preventing defects, increasing the fineness of the layer during the etching process, and preventing short phenomenon of the metal wire.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950048745A KR100217902B1 (en) | 1995-12-12 | 1995-12-12 | Method of forming polysilicon layer of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019950048745A KR100217902B1 (en) | 1995-12-12 | 1995-12-12 | Method of forming polysilicon layer of semiconductor device |
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| Publication Number | Publication Date |
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| KR970052218A KR970052218A (en) | 1997-07-29 |
| KR100217902B1 true KR100217902B1 (en) | 1999-09-01 |
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| KR1019950048745A KR100217902B1 (en) | 1995-12-12 | 1995-12-12 | Method of forming polysilicon layer of semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2015130016A1 (en) * | 2014-02-26 | 2015-09-03 | 주식회사 유진테크 | Method for forming polysilicon film |
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| JP4655495B2 (en) * | 2004-03-31 | 2011-03-23 | 東京エレクトロン株式会社 | Deposition method |
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1995
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015130016A1 (en) * | 2014-02-26 | 2015-09-03 | 주식회사 유진테크 | Method for forming polysilicon film |
| US9741562B2 (en) | 2014-02-26 | 2017-08-22 | Eugene Technology Co., Ltd. | Method for forming polysilicon film |
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| Publication number | Publication date |
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| KR970052218A (en) | 1997-07-29 |
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