KR20010046540A - Method of forming a metal contact in a semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a metal contact in a semiconductor device is provided to achieve the simplification of processes by forming simultaneously the metal contact on the capacitor of a cell region while via hole is forming in neighboring region. CONSTITUTION: The first interlayer insulating film(116) is deposited on a semiconductor substrate(110) comprising a cell region and a neighboring region, and gate electrodes(114), bit lines(118) and buried contact plugs(120) are formed in the first interlayer insulating film(116). A capacitor is formed on the first interlayer insulating film(116), and the second interlayer insulating film(126) is deposited thereon. By etching the second interlayer insulating film(126), the first metal contact plug(128) and the first metal wiring(130) is formed to contact the bit lines(118) and the gate electrodes(114) of the neighboring region. The third interlayer insulating film(132) is deposited on the whole substrate. By etching the third interlayer insulating film(132), the second metal contact plug(134a) is formed to contact the capacitor of the cell region, and a via hole is formed to contact the metal wiring(130) of the neighboring region.

Description

METHOD OF FORMING A METAL CONTACT IN A SEMICONDUCTOR DEVICE}

The present invention relates to a method of forming a metal contact in a semiconductor device, and more particularly, to a method of forming a metal contact plug contacting a capacitor in a cell region while forming vias in a peripheral region after capacitor formation.

As the degree of integration of semiconductor devices increases, high storage capacities are required and the height of the lower electrode of the storage capacitor is increased. Accordingly, the amount of etching of the interlayer insulating film is increased when forming the metal contact, so that the metal contact formed on the capacitor of the cell region and the gate electrode and bit line of the peripheral region are formed to form a more stable metal contact when forming the metal contact. ) To form a metal contact to be formed separately. However, in terms of process simplification, forming the metal contact in the above manner is not efficient.

Therefore, a method of simultaneously forming a metal contact in the cell region and a peripheral region has been proposed, but when the interlayer insulating layer is etched for the metal contact, the capacitor is quickly exposed in the cell region having a relatively thin thickness of the interlayer insulating layer, so that the upper electrode of the capacitor is etched. Problem occurs. In order to compensate for this problem, there is a method of increasing the thickness of the upper electrode, but this causes a misalignment problem in the photographing process for the metal contact by increasing the step difference between the cell region and the peripheral region.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a metal contact in a semiconductor device in which a metal contact in a peripheral region is first formed and then a metal contact is simultaneously formed in a cell region during via formation.

1A and 1C are cross-sectional views sequentially illustrating a method of forming a metal contact according to the present invention.

* Explanation of symbols for the main parts of the drawings

110 semiconductor substrate 112 device isolation film

114: gate electrode 116: first interlayer insulating film

118: bit line 120: BC contact plug

122: lower electrode of capacitor 124: upper electrode of capacitor

126: second interlayer insulating film 128: first metal contact plug

130: first metal wiring 132: third interlayer insulating film

134a: second metal contact plug 134b: via

136: second metal wiring 138: fourth interlayer insulating film

According to the present invention for achieving the above object, a method of forming a metal contact in a semiconductor device is to deposit a first interlayer insulating film on a semiconductor substrate defined as a cell region and a peripheral region, a gate electrode, a bit in the first interlayer insulating film Lines and BC contact plugs are formed. A capacitor is formed on the first interlayer insulating film of the cell region. A second interlayer insulating film is deposited on the entire surface of the substrate. The second interlayer insulating layer is etched through a photolithography process to form a first metal contact plug and a first metal wiring to contact the bit line and the gate electrode in the peripheral region. A third interlayer insulating film is deposited on the entire surface of the substrate. The third interlayer insulating layer is etched to form a second metal contact plug in contact with the capacitor in the cell region, and a via in contact with the metal wiring in the peripheral region.

(Example)

An embodiment of the present invention will be described in detail with reference to FIGS. 1A-1C.

In the novel semiconductor device of the present invention, the metal contact forming method simultaneously forms a metal contact in the capacitor of the cell region when forming a via after forming the metal contact in the peripheral region.

1A to 1C are cross-sectional views illustrating a method for forming a metal contact in a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1A, since the device isolation layer 112 is formed in the semiconductor substrate 110 defined as the cell region C and the peripheral region P, an active region and an inactive region are defined. The gate electrode 114 is formed on the semiconductor substrate 110. A first interlayer insulating layer 116 is deposited on the entire surface of the semiconductor substrate 110. The first interlayer insulating layer 116 is formed of boron phosphorus silicate glass (BPSG) or undoped silicate glass (USG) by an Atmospheric Pressure Chemical Vapor Deposition (APCVD) method. A bit line 118, a direct contact (DC) contact plug, and a buried contact (BC) contact plug 120 are formed in the first interlayer insulating layer 116. The lower electrode 122 of the capacitor is formed on the BC contact plug 120 of the thinner cell region C. A dielectric film (not shown) and an upper electrode 124 of the capacitor are formed on the lower electrode 122 to complete the capacitor. A second interlayer insulating layer 126 is deposited on the entire surface of the substrate 110. The second interlayer insulating layer 126 is formed of BPSG by APCVD. The BPSG is reflowed in a temperature range of 800 ° C. to 900 ° C. to reduce the step difference between the cell region C and the peripheral region P. FIG.

Referring to FIG. 1B, the second and first interlayer insulating layers 126 and 116 are formed until the gate electrode 114, the bit line 118 and the active region of the peripheral region P are exposed through a photolithography process. It is etched to form a metal contact hole. Since the inner wall of the metal contact hole is deposited as a barrier metal layer and filled with a metal such as tungsten (W) and tungsten silicide, a first metal contact plug 128 is formed. The first metal wire 130 is formed on the first metal contact plug 128. A third interlayer insulating layer 132 is deposited on the entire surface of the substrate 110.

Referring to FIG. 1C, the third interlayer is exposed until the upper electrode 124 of the capacitor of the cell region C and the first metal wiring 130 of the peripheral region C are exposed through a photographic process. The insulating layer 132 is etched to simultaneously form a metal contact hole in the cell region C and a via hole in the peripheral region P. In this manner, the amount of the interlayer insulating film etched in the cell region C and the peripheral region P is similar, so that the damage of the capacitor upper electrode 124 is reduced.

In the related art, the metal contact hole of the cell region C may be formed in the edge inclined surface of the cell region C, and the depth thereof may be deeper than the via hole of the peripheral region P. FIG. However, in the present invention, as shown in FIG. 1C, since the metal contact hole is formed on the upper electrode 124 of the capacitor, the contact depth may be reduced to stably fill the metal contact. Since the metal contact hole and the inner wall of the via hole are deposited with a barrier metal film and filled with a metal such as tungsten or tungsten silicide, a second metal contact plug 134a is formed in the cell region C, and a via is formed in the peripheral region P. 134b) is formed at the same time. A second metal wire 136 is formed on the second metal contact plug 134a of the cell region C and the via 134b of the peripheral region P. A fourth interlayer insulating layer 138 is deposited on the entire surface of the substrate 110.

The present invention has the effect of simplifying the process by simultaneously forming a metal contact on the capacitor of the cell region when forming the via of the peripheral region.

In addition, since the metal contact of the cell region is formed inside the edge of the cell region, the present invention has an effect of facilitating metal film deposition.

Claims (3)

A first interlayer insulating layer 110 is deposited on the semiconductor substrate 110 defined by the cell region C and the peripheral region P. The gate electrode, the bit line, and the BC contact plug are formed in the first interlayer insulating layer 116. Forming 114, 118, 120; Forming a lower electrode (122) and an upper electrode (124) of a capacitor on the first interlayer insulating film (116) of the cell region (C); Depositing a second interlayer insulating film (126) over the substrate (110); The second metal interlayer insulating layer 126 is etched through a photolithography process so as to contact the bit line 118 and the gate electrode 118 in the peripheral region P and the first metal contact plug 128 and the metal wiring ( 130); Depositing a third interlayer insulating film (132) on the entire surface of the substrate (110); The third interlayer insulating layer 132 is etched to form a second metal contact plug 134a contacting the upper electrode 124 of the capacitor of the cell region C, and at the same time, the metal of the peripheral region P. Forming a via (134b) in contact with the wiring (130). The method of claim 1, And the second metal contact plug (134a) is located inward of the edge region of the cell region (C). The method of claim 1, And the metal contact plugs (128, 134a) and vias (134b) are formed of tungsten or tungsten silicide.