KR20010056086A - Capacitor forming method - Google Patents

Capacitor forming method Download PDF

Info

Publication number
KR20010056086A
KR20010056086A KR1019990057505A KR19990057505A KR20010056086A KR 20010056086 A KR20010056086 A KR 20010056086A KR 1019990057505 A KR1019990057505 A KR 1019990057505A KR 19990057505 A KR19990057505 A KR 19990057505A KR 20010056086 A KR20010056086 A KR 20010056086A
Authority
KR
South Korea
Prior art keywords
forming
interlayer insulating
film
insulating film
conductive layer
Prior art date
Application number
KR1019990057505A
Other languages
Korean (ko)
Inventor
남정석
Original Assignee
박종섭
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 박종섭, 주식회사 하이닉스반도체 filed Critical 박종섭
Priority to KR1019990057505A priority Critical patent/KR20010056086A/en
Publication of KR20010056086A publication Critical patent/KR20010056086A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
    • H01L21/02326—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen into a nitride layer, e.g. changing SiN to SiON
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors

Abstract

PURPOSE: A method for forming a capacitor is provided to form an excellent dielectric layer by preventing the generation of a native oxide layer through forming a nitride layer and an oxide layer in same chamber. CONSTITUTION: The first to the fourth gates(23A-23D) are formed on a semiconductor substrate(21). The first interlayer dielectric(24) is formed on a whole face of the structure. The first to the third plugs(25A-25C) are formed by etching the first interlayer dielectric(24) and filling a conductive material thereon. The second interlayer dielectric(26) is formed thereon. A bit line(27) is formed by etching the interlayer dielectric of the second plug(25B) and depositing and patterning the conductive material. The third and the fourth interlayer dielectrics(28,29) are formed thereon. The second, the third, and the fourth interlayer dielectrics(26,28,29) of the first and the third plugs(25A,25C) are etched. The first conductive layer(30) is formed thereon. The second conductive layer(31) is formed thereon. A nitride layer(32) is deposited on the second conductive layer(31) and the fourth interlayer dielectric(29). A dielectric layer is formed by forming an oxide layer(33) on the nitride layer(32). A poly electrode(34) is formed on a whole face of the oxide layer(33).

Description

커패시터 형성방법{CAPACITOR FORMING METHOD}Capacitor Formation Method {CAPACITOR FORMING METHOD}

본 발명은 커패시터 형성방법에 관한 것으로, 특히 디램(Dynamic Ramdom Access Momory;DRAM)의 고집적화에 따른 고용량 커패시터를 형성하기위하여 질화막 및 산화막으로 구성된 NO막을 유전막으로 이용할 경우 발생하는 자연산화막을 방지하여 양질의 유전막을 확보하기에 적당하도록 한 커패시터 형성방법에 관한 것이다.The present invention relates to a method for forming a capacitor, and in particular, to form a high capacity capacitor according to high integration of a DRAM (Dynamic Ramdom Access Momory (DRAM)) to prevent a natural oxide film generated by using a NO film composed of a nitride film and an oxide film as a dielectric film, The present invention relates to a capacitor forming method suitable for securing a dielectric film.

종래 커패시터 형성방법의 일실시예를 도 1a 내지 도 1d의 수순단면도를 참고하여 설명하면 다음과 같다.An embodiment of the conventional capacitor forming method will be described below with reference to the procedure cross-sectional view of FIGS. 1A to 1D.

먼저, 도 1a에 도시한 바와 같이 반도체기판(1)상에 트랜치(2)를 형성하여 액티브영역을 정의하고, 반도체기판(1) 및 트랜치(2)의 상부에 일정한 거리로 이격되는 게이트(3A~3D)를 형성한다.First, as shown in FIG. 1A, a trench 2 is formed on the semiconductor substrate 1 to define an active region, and the gate 3A is spaced at a predetermined distance from the upper portion of the semiconductor substrate 1 and the trench 2. ˜3D).

그리고, 상기 게이트(3A~3D)가 형성된 구조물 상에 층간절연막(4)을 형성하고, 액티브영역과 트랜치(2)상의 게이트(3A~3D)간 이격영역을 식각하여 컨택홀을 형성한 후, 도전성물질을 채워 플러그(5A~5C)를 형성한다.After forming the interlayer insulating film 4 on the structure where the gates 3A to 3D are formed, and forming a contact hole by etching a spaced area between the active region and the gates 3A to 3D on the trench 2, The conductive material is filled to form plugs 5A to 5C.

그리고, 상기 플러그(5A~5C)가 형성된 구조물 상에 층간절연막(6)을 형성하고, 상기 형성된 플러그(5B)의 일부가 드러나도록 컨택홀을 형성한 후 그 상부에 배선물질을 증착하고 이를 패터닝하여 비트라인(7)을 형성한다.In addition, an interlayer insulating film 6 is formed on the structure where the plugs 5A to 5C are formed, a contact hole is formed to expose a part of the formed plug 5B, and a wiring material is deposited thereon and patterned thereon. The bit line 7 is formed.

그리고, 상기 비트라인(7)이 형성된 구조물 상에 층간절연막(8,9)을 형성하고, 상기 플러그(5A,5C)가 형성된 영역을 식각하여 컨택홀을 형성한 다음 컨택홀을 도전성 물질로 채워 제 1도전체층(10)을 형성한다.Then, the interlayer insulating films 8 and 9 are formed on the structure where the bit line 7 is formed, and the contact holes are formed by etching the regions where the plugs 5A and 5C are formed, and then filling the contact holes with a conductive material. The first conductive layer 10 is formed.

그리고, 상기 제 1도전체층(10) 및 층간절연막(9)상부에 제 2도전체층(11)을 높이 형성하고 이를 커패시터 하부전극을 형성하도록 식각한다.Then, the second conductive layer 11 is formed high on the first conductive layer 10 and the interlayer insulating film 9 and etched to form a capacitor lower electrode.

상기 제 2도전체층(11)은 도핑된 폴리실리콘으로 형성하며 그 형상은 원통기둥 형태가 된다.The second conductive layer 11 is formed of doped polysilicon and its shape is cylindrical.

그 다음, 도 1b에 도시한 바와 같이 상기 형성한 제 2도전체층(11) 및 층간절연막(9)상부에 질화막(12)을 증착한다.Next, as shown in FIG. 1B, a nitride film 12 is deposited on the second conductive layer 11 and the interlayer insulating film 9 formed above.

그 다음, 도 1c에 도시한 바와 같이 상기 형성한 웨이퍼를 다음공정을 진행하기위해 다른 챔버로 옮기는 동안 상기 질화막(12)의 상부에 자연산화막(13)이 형성되고, 그 상부에 습식산화로 산화막(14)을 형성하여 NO막으로 이루어진 유전막을 형성한다.Then, as shown in FIG. 1C, a natural oxide film 13 is formed on top of the nitride film 12 while the formed wafer is transferred to another chamber to proceed to the next process. (14) is formed to form a dielectric film made of an NO film.

이때, 상기와 같이 질화막(12)이 형성된 이후에 다음공정을 위해 웨이퍼를 다른 챔버로 옮기는 지연시간 동안 그 상부에는 자연발생적으로 산화막이 생기는데 이를 자연산화막(13)이라 하고, 유전막의 유전율을 떨어뜨리는 요인이 된다.At this time, after the nitride film 12 is formed as described above, an oxide film is naturally generated on the upper side during the delay time of transferring the wafer to another chamber, which is called a natural oxide film 13, and the dielectric constant of the dielectric film is reduced. It becomes a factor.

그 다음. 도 1d에 도시한 바와 같이 상기 형성한 산화막(14)의 상부전면에 폴리실리콘으로 이루어진 폴리전극(15)을 형성한다.next. As shown in FIG. 1D, a polyelectrode 15 made of polysilicon is formed on the upper surface of the formed oxide film 14.

이때, 상기 폴리전극(15)은 커패시터 상부전극 역할을 한다.In this case, the polyelectrode 15 serves as a capacitor upper electrode.

상기한 바와 같은 종래 커패시터 형성방법은 NO유전막을 형성하기 위해서 질화막을 증착한 다음 공정장소를 옮겨서 습식 산화막을 형성하므로 공정시간이 오래 걸리며, 상기 질화막 증착 후 지연시간이 있을경우 자연산화막이 생겨 유전막의 질을 떨어뜨리는 문제점이 있었다.The conventional capacitor forming method as described above takes a long process time because a wet oxide film is formed by depositing a nitride film to form a NO dielectric film and then moving the process location, and a natural oxide film is formed when there is a delay time after depositing the nitride film. There was a problem that degraded the quality.

본 발명은 상기한 바와 같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 동일한 챔버에서 질화막과 산화막을 형성하도록하여 생산성을 향상시키면서 양질의 유전막을 확보할 수 있는 커패시터 형성방법을 제공하는데 있다.The present invention has been made to solve the conventional problems as described above, an object of the present invention is to form a nitride film and an oxide film in the same chamber to provide a capacitor formation method that can ensure a high-quality dielectric film while improving productivity. It is.

도 1은 종래 커패시터 형성방법을 보인 수순단면도.1 is a cross-sectional view showing a conventional capacitor forming method.

도 2은 본 발명의 수순단면도.2 is a cross-sectional view of the procedure of the present invention.

*** 도면의 주요부분에 대한 부호의 설명 ****** Explanation of symbols for main parts of drawing ***

21 : 반도체기판 22 : 트랜치21: semiconductor substrate 22: trench

23A~23D : 게이트 24,26,28,29 : 층간절연막23A ~ 23D: Gate 24,26,28,29: Interlayer Insulation

25A~25C : 플러그 27 : 비트라인25A ~ 25C: Plug 27: Bitline

30 : 제 1도전체층 31 : 제 2도전체층30: first conductive layer 31: second conductive layer

32 : 질화막 33 : 산화막32: nitride film 33: oxide film

34 : 폴리전극34: polyelectrode

상기한 바와같은 본 발명의 목적을 달성하기 위한 커패시터 형성방법은 트랜치가 형성된 반도체기판 상에 일정한 거리로 이격되는 제 1~제 4게이트를 형성한 후, 상부전면에 제 1층간절연막을 형성하는 공정과; 상기 제 1~제 4게이트간 이격영역의 제 1층간절연막을 식각하고, 도전성물질을 채워 제 1~제 3플러그를 형성한 다음 상부전면에 제 2층간절연막을 형성하는 공정과; 상기 제 2플러그가 형성된 영역의 제 2층간절연막을 식각하고, 그 상부에 도전성물질을 증착하고 패터닝하여 비트라인을 형성한 다음 상부전면에 차례로 제 3층간절연막, 제 4층간절연막을 형성하는 공정과; 상기 제 1,제 3플러그가 형성된 영역의 제 2,제 3,제 4층간절연막을 식각하고, 제 1도전체층을 채워넣은 다음 그 상부전면에 제 2도전체층을 높이 형성하고 이를 커패시터 하부전극을 형성하도록 식각하는 공정과; 상기 형성한 제 2도전체층 및 제 4층간절연막 상부에 질화막을 증착하는 공정과; 상기 형성한 질화막의 상부에 산화막을 형성하여 NO막으로 이루어진 유전막을 형성하는 공정과; 상기 형성한 산화막의 상부전면에 폴리실리콘으로 이루어진 폴리전극을 형성하는 공정으로 이루어지는 것을 특징으로한다.A capacitor forming method for achieving the object of the present invention as described above is a step of forming a first interlayer insulating film on the upper surface after forming the first to fourth gates spaced at a predetermined distance on the semiconductor substrate formed with a trench and; Etching the first interlayer insulating film in the spaced area between the first and fourth gates, filling the conductive material to form the first to third plugs, and then forming a second interlayer insulating film on an upper surface of the first interlayer insulating film; Etching the second interlayer insulating film in the region where the second plug is formed, forming a bit line by depositing and patterning a conductive material thereon, and forming a third interlayer insulating film and a fourth interlayer insulating film on the upper surface in turn; ; Etch the second, third, and fourth interlayer insulating films in the region where the first and third plugs are formed, fill the first conductive layer, and then form a second conductive layer high on the upper surface of the capacitor to form the lower electrode of the capacitor. Etching to form; Depositing a nitride film on the formed second conductive layer and the fourth interlayer insulating film; Forming an oxide film made of an NO film by forming an oxide film on the formed nitride film; And forming a polyelectrode made of polysilicon on the upper surface of the formed oxide film.

상기한 바와 같은 본 발명에의한 커패시터 형성방법을 도 2a 내지 도 2d에 도시한 수순단면도를 일 실시예로하여 상세히 설명하면 다음과 같다.The method of forming a capacitor according to the present invention as described above will be described in detail with reference to a procedure cross-sectional view shown in FIGS. 2A to 2D as an embodiment.

먼저, 도 2a에 도시한 바와같이 반도체기판(21)상에 트랜치(22)를 형성하여 액티브영역을 정의하고, 반도체기판(21) 및 트랜치(22)의 상부에 일정한 거리로 이격되는 게이트(23A~23D)를 형성한다.First, as shown in FIG. 2A, a trench 22 is formed on the semiconductor substrate 21 to define an active region, and the gate 23A is spaced at a predetermined distance from the upper portion of the semiconductor substrate 21 and the trench 22. ˜23D).

그리고, 상기 게이트(23A~23D)가 형성된 구조물 상에 층간절연막(24)을 형성하고, 액티브영역과 트랜치(22)상의 게이트(23A~23D)간 이격영역을 식각하여 컨택홀을 형성한 후, 도전성물질을 채워 플러그(25A~25C)를 형성한다.After the interlayer insulating film 24 is formed on the structure on which the gates 23A to 23D are formed, a contact hole is formed by etching the spaced area between the active region and the gates 23A to 23D on the trench 22. The conductive material is filled to form plugs 25A to 25C.

그리고, 상기 플러그(25A~25C)가 형성된 구조물 상에 층간절연막(26)을 형성하고, 상기 형성된 플러그(25B)의 일부가 드러나도록 컨택홀을 형성한 후 그 상부에 배선물질을 증착하고 이를 패터닝하여 비트라인(27)을 형성한다.In addition, an interlayer insulating layer 26 is formed on the structure in which the plugs 25A to 25C are formed, a contact hole is formed to expose a part of the formed plug 25B, and a wiring material is deposited thereon and patterned thereon. The bit line 27 is formed.

그리고, 상기 비트라인(27)이 형성된 구조물 상에 층간절연막(28,29)을 형성하고, 상기 플러그(25A,25C)가 형성된 영역을 식각하여 컨택홀을 형성한 다음 컨택홀이 채워지도록 제 1도전체층(30)을 형성한다.In addition, interlayer insulating layers 28 and 29 are formed on the structure where the bit line 27 is formed, and the contact holes are formed by etching the regions where the plugs 25A and 25C are formed, and then filling the contact holes. The conductor layer 30 is formed.

그리고, 상기 제 1도전체층(30) 및 층간절연막(29)상부에 제 2도전체층(31)을 높이 형성하고 이를 커패시터 하부전극을 형성하도록 식각한다.Then, the second conductive layer 31 is formed high on the first conductive layer 30 and the interlayer insulating layer 29 and etched to form a capacitor lower electrode.

상기 제 2도전체층(31)은 도핑된 폴리실리콘으로 형성하며 그 형상은 원통기둥 형태가 되고, 상기 제 1도전체층(31)과 각각 연결한다..The second conductive layer 31 is formed of doped polysilicon and has a cylindrical shape, and connects with the first conductive layer 31, respectively.

그 다음, 도 2b에 도시한 바와 같이 상기 형성한 제 2도전체층(31) 및 층간절연막(29)상부에 질화막(32)을 증착한다.Next, as illustrated in FIG. 2B, a nitride film 32 is deposited on the formed second conductive layer 31 and the interlayer insulating film 29.

이때, 상기 질화막(32)을 형성하기위해서 NH3가스를 챔버로 흘린다.At this time, NH 3 gas is flowed into the chamber to form the nitride film 32.

그 다음, 도 2c에 도시한 바와 같이 상기 형성한 질화막(32)의 상부에 산화막(33)을 형성하여 NO막으로 이루어진 유전막을 형성한다.Next, as shown in FIG. 2C, an oxide film 33 is formed on the formed nitride film 32 to form a dielectric film made of an NO film.

이때, 상기 산화막(33)을 형성하기 위해서 H2+O2분위기에서 상기 질화막(32)상부를 산화시킨다.At this time, the upper portion of the nitride film 32 is oxidized in an H 2 + O 2 atmosphere to form the oxide film 33.

그 다음. 도 2d에 도시한 바와 같이 상기 형성한 산화막(33)의 상부전면에 폴리실리콘으로 이루어진 폴리전극(34)을 형성한다.next. As shown in FIG. 2D, a polyelectrode 34 made of polysilicon is formed on the upper surface of the formed oxide film 33.

이때, 상기 폴리전극(34)은 커패시터 상부전극 역할을 한다.In this case, the polyelectrode 34 serves as a capacitor upper electrode.

상기 공정이 진행되는 챔버는 급속열처리공정(Rapid Thermal Processing:RTP)에서 사용하는 챔버를 사용하는데, 급속열처리공정에서 상기 질화막(32) 또는 산화막(33)을 형성하는 데는 수~수십초에 완성이 되므로 종래 일반챔버에서 30분이상 걸리던 공정시간을 단축할 수 있으며, 급속열처리공정에 사용되는 챔버는 그 내부에 여러개의 보트를 가진것이 사용되므로 상기와 같이 질화막(32), 산화막(33)을 형성할 경우 보트만 바꾸면 단일 챔버에서 형성할 수 있다.The chamber in which the process proceeds uses a chamber used in a rapid thermal processing (RTP) process, which is completed in several to several tens of seconds to form the nitride film 32 or the oxide film 33 in the rapid thermal processing process. Therefore, it is possible to shorten the process time that took 30 minutes or more in the conventional general chamber, and since the chamber used for the rapid heat treatment process has several boats therein, the nitride film 32 and the oxide film 33 are formed as described above. In this case, the boat can be changed in a single chamber.

상기한 바와 같은 본 발명 커패시터 형성방법은 급속열처리공정 챔버에서NH3가스를 이용하여 질화막을 형성하고, 챔버를 옮기지 않고 곧바로 H2+O2분위기로 전환하여 산화막을 형성하도록함과 아울러 급속열처리공정을 사용하므로 공정시간이 단축되어 생산성을 향상시키면서 자연산화막의 발생을 방지할 수 있어 양질의 유전막을 확보할 수 있는 효과가 있다.The capacitor forming method of the present invention as described above forms a nitride film using NH 3 gas in a rapid heat treatment process chamber, and immediately converts into an H 2 + O 2 atmosphere to form an oxide film without moving the chamber. Since the process time is shortened, it is possible to prevent the occurrence of the natural oxide film while improving the productivity, thereby securing a good dielectric film.

Claims (3)

트랜치가 형성된 반도체기판 상에 일정한 거리로 이격되는 제 1~제 4게이트를 형성한 후, 상부전면에 제 1층간절연막을 형성하는 공정과; 상기 제 1~제 4게이트간 이격영역의 제 1층간절연막을 식각하고, 도전성물질을 채워 제 1~제 3플러그를 형성한 다음 상부전면에 제 2층간절연막을 형성하는 공정과; 상기 제 2플러그가 형성된 영역의 제 2층간절연막을 식각하고, 그 상부에 도전성물질을 증착하고 패터닝하여 비트라인을 형성한 다음 상부전면에 차례로 제 3층간절연막, 제 4층간절연막을 형성하는 공정과; 상기 제 1,제 3플러그가 형성된 영역의 제 2,제 3,제 4층간절연막을 식각하고, 제 1도전체층을 채워넣은 다음 상부전면에 제 2도전체층을 높이 형성하고 이를 커패시터 하부전극을 형성하도록 식각하는 공정과; 상기 형성한 제 2도전체층 및 제 4층간절연막 상부에 질화막을 증착하는 공정과; 상기 형성한 질화막의 상부에 산화막을 형성하여 NO막으로 이루어진 유전막을 형성하는 공정과; 상기 형성한 산화막의 상부전면에 폴리실리콘으로 이루어진 폴리전극을 형성하는 공정으로 이루어지는 것을 특징으로하는 커패시터 형성방법.Forming first to fourth gates spaced apart by a predetermined distance on the semiconductor substrate where the trench is formed, and then forming a first interlayer insulating film on the upper surface of the semiconductor substrate; Etching the first interlayer insulating film in the spaced area between the first and fourth gates, filling the conductive material to form the first to third plugs, and then forming a second interlayer insulating film on an upper surface of the first interlayer insulating film; Etching the second interlayer insulating film in the region where the second plug is formed, forming a bit line by depositing and patterning a conductive material thereon, and forming a third interlayer insulating film and a fourth interlayer insulating film on the upper surface in turn; ; Etch the second, third and fourth interlayer insulating films in the region where the first and third plugs are formed, fill the first conductive layer, and then form a second conductive layer high on the upper surface thereof to form a capacitor lower electrode. Etching to etch; Depositing a nitride film on the formed second conductive layer and the fourth interlayer insulating film; Forming an oxide film made of an NO film by forming an oxide film on the formed nitride film; And forming a polyelectrode made of polysilicon on the upper surface of the formed oxide film. 제 1항에 있어서, 상기 NO유전막을 형성하는 공정은 하나의 챔버에서 NH3가스를 이용하여 질화막을 형성하고, 챔버를 옮기지 않고 곧바로 H2+O2분위기로 전환하여 산화막을 형성하는 것을 특징으로하는 커패시터 형성방법.The method of claim 1, wherein the forming of the NO dielectric film comprises forming a nitride film using NH 3 gas in one chamber, and immediately switching to an H 2 + O 2 atmosphere to form an oxide film without moving the chamber. Capacitor formation method. 제 1항에 있어서, 상기 챔버는 급속열처리공정에서 사용하는, 다수의 보트를 가진 챔버를 이용하여 진행하는 것을 특징으로하는 커패시터 형성방법.The method of claim 1, wherein the chamber proceeds by using a chamber having a plurality of boats used in a rapid heat treatment process.
KR1019990057505A 1999-12-14 1999-12-14 Capacitor forming method KR20010056086A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019990057505A KR20010056086A (en) 1999-12-14 1999-12-14 Capacitor forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019990057505A KR20010056086A (en) 1999-12-14 1999-12-14 Capacitor forming method

Publications (1)

Publication Number Publication Date
KR20010056086A true KR20010056086A (en) 2001-07-04

Family

ID=19625688

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019990057505A KR20010056086A (en) 1999-12-14 1999-12-14 Capacitor forming method

Country Status (1)

Country Link
KR (1) KR20010056086A (en)

Similar Documents

Publication Publication Date Title
KR100726145B1 (en) Method for fabricating semiconductor device
JP2004193563A (en) Semiconductor device having mim capacitor
US6656833B2 (en) Method of DRAM
KR100507862B1 (en) Method for fabricating semiconductor device
KR20010056086A (en) Capacitor forming method
KR100487915B1 (en) Capacitor Formation Method of Semiconductor Device
US6541358B2 (en) Method of fabricating a semiconductor device by filling gaps between gate electrodes with HSQ
KR100515441B1 (en) Method for fabricating an integrated circuit
KR20070060352A (en) Method of manufacturing semiconductor device
KR100753031B1 (en) Method of forming contact hole in semiconductor device
KR20060104033A (en) Semiconductor device with recessed active region and method for manufacturing the same
KR100310823B1 (en) Contact hole formation method of semiconductor device
KR100253326B1 (en) Method for semiconductor device
KR20010004929A (en) Method of forming polysilicon plug for semiconductor device
KR100307967B1 (en) Mehtod of forming IPO layer of MML device
KR20030002749A (en) Method of manufacturing a semiconductor device
KR20020045190A (en) Method for Fabricating Semiconductor Device
KR20040008482A (en) A method for forming a semiconductor device
KR20050116665A (en) Method for fabricating semiconductor device
KR20010004726A (en) Method of forming a semiconductor device
KR20040083810A (en) Method for forming bitline contact of semiconductor device
KR20020002924A (en) Method for manufacturing memory device
KR20010036328A (en) Method for forming node contact of memory cell
KR20030043138A (en) Semiconductor device and Method for fabricating the same
KR20060075039A (en) Method for forming landing plug in semiconductor device

Legal Events

Date Code Title Description
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid