KR20010018840A - Apparatus for baking wafer of semiconductor track system - Google Patents
Apparatus for baking wafer of semiconductor track system Download PDFInfo
- Publication number
- KR20010018840A KR20010018840A KR1019990034955A KR19990034955A KR20010018840A KR 20010018840 A KR20010018840 A KR 20010018840A KR 1019990034955 A KR1019990034955 A KR 1019990034955A KR 19990034955 A KR19990034955 A KR 19990034955A KR 20010018840 A KR20010018840 A KR 20010018840A
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- wafer
- baking
- pins
- semiconductor track
- semiconductor
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6838—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping with gripping and holding devices using a vacuum; Bernoulli devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68742—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a lifting arrangement, e.g. lift pins
Abstract
Description
본 발명은 반도체 트랙장비용 베이크 장치에 관한 것으로, 특히 플레이트의 상면에 웨이퍼의 안착시 미끄러져서 공정불량을 유발하는 것을 방지하도록 하는데 적합한 반도체 트랙장비용 베이크 장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a baking apparatus for semiconductor track equipment, and more particularly, to a baking apparatus for semiconductor track equipment, which is adapted to prevent slipping during mounting of a wafer on an upper surface of a plate to cause a process defect.
반도체 제조공정중 트랙공정에서는 코팅작업을 마친 웨이퍼를 로봇 암을 이용하여 베이크 장치로 이송하여 베이크를 실시하게 되는데, 이와 같이 웨이퍼의 베이크를 실시하는 베이크 장치의 구조가 도 1에 도시되어 있는 바, 이를 간단히 설명하면 다음과 같다.In the track process of the semiconductor manufacturing process, the coated wafer is transferred to a baking apparatus using a robot arm to bake. The structure of the baking apparatus for baking the wafer is illustrated in FIG. 1. This is briefly described as follows.
도 1과 도 2에 도시된 바와 같이, 종래 트랙장비의 베이크 장치는 원판형의 몸체(1) 중앙에 상,하방향으로 승강가능하도록 3개의 승강핀(2)이 설치되어 있고, 상면 가장자리에는 웨이퍼(W)가 얹혀지는 5개의 가이드 블럭(3)들이 고정되어 있으며, 그 가이드 블럭(3)의 상면에는 각각 웨이퍼(W)의 측면을 지지하기 위한 지지핀(4)이 고정설치되어 있다.As shown in Figures 1 and 2, the baking device of the conventional track equipment is provided with three lifting pins (2) are provided in the center of the disc-shaped body (1) to be able to lift in the up and down direction, the upper edge Five guide blocks 3 on which the wafers W are mounted are fixed, and support pins 4 for supporting the side surfaces of the wafers W are fixed to the upper surfaces of the guide blocks 3, respectively.
상기와 같이 구성되어 있는 종래 트랙장비의 베이크장치는 도 3a와 같이 승강핀(2)이 상측으로 완전히 상승한 상태에서 이송암이 웨이퍼(W)를 이송하여 승강핀(2)들의 상면에 얹어 놓는다.In the baking apparatus of the conventional track equipment configured as described above, the transfer arm transfers the wafer W in a state in which the lifting pin 2 is completely raised upward, as shown in FIG. 3A, and places it on the upper surfaces of the lifting pins 2.
그런 상태에서, 상기 승강핀(2)을 하강시켜서 도 3b와 같이 웨이퍼(W)가 가이드 블럭(3)의 상면에 얹혀짐과 동시에 지지핀(4)들의 측면에 지지되도록 한 상태에서 웨이퍼(W)의 베이크작업이 진행된다.In such a state, the lifting pin 2 is lowered so that the wafer W is mounted on the upper surface of the guide block 3 and simultaneously supported on the side surfaces of the support pins 4 as shown in FIG. 3B. ) Baking is in progress.
그러나, 상기와 같은 종래 반도체 트랙장비의 베이크 장치는 승강핀(2)들의 상면에 웨이퍼(W)가 얹혀진 상태에서 이동시에 웨이퍼(W)가 미끄러져서 가이드 블럭(3)의 상면에 정확히 안착되지 못하는 경우가 종종 발생되고, 이와 같은 상태에서 베이크 작업이 진행되어 불균일한 베이크작업에 의한 품질불량을 초래하는 문제점이 있었다.However, the baking apparatus of the conventional semiconductor track equipment as described above does not accurately seat the upper surface of the guide block 3 due to the sliding of the wafer W during movement while the wafer W is placed on the upper surfaces of the lifting pins 2. Occasionally occurs, there is a problem that the bake operation in this state, resulting in poor quality due to non-uniform bake operation.
상기와 같은 문제점을 감안하여 안출한 본 발명의 목적은 베이크 플레이트의 상면에 웨이퍼를 정확히 안착시켜서 베이크작업에 의한 품질불량이 발생되는 것을 방지하도록 하는데 적합한 반도체 트랙장비의 베이크 장치를 제공함에 있다.SUMMARY OF THE INVENTION An object of the present invention devised in view of the above problems is to provide a baking apparatus of a semiconductor track equipment suitable for accurately placing a wafer on an upper surface of a baking plate to prevent quality defects caused by baking.
도 1은 종래 베이크 장치의 구조를 보인 평면도.1 is a plan view showing the structure of a conventional baking apparatus.
도 2는 도 1의 A-A'를 절취하여 보인 단면도.2 is a cross-sectional view taken along the line AA ′ of FIG. 1;
도 3a,3b는 종래의 베이크 장치에서 웨이퍼를 안착하는 순서를 보인 단면도.3A and 3B are cross-sectional views illustrating a procedure of seating a wafer in a conventional baking apparatus.
도 4는 본 발명 반도체 트랙장비용 베이크 장치의 구조를 보인 사시도.Figure 4 is a perspective view showing the structure of the baking device for a semiconductor track equipment of the present invention.
도 5는 본 발명 반도체 트랙장비의 베이크 장치의 정면도.5 is a front view of the baking apparatus of the present invention semiconductor track equipment.
도 6a, 6b는 본 발명에서 웨이퍼가 안착되는 순서를 보인 정면도.Figure 6a, 6b is a front view showing the order in which the wafer is seated in the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
11 : 베이크 플레이트 12 : 승강핀11: bake plate 12: lifting pin
12a,13a : 버큠홀 13 : 고정핀12a, 13a: Burr Hole 13: Fixing Pin
W : 웨이퍼W: Wafer
상기와 같은 본 발명의 목적을 달성하기 위하여 웨이퍼를 가열하기 위한 베이크 플레이트와, 그 베이크 플레이트에 승강가능하도록 삽입설치되어 있으며 상면에 버큠홀이 구비되어 있는 수개의 승강핀과, 그 승강핀들의 주변에 고정설치됨과 아울러 상면에 버큠홀이 각각 구비되어 있는 수개의 고정핀을 구비하여서 구성되는 것을 특징으로 하는 반도체 트랙장비의 베이크 장치가 제공된다.In order to achieve the above object of the present invention, a baking plate for heating a wafer, a plurality of lifting pins inserted into the baking plate so as to be liftable, and having a burring hole on the upper surface thereof, and surrounding the lifting pins The fixing device is provided in the bake device of the semiconductor track equipment, characterized in that it is provided with a plurality of fixing pins are provided on the upper surface, respectively, the butt hole.
이하, 상기와 같이 구성되는 본 발명 반도체 트랙장비의 베이크 장치를 첨부된 도면의 실시예를 참고하여 보다 상세히 설명하면 다음과 같다.Hereinafter, with reference to the embodiment of the accompanying drawings, the baking apparatus of the present invention semiconductor track equipment is configured as described above in more detail.
도 4는 본 발명 반도체 트랙장비용 베이크 장치의 구조를 보인 평면도이고, 도 5는 본 발명 반도체 트랙장비의 베이크 장치의 정면도로서, 도시된 바와 같이, 본 발명 반도체 트랙장비의 베이크 장치는 원판형의 베이크 플레이트(11)의 중앙부에 실린더(미도시)에 의하여 상,하방향으로 승강가능한 3개의 승강핀(12)이 설치되어 있고, 그 승강핀(12)들의 외측에는 베이크 플레이트(11)의 상면에 일정 높이의 고정핀(13)들이 설치되어 있다.Figure 4 is a plan view showing the structure of the baking apparatus for semiconductor track equipment of the present invention, Figure 5 is a front view of the baking apparatus of the semiconductor track equipment of the present invention, as shown, the baking apparatus of the semiconductor track equipment of the present invention is disc-shaped Three lifting pins 12 are provided at a central portion of the baking plate 11 to lift up and down by a cylinder (not shown), and the upper surface of the baking plate 11 is located outside the lifting pins 12. Fixing pins 13 of a certain height are installed.
그리고, 상기 승강핀(12)과 고정핀(13)들의 상면에는 웨이퍼(W)를 흡착고정하기 위한 버큠 홀(12a)(13a)들이 각각 형성되어 있다.On the upper surfaces of the lifting pins 12 and the fixing pins 13, burr holes 12a and 13a are formed to adsorb and fix the wafer W, respectively.
상기와 같이 구성되어 있는 본 발명 반도체 트랙장비의 베이크 장치에서 웨이퍼를 로딩시킬때는 승강핀(12)들이 하측에 설치된 실린더(미도시)에 의하여 일정 높이로 상승을 하면 도 6a와 같이 이송 암이 코팅작업을 마친 웨이퍼(W)를 승강핀(12)들의 상면에 얹어 놓는다. 그런 다음, 승강핀(12)에 형성되어 있는 버큠홀(12a)들을 통하여 버큠을 발생시켜서 웨이퍼(W)를 흡착고정하고, 그와 같은 상태에서 승강핀(12)을 하강시켜서 고정핀(13)들의 상면에 얹어 놓는다.When loading the wafer in the baking apparatus of the semiconductor track device of the present invention configured as described above, when the lifting pins 12 are raised to a certain height by a cylinder (not shown) installed on the lower side, the transfer arm is coated as shown in FIG. 6A. The finished wafer W is placed on the upper surfaces of the lifting pins 12. Then, by generating a burr through the burr holes 12a formed in the elevating pin 12, the wafer W is adsorbed and fixed, and the elevating pin 12 is lowered in such a state to fix the pin 13. Put on the top of the field.
그런 다음, 승강핀(12)들의 버큠홀(12a)들에 발생되던 버큠을 제거하고, 도 6b에 도시된 바와 같이, 고정핀(13)들에 형성된 버큠홀(13a)에 버큠을 발생시켜서 고정핀(13)의 상면에 웨이퍼(W)가 흡착고정되도록 한 상태에서 베이크작업을 실시한다.Then, the burrs generated in the burr holes 12a of the lifting pins 12 are removed, and as shown in FIG. 6B, the burrs are formed in the burr holes 13a formed in the fixing pins 13 and fixed. The baking operation is performed while the wafer W is attracted and fixed to the upper surface of the pin 13.
베이크작업을 마친 다음에 베이크 플레이트(11)에서 웨이퍼(W)를 언로딩할때의 동작은 상기의 역순으로 진행된다.The operation at the time of unloading the wafer W from the baking plate 11 after finishing the baking operation is performed in the reverse order.
즉, 상기 고정핀(13)들의 버큠홀(13a)에 발생되는 버큠을 차단하고, 승강핀(12)들이 상승을 하며 일정 높이로 웨이퍼(W)를 들어 올린다. 그와 같은 상태에서 이송 암이 웨이퍼(W)를 후공정을 진행하기 위한 장소로 이송하게 된다.That is, blocking the burrs generated in the burr holes 13a of the fixing pins 13 and lifting pins 12 are raised to lift the wafer W to a certain height. In such a state, the transfer arm transfers the wafer W to a place for performing a later process.
이상에서 상세히 설명한 바와 같이, 본 발명 반도체 트랙장비의 베이크 장치는 베이크 플레이트에 버큠홀이 구비된 수개의 승강핀을 설치하고, 그 승강핀들의 주변에 버큠홀이 구비된 수개의 고정핀을 설치하여, 베이크 플레이트에 웨이퍼의 안착시 웨이퍼를 버큠으로 흡착한 상태에서 안착시킴으로서, 위치틀어짐없이 정확히 안착시키는 효과가 있다.As described in detail above, the baking device of the semiconductor track device of the present invention is provided with a plurality of lifting pins provided with a butt hole on the baking plate, by installing a plurality of fixing pins provided with a butt hole around the lifting pins When the wafer is seated on the bake plate, the wafer is seated in a state in which the wafer is held in the suction state, so that the seat can be accurately seated without distortion.
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990034955A KR20010018840A (en) | 1999-08-23 | 1999-08-23 | Apparatus for baking wafer of semiconductor track system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990034955A KR20010018840A (en) | 1999-08-23 | 1999-08-23 | Apparatus for baking wafer of semiconductor track system |
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| Publication Number | Publication Date |
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| KR20010018840A true KR20010018840A (en) | 2001-03-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019990034955A KR20010018840A (en) | 1999-08-23 | 1999-08-23 | Apparatus for baking wafer of semiconductor track system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100603239B1 (en) * | 2003-09-25 | 2006-07-20 | 에스엠시 가부시키가이샤 | Temperature regulating apparatus for semi-conductor substrate |
-
1999
- 1999-08-23 KR KR1019990034955A patent/KR20010018840A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100603239B1 (en) * | 2003-09-25 | 2006-07-20 | 에스엠시 가부시키가이샤 | Temperature regulating apparatus for semi-conductor substrate |
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