KR20010005184A - Method of forming contact hole of semiconductor device - Google Patents
Method of forming contact hole of semiconductor device Download PDFInfo
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- KR20010005184A KR20010005184A KR1019990025984A KR19990025984A KR20010005184A KR 20010005184 A KR20010005184 A KR 20010005184A KR 1019990025984 A KR1019990025984 A KR 1019990025984A KR 19990025984 A KR19990025984 A KR 19990025984A KR 20010005184 A KR20010005184 A KR 20010005184A
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- Prior art keywords
- contact hole
- interlayer insulating
- insulating film
- forming
- etching
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000011229 interlayer Substances 0.000 claims abstract description 34
- 229920000642 polymer Polymers 0.000 claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 17
- 238000005260 corrosion Methods 0.000 claims abstract description 12
- 230000007797 corrosion Effects 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 11
- 239000010703 silicon Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 230000015572 biosynthetic process Effects 0.000 claims abstract 5
- 238000005530 etching Methods 0.000 claims description 19
- 239000010410 layer Substances 0.000 claims description 15
- 230000004888 barrier function Effects 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 9
- 150000002500 ions Chemical class 0.000 claims description 4
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 230000000903 blocking effect Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 콘택홀 형성방법에 관한 것으로, 특히 콘택홀 측벽의 적정위치에 일정량의 폴리머를 형성하고 특별한 블로킹층없이 산화막의 부식(corrosion)을 이용하여 콘택홀을 식각하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a contact hole in a semiconductor device, and more particularly, to a method of forming a predetermined amount of polymer at an appropriate position on a sidewall of a contact hole and etching a contact hole by using a corrosion of an oxide film without a special blocking layer. .
도 1a 내지 1c를 참조하여 종래 기술에 의한 반도체소자의 콘택홀 식각방법을 설명하면 다음과 같다.A contact hole etching method of a semiconductor device according to the prior art will be described with reference to FIGS. 1A to 1C as follows.
먼저, 도 1a에 나타낸 바와 같이 실리콘기판(1)상에 하부 금속배선(2)을 포함하는 하부구조를 형성하고 소정두께 이상의 층간절연막(3)을 형성한 후, 이 층간절연막(3)상에 콘택홀 형성을 위한 포토레지스트 마스크패턴(4)을 형성한다.First, as shown in FIG. 1A, a lower structure including a lower metal wiring 2 is formed on a silicon substrate 1, and an interlayer insulating film 3 having a predetermined thickness or more is formed thereon, and then on the interlayer insulating film 3. A photoresist mask pattern 4 for forming contact holes is formed.
이어서 도 1b에 나타낸 바와 같이 상기 포토레지스트 패턴(4)을 식각 장벽으로 이용하고 C와 F를 포함한 플라즈마를 사용하여 층간절연막(3)을 건식식각한다. 여기서, 화살표로 표시한 것이 에천트(etchant) 이온 또는 래디컬의 경로로서 포토레지스트 패턴의 측벽으로 입사된 에천트가 콘택홀 중간 부분으로 입사되는 모양을 나타내고 있다.Subsequently, as shown in FIG. 1B, the interlayer insulating film 3 is dry-etched using the photoresist pattern 4 as an etching barrier and using plasma containing C and F. Here, the arrows indicate that the etchant incident on the sidewall of the photoresist pattern as an etchant ion or radical path is incident on the middle portion of the contact hole.
도 1c는 콘택홀 식각이 완료된 후의 단면도로서, 콘택홀 프로파일상의 보윙(bowing)으로 인하여 콘택홀내에 형성될 도전층이 하부 금속배선(2)과의 단락을 유발할 가능성이 보일 정도로 마진이 부족한 모양을 나타내고 있다.Figure 1c is a cross-sectional view after the completion of the contact hole etching, the shape of the margin is insufficient enough that the conductive layer to be formed in the contact hole due to bowing on the contact hole profile is likely to cause a short circuit with the lower metal wiring (2) It is shown.
상기와 같이 진행되는 종래의 콘택홀 형성방법에서는 특히 높은 종횡비(aspect ratio)의 콘택홀 식각시 콘택홀로 입사된 후 반사되거나 산란되는 에천트에 의하여 콘택홀 내부를 전체적으로 보윙 프로파일로 만들어 콘택홀과 하부 배선과의 단락을 유발하는 문제점이 있다.In the conventional method for forming a contact hole as described above, the contact hole and the lower part of the contact hole are made as an overall bowing profile by an etchant that is reflected or scattered after being incident into the contact hole during the etching of the contact hole having a high aspect ratio. There is a problem that causes a short circuit with the wiring.
본 발명은 상술한 문제점을 해결하기 위한 것으로, 콘택홀 형성을 위한 포토레지스트 마스크패턴 형성후 건식식각에 의한 콘택홀 식각시 콘택홀 측벽의 적정위치에 일정량의 폴리머를 형성하고, 특별한 블로킹층없이 산화막의 부식을 이용하여 하부 배선에 대하여 자기정렬된 콘택홀을 형성하는 방법을 제공하는 것을 그 목적으로 한다.The present invention is to solve the above-mentioned problems, and after forming the photoresist mask pattern for forming the contact hole, a certain amount of polymer is formed at the proper position of the contact hole sidewall during the etching of the contact hole by dry etching, and an oxide film without a special blocking layer It is an object of the present invention to provide a method for forming a self-aligned contact hole with respect to the lower wiring by using the corrosion.
상기 목적을 달성하기 위한 본 발명의 반도체소자의 콘택홀 형성방법은 실리콘기판상에 하부 배선을 포함하는 하부구조를 형성하고, 그 전면에 층간절연막을 형성하는 제1단계와, 상기 층간절연막상에 콘택홀 형성을 위한 포토레지스트 패턴을 형성하는 제2단계, 상기 포토레지스트 패턴을 식각장벽으로 하여 C와 F를 포함하는 플라즈마를 사용하여 상기 층간절연막을 일차적으로 소정 두께만큼 건식식각함과 동시에 층간절연막의 식각에 의해 형성되는 콘택홀 측벽에 폴리머가 증착되도록 하는 제3단계, 상기 포토레지스트 패턴과 상기 콘택홀 측벽에 증착된 폴리머를 식각 장벽으로 하여 식각가스에 O2가스를 첨가하여 산화막 부식 현상을 이용하여 상기 층간절연막의 나머지 부분을 건식식각하는 제4단계를 포함하여 구성된다.The contact hole forming method of the semiconductor device of the present invention for achieving the above object is a first step of forming a lower structure including a lower wiring on a silicon substrate, and forming an interlayer insulating film on the front surface, and on the interlayer insulating film A second step of forming a photoresist pattern for forming a contact hole, using the plasma including C and F as an etch barrier to dry-etch the interlayer insulating film to a predetermined thickness, and simultaneously A third step of depositing a polymer on the sidewalls of the contact hole formed by the etching of the oxide, using the photoresist pattern and the polymer deposited on the sidewalls of the contacthole as an etch barrier to add the O2 gas to the etching gas to use the corrosion of the oxide film And dry etching the remaining portions of the interlayer insulating film.
도 1a 내지 도 1c는 종래 기술에 의한 반도체소자의 콘택홀 형성방법을 도시한 공정순서도,1A to 1C are process flowcharts showing a method for forming a contact hole in a semiconductor device according to the prior art;
도 2a 내지 2d는 본 발명에 의한 반도체소자의 콘택홀 형성방법을 도시한 공정순서도,2A to 2D are process flowcharts showing a method for forming a contact hole in a semiconductor device according to the present invention;
도 3은 종래 기술에 의해 형성된 콘택홀의 모양을 나타낸 SEM사진,3 is a SEM photograph showing the shape of a contact hole formed by the prior art;
도 4는 본 발명에 의해 형성된 콘택홀의 모양을 나타낸 SEM사진.Figure 4 is a SEM photograph showing the shape of the contact hole formed by the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
21.실리콘기판 22.하부 배선21.Silicone Board 22.Lower Wiring
23.층간절연막 24.포토레지스트 패턴23. Interlayer insulating film 24. Photoresist pattern
25.폴리머25.Polymer
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2a 내지 2d에 본 발명에 의한 반도체소자의 콘택홀 형성방법을 공정순서에 따라 도시하였다.2A to 2D illustrate a method for forming a contact hole in a semiconductor device according to the present invention in the order of a process.
먼저, 도 2a에 나타낸 바와 같이 실리콘기판(21)상에 하부 금속배선(22)을 포함하는 하부구조를 형성하고 소정두께 이상의 층간절연막(23)을 형성한 후, 이 층간절연막(23)상에 콘택홀 형성을 위한 포토레지스트 마스크패턴(24)을 형성한다. 상기 층간절연막(23)은 실리콘이 많이 함유된 옥시나이트라이드(Si-rich oxynitride)로 형성한다.First, as shown in FIG. 2A, a lower structure including a lower metal wiring 22 is formed on the silicon substrate 21, and an interlayer insulating film 23 having a predetermined thickness or more is formed thereon, and then on the interlayer insulating film 23. A photoresist mask pattern 24 for forming contact holes is formed. The interlayer insulating layer 23 is formed of silicon-rich oxynitride.
이어서 도 2b에 나타낸 바와 같이 상기 포토레지스패턴(24)을 식각장벽으로 이용하여 일차적으로 C와 F를 포함하는 플라즈마를 사용하여 상기 층간절연막(23)을 소정 두께만큼 건식식각한다. 플라즈마에 CHxFx가스를 첨가하여 다량의 CHx 래디컬을 유도한 다음 실리콘과 하부 배선물질에 대해서는 높은 선택비를 가지며 층간절연막을 이루는 나이트라이드에 대해서는 낮은 선택비를 가지게 하여 층간절연막을 식각할 수도 있다. 또한, IPS 또는 ICP 또는 TCP 또는 ECR 플라즈마 식각장비에서 CH2F2 가스를 포함한 플라즈마를 이용하여 다량의 CHx 래디컬을 유도한 후 실리콘에 대해서는 높은 선택비를 갖고 나이트라이드층에 대해서는 낮은 선택비를 가지게 하여 층간절연막을 식각할 수도 있다.Next, as shown in FIG. 2B, the interlayer insulating layer 23 is dry-etched by a predetermined thickness using a plasma including C and F primarily using the photoresist pattern 24 as an etching barrier. CHxFx gas may be added to the plasma to induce a large amount of CHx radicals, and then the interlayer insulating layer may be etched by having a high selectivity for silicon and a lower interconnection material and a low selectivity for nitride forming an interlayer insulating film. In addition, after inducing a large amount of CHx radicals using a plasma containing CH2F2 gas in an IPS or ICP or TCP or ECR plasma etching equipment, it has a high selectivity for silicon and a low selectivity for nitride layer. It can also be etched.
도면에서 점선 화살표로 표시한 것은 에천트 이온 또는 래디컬의 경로로서, 포토레지스트 패턴(24)의 측면에 상기 에천트 이온 또는 래디컬에 의해 약간의 경사가 만들어지며, 콘택홀 내부로 입사된 에천트는 층간절연막(23)과 반응하여 실선 화살표로 표시한 소량의 폴리머(25)를 발생하는 바, 이 폴리머는 콘택홀 측벽에 증착되어 식각 장벽으로 작용하게 된다.The dotted arrows in the figure indicate paths of etchant ions or radicals, and a slight inclination is made on the side of the photoresist pattern 24 by the etchant ions or radicals, and the etchant incident into the contact hole is interlayer. Reacting with the insulating film 23 generates a small amount of polymer 25 indicated by a solid arrow, which is deposited on the sidewalls of the contact holes to act as an etch barrier.
다음에 도 2c에 나타낸 바와 같이 상기와 같이 측벽이 약간 경사진 포토레지스트 패턴(24)과 상기 콘택홀 측벽에 증착된 폴리머(25)를 식각 장벽으로 하여 C와 F 이외에 O2를 포함한 플라즈마를 사용하여 더이상 폴리머가 증착되지 않도록 층간절연막(23)의 나머지 부분을 건식식각한다. 도면에서 점선 화살표는 계속해서 에천트가 입사되는 경로를 나타내며, 실선 화살표는 반사된 에천트의 경로로서 폴리머 생성없이 O2가스 첨가에 의한 산화막의 부식만으로 폴리머(25)의 바로 하단부터 보윙 프로파일이 형성된 모양을 나타낸다.Next, as shown in FIG. 2C, a plasma containing O 2 in addition to C and F is used by using a photoresist pattern 24 having a slightly inclined sidewall as described above and a polymer 25 deposited on the sidewall of the contact hole as an etch barrier. The remaining portion of the interlayer insulating film 23 is dry etched so that no more polymer is deposited. In the drawing, a dotted arrow indicates a path where an etchant continues to be incident, and a solid arrow indicates a path of a reflected etchant, where a bowing profile is formed from the bottom of the polymer 25 only by corrosion of the oxide film by addition of O 2 gas without generating polymer. It shows shape.
도 2d는 콘택홀 식각이 완료된 후의 단면도로서, 하부 배선(22) 높이에서 콘택홀 크기를 작게 하여 하부 배선(22)과 후속공정에서 콘택홀내에 형성될 도전층과의 스페이싱(spacing) 마진을 충분히 확보함으로써 하부 배선과 도전층간의 단락을 방지할 수 있게 된다.FIG. 2D is a cross-sectional view after the contact hole etching is completed, and the contact hole size is reduced at the height of the lower wiring 22 to sufficiently fill the spacing margin between the lower wiring 22 and the conductive layer to be formed in the contact hole in a subsequent process. By securing it, a short circuit between the lower wiring and the conductive layer can be prevented.
한편, 콘택홀 형성용 포토레지스트 패턴(24)을 이용한 콘택홀 식각시 O2가스를 첨가하여 산화막 부식현상을 이용하여 콘택홀 내부에 부분적인 보윙 프로파일을 형성한 후, C와 F가 포함된 플라즈마로 층간절연막을 소정두께 식각함과 동시에 콘택홀 측벽에 폴리머를 형성한 다음, 다시 O2가스를 첨가하여 산화막 부식현상을 이용하여 콘택홀 내부에 부분적인 보윙 프로파일을 형성함으로써 콘택홀 내부에 2중 보잉프로파일을 형성할 수도 있다.Meanwhile, during contact hole etching using the contact hole forming photoresist pattern 24, O2 gas is added to form a partial bowing profile inside the contact hole using oxide corrosion, and then into a plasma containing C and F. The interlayer insulating film is etched to a predetermined thickness and at the same time a polymer is formed on the sidewalls of the contact hole, and then O2 gas is added again to form a partial bowing profile inside the contact hole by using oxide corrosion. May be formed.
또한, O2가스 첨가에 의한 산화막 부식현상의 시점을 조절하여 보잉 프로파일의 위치를 조절하여 식각하는 것도 가능하다.In addition, it is also possible to etch by adjusting the position of the boeing profile by adjusting the timing of corrosion of the oxide film by the addition of O 2 gas.
도 3와 도 4에 종래 기술과 본 발명에 의해 형성한 콘택홀의 단면 형태를 비교하여 나타내었다.3 and 4 show cross-sectional shapes of contact holes formed by the prior art and the present invention.
상기와 같이 이루어지는 본 발명의 콘택홀 형성방법에서는 특히 높은 종횡비의 콘택홀 식각시 콘택홀로 입사된 에천트에 의하여 발생되는 측벽 폴리머를 식각장벽으로 이용하고 콘택홀 내부를 산화막 부식을 이용하여 부분적으로 보윙 프로파일로 만들어 콘택홀과 하부 배선과의 단락을 방지한다.In the method of forming a contact hole of the present invention as described above, the sidewall polymer generated by the etchant incident into the contact hole during the etching of the high aspect ratio contact hole is used as the etching barrier, and the inside of the contact hole is partially bowed using the oxide film corrosion. The profile prevents short circuits between the contact holes and the bottom wiring.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
본 발명에 의하면, 콘택홀 식각시 콘택홀 측벽의 적정위치에 일정량의 폴리머를 형성한 후, 특별한 블로킹층없이 산화막 부식을 이용하여 하부 배선 패턴에 대하여 자기정렬된 콘택홀을 형성하여 하부 배선과의 충분한 스페이싱 마진을 확보함으로써 반도체소자 설계 마진를 확보하고 소자의 수율과 특성 향상을 도모할 수 있다.According to the present invention, a predetermined amount of polymer is formed at an appropriate position on the sidewall of the contact hole during the etching of the contact hole, and then a self-aligned contact hole is formed on the lower wiring pattern by using oxide corrosion without a special blocking layer. By securing sufficient spacing margins, it is possible to secure design margins for semiconductor devices and to improve device yield and characteristics.
Claims (10)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100762227B1 (en) * | 2001-12-15 | 2007-10-01 | 주식회사 하이닉스반도체 | Method for forming the capacitor of semiconductor device |
| KR100866124B1 (en) * | 2002-12-03 | 2008-10-31 | 주식회사 하이닉스반도체 | Method for forming capacitor of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH06236864A (en) * | 1969-04-23 | 1994-08-23 | Hitachi Ltd | Etching method, processing method after etching, and etching equipment |
| JPH10177992A (en) * | 1996-12-16 | 1998-06-30 | Sharp Corp | Taper etching method of micro contact hole |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100762227B1 (en) * | 2001-12-15 | 2007-10-01 | 주식회사 하이닉스반도체 | Method for forming the capacitor of semiconductor device |
| KR100866124B1 (en) * | 2002-12-03 | 2008-10-31 | 주식회사 하이닉스반도체 | Method for forming capacitor of semiconductor device |
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