KR20010004273A - Method of manufacturing a semiconductor device - Google Patents
Method of manufacturing a semiconductor device Download PDFInfo
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- KR20010004273A KR20010004273A KR1019990024896A KR19990024896A KR20010004273A KR 20010004273 A KR20010004273 A KR 20010004273A KR 1019990024896 A KR1019990024896 A KR 1019990024896A KR 19990024896 A KR19990024896 A KR 19990024896A KR 20010004273 A KR20010004273 A KR 20010004273A
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- layer
- gate electrode
- semiconductor device
- epitaxial growth
- thickness
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 68
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 10
- 125000006850 spacer group Chemical group 0.000 claims abstract description 6
- 238000000206 photolithography Methods 0.000 claims abstract description 5
- 150000002500 ions Chemical class 0.000 claims abstract description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 3
- 239000002184 metal Substances 0.000 claims abstract description 3
- 229910052751 metal Inorganic materials 0.000 claims abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 3
- 229920005591 polysilicon Polymers 0.000 claims abstract description 3
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 3
- 238000005468 ion implantation Methods 0.000 claims description 17
- 230000001590 oxidative effect Effects 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 238000007517 polishing process Methods 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 2
- 239000007943 implant Substances 0.000 abstract 1
- 230000005465 channeling Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
Abstract
Description
본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 선택적 에피택셜 성장(Selective Epitaxial Growth; 이하, SEG라 함) 방법을 이용하여 엘리베이티드(elevated) 소오스/드레인 구조를 형성할때 선택적 에피택셜 성장층을 게이트 전극보다 높게 형성하고 이를 화학적 기계적 연마(Chemical Michenical Polishing; CMP) 공정으로 평탄화하므로써 SEG층에 발생된 패이싯(facet)을 제거하여 균일하면서 동시에 얕은 깊이의 접합 영역을 형성할 수 있는 반도체 소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in particular, to form an selective source epitaxial growth layer when forming an elevated source / drain structure using a method of selective epitaxial growth (hereinafter referred to as SEG). Fabrication of a semiconductor device capable of forming a junction region having a uniform and shallow depth by removing the facet generated in the SEG layer by forming it higher than the gate electrode and planarizing it by a chemical mechanical polishing (CMP) process. It is about a method.
반도체 소자가 고집적화됨에 따라, 소자의 접합깊이 또한 점점 낮게 형성하고 있는 실정이다. 접합영역의 깊이를 낮게 형성하기 위하여 일반적으로는 이온 주입 공정시의 에너지를 낮추는 방법을 사용하고 있다. 그러나 이 방법은 이온 주입시 충분한 빔 전류(beam current)를 얻을 수 없고, 낮은 이온 주입 에너지에서 채널링 가능성이 증가하는 등의 문제점이 있다.As semiconductor devices are highly integrated, the junction depths of the devices are also becoming lower. In order to reduce the depth of the junction region, a method of lowering the energy during the ion implantation process is generally used. However, this method has problems such as not being able to obtain a sufficient beam current at the time of ion implantation and increasing the possibility of channeling at low ion implantation energy.
이러한 문제를 해결하기 위해 반도체 기판에 게이트 전극을 형성한 다음 소오스 및 드레인 영역에만 선택적으로 실리콘층을 형성하여 소오스 및 드레인 영역의 높이를 증가시켜 주는 SEG 방법이 제안되었다. 이 방법을 도 1을 참조하여 설명하면 다음과 같다.In order to solve this problem, a SEG method has been proposed that increases the height of the source and drain regions by forming a gate electrode on a semiconductor substrate and then selectively forming a silicon layer only in the source and drain regions. This method is described with reference to FIG. 1 as follows.
도 1은 종래 반도체 소자 제조 방법을 설명하기 위해 도시한 소자의 단면도이다.1 is a cross-sectional view showing a device for explaining a conventional semiconductor device manufacturing method.
먼저, 반도체 기판(11)을 열산화하여 게이트 산화막(12)을 형성하고, 전체구조 상에 게이트 전극용 도전층(13) 및 제 1 절연막(14)을 순차적으로 형성한다. 이후, 포토리소그라피 공정 및 식각 공정에 의해 게이트 전극이 형성될 부분을 정의하고 제 1 절연막(14) 및 도전층(13)을 순차적으로 제거하여 게이트 전극을 형성한다. 다음에, 저농도 불순물을 이용한 이온주입 공정으로 LDD 영역(16)을 형성한다. 이후, 전체구조 상에 제 2 절연막(15)을 형성한 후 전면 식각을 실시하여 게이트 전극 양측부에 스페이서를 형성한다. 다음으로, 엘리베이티드(elevated) 소오스, 드레인 구조를 형성하기 위해 SEG 공정을 수행하여 SEG층(17)을 형성한 후, 고농도 이온 주입 공정을 실시하여 접합 영역(18)을 형성한다.First, the gate oxide film 12 is formed by thermally oxidizing the semiconductor substrate 11, and the conductive layer 13 and the first insulating film 14 for the gate electrode are sequentially formed on the entire structure. Subsequently, a portion in which the gate electrode is to be formed is defined by a photolithography process and an etching process, and the first insulating layer 14 and the conductive layer 13 are sequentially removed to form the gate electrode. Next, the LDD region 16 is formed by an ion implantation process using low concentration impurities. Subsequently, after forming the second insulating layer 15 on the entire structure, the entire surface is etched to form spacers at both sides of the gate electrode. Next, the SEG layer 17 is formed by performing an SEG process to form an elevated source and drain structure, followed by a high concentration ion implantation process to form the junction region 18.
이상에서 설명한 바와 같은 반도체 소자의 LDD 구조 형성 방법의 경우, LDD영역(16) 형성을 위한 이온 주입 공정을 실시한 다음 SEG 공정을 진행하기 때문에 이온 주입 공정시 충분한 빔 전류(beam current)를 얻는 문제나 낮은 에너지에서의 채널링 가능성 증가 문제 등을 해결할 수 없다. 또한, SEG 공정의 특성상 게이트 전극의 에지(edge) 부분에 패이싯(facet) 현상이 발생(A 부분)하고, 패이싯 현상이 발생한 지역(A 부분)에서 후속 접합 영역(18) 형성을 위한 이온주입 공정시 접합의 깊이가 부분적으로 깊어지는 문제가 있다(B 부분 참조). 이러한 패이싯 현상은 게이트 전극의 에지 부분에 발생하기 때문에, 게이트 전극의 에지 부분에서는 접합 깊이가 낮고 그 이외의 지역에서는 깊은 접합을 갖는 LDD 구조를 형성할 수 없는 문제가 있다.As described above, in the method of forming the LDD structure of the semiconductor device, since the ion implantation process for forming the LDD region 16 is performed followed by the SEG process, there is a problem of obtaining sufficient beam current during the ion implantation process. Problems such as increased channeling potential at low energy cannot be solved. In addition, due to the characteristics of the SEG process, a facet phenomenon occurs at an edge portion of the gate electrode (part A), and ions for forming a subsequent junction region 18 in a region (part A) where the facet phenomenon occurs. There is a problem that the depth of the junction is partially deep during the injection process (see section B). Since this facet phenomenon occurs at the edge portion of the gate electrode, there is a problem that an LDD structure having a low junction depth at the edge portion of the gate electrode and a deep junction at other regions cannot be formed.
따라서, 본 발명은 게이트 전극을 형성하고 선택적 에피택셜 성장층을 형성하되 이를 게이트 전극보다 높은 두께로 형성하고, 이후 CMP 공정을 이용하여 표면을 평탄화하므로써 선택적 에피택셜 성장층에 발생된 패이싯(facet) 현상이 제거되어 접합 영역을 균일하면서 동시에 얕은 두께로 형성할 수 있는 반도체 소자 제조 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention forms a gate electrode and forms a selective epitaxial growth layer, which is formed to a thickness higher than that of the gate electrode, and is then facet generated in the selective epitaxial growth layer by planarizing the surface using a CMP process. It is an object of the present invention to provide a method for fabricating a semiconductor device in which a phenomenon is eliminated to form a junction region with a uniform and shallow thickness.
상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자 제조 방법은 소자분리 공정을 실시한 반도체 기판을 열산화시켜 게이트 산화막을 형성하고 전체구조 상에 도전층 및 제 1 절연막을 순차적으로 형성하는 단계; 포토리소그라피 공정 및 식각 공정으로 게이트 전극이 형성될 부분을 정의하고 상기 제 1 절연막 및 도전층을 순차적으로 식각하여 게이트 전극을 형성하는 단계; 상기 반도체 기판을 산화 분위기에서 열처리하여 게이트 산화막 상부 및 도전층 측벽에 열산화막을 형성한 후, 저농도 이온 주입 공정을 실시하여 LDD 영역을 형성하는 단계; 전체구조 상에 제 2 절연막을 형성하고 전면 식각 공정을 실시하여 게이트 전극 측벽에 절연막 스페이서를 형성하는 단계; 상기 단계로부터 세정 공정을 실시한 후 선택적 에피택셜 성장 공정을 실시하여 노출된 반도체 기판 상에 선택적 에피택셜 성장층을 형성하는 단계; 상기 제 1 절연막을 연마 정지층으로 하여 화학적 기계적 연마 공정을 실시하여 상기 선택적 에피택셜 성장층을 연마하고, 이로 인하여 선택적 에피택셜 성장층의 패이싯 부분이 제거되는 단계; 고농도 이온주입 공정을 실시하고 급속 열처리하여 접합 영역을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.A semiconductor device manufacturing method according to the present invention for achieving the above object comprises the steps of thermally oxidizing a semiconductor substrate subjected to the device isolation process to form a gate oxide film and sequentially forming a conductive layer and a first insulating film on the entire structure; Defining a portion where the gate electrode is to be formed by a photolithography process and an etching process and sequentially etching the first insulating layer and the conductive layer to form a gate electrode; Heat-treating the semiconductor substrate in an oxidizing atmosphere to form a thermal oxide layer on the gate oxide layer and the sidewalls of the conductive layer, and then performing a low concentration ion implantation process to form an LDD region; Forming an insulating film spacer on the sidewalls of the gate electrode by forming a second insulating film on the entire structure and performing an entire surface etching process; Performing a cleaning process from the step and then performing a selective epitaxial growth process to form a selective epitaxial growth layer on the exposed semiconductor substrate; Performing a chemical mechanical polishing process using the first insulating layer as a polishing stop layer to polish the selective epitaxial growth layer, thereby removing the facet portion of the selective epitaxial growth layer; It characterized in that it comprises a step of performing a high concentration ion implantation process and rapid heat treatment to form a junction region.
도 1은 종래 반도체 소자 제조 방법을 설명하기 위해 도시한 소자의 단면도.1 is a cross-sectional view of a device shown for explaining a conventional semiconductor device manufacturing method.
도 2a 내지 2d는 본 발명에 따른 반도체 소자 제조 방법을 설명하기 위해 도시한 소자의 단면도.2A to 2D are cross-sectional views of a device for explaining the method of manufacturing a semiconductor device according to the present invention.
〈도면의 주요 부분에 대한 부호 설명〉<Description of Signs of Major Parts of Drawings>
11, 21 : 반도체 기판 12, 22 : 게이트 산화막11 and 21: semiconductor substrate 12 and 22: gate oxide film
13, 23 : 도전층 14, 24 : 제 1 절연막13, 23: conductive layers 14, 24: first insulating film
15 : 제 2 절연막 16, 26 : LDD 영역15: second insulating film 16, 26: LDD region
17, 28 : SEG층 18, 29 : 접합 영역17, 28: SEG layer 18, 29: junction region
25 : 열산화막 27 : 절연막 스페이서25 thermal oxide film 27 insulating film spacer
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2a 내지 2d는 본 발명에 따른 반도체 소자 제조 방법을 설명하기 위해 도시한 소자의 단면도이다.2A to 2D are cross-sectional views of a device for explaining the method of manufacturing a semiconductor device according to the present invention.
도 2a에 도시된 바와 같이, 소자분리 공정을 실시한 반도체 기판(21)을 열산화시켜 게이트 산화막(22)을 형성하고 전체구조 상에 도전층(23) 및 제 1 절연막(24)을 순차적으로 형성한다. 이후, 포토리소그라피 공정 및 식각 공정으로 게이트 전극이 형성될 부분을 정의하고 제 1 절연막(24) 및 도전층(23)을 순차적으로 식각하여 게이트 전극을 형성한다. 도전층(23)은 도프트 폴리실리콘, 비정질 실리콘, 금속 및 실리사이드의 다층 구조 중 어느 하나를 이용하여 형성한다. 제 1 절연막(24)은 1000 내지 2000Å의 두께로 형성하며 게이트 전극 패터닝시 마스크 역할을 한다. 다음에 산화 분위기에서 열처리하여 게이트 산화막(22) 상부 및 도전층(23) 측벽에 열산화막(25)을 형성한 후, 저농도 이온 주입 공정을 실시하여 LDD 영역(26)을 형성한다. 열산화막(25)은 30 내지 100Å의 두께로 형성한다.As shown in FIG. 2A, the gate oxide film 22 is formed by thermally oxidizing the semiconductor substrate 21 subjected to the device isolation process, and the conductive layer 23 and the first insulating film 24 are sequentially formed on the entire structure. do. Subsequently, a portion in which the gate electrode is to be formed is defined by a photolithography process and an etching process, and the first insulating layer 24 and the conductive layer 23 are sequentially etched to form a gate electrode. The conductive layer 23 is formed using any one of a multilayer structure of doped polysilicon, amorphous silicon, metal, and silicide. The first insulating layer 24 is formed to a thickness of 1000 to 2000Å and serves as a mask when patterning the gate electrode. Next, the thermal oxidation film 25 is formed on the gate oxide film 22 and the sidewalls of the conductive layer 23 by heat treatment in an oxidizing atmosphere, and then a low concentration ion implantation process is performed to form the LDD region 26. The thermal oxide film 25 is formed to a thickness of 30 to 100 GPa.
도 2b는 전체구조 상에 제 2 절연막을 형성하고 전면 식각 공정을 실시하여 게이트 전극 측벽에 절연막 스페이서(27)을 형성한 상태를 나타내는 소자의 단면도이다.FIG. 2B is a cross-sectional view of a device in which a second insulating film is formed over the entire structure and an entire surface etching process is performed to form an insulating film spacer 27 on the sidewall of the gate electrode.
도 2c는 세정 공정을 실시한 후 SEG 공정을 실시하여 노출된 반도체 기판(21) 상에 SEG층(28A)을 형성한 상태를 나타내는 소자의 단면도이다. SEG층(28A)은 게이트 전극의 두께보다 300 내지 500Å 두껍게 형성한다.FIG. 2C is a cross-sectional view of a device illustrating a state in which the SEG layer 28A is formed on the exposed semiconductor substrate 21 by performing the SEG process after performing the cleaning process. The SEG layer 28A is formed to be 300 to 500 mm thicker than the thickness of the gate electrode.
도 2d에 도시된 것과 같이, CMP 공정을 실시하여 게이트 전극보다 두껍게 형성된 SEG층(28A)을 연마하므로써 SEG층(28A)의 패이싯 부분을 제거한다. 이때 SEG층(28A)은 500 내지 700Å의 두께만큼 제거된다. CMP 공정시 제 1 절연막(24)은 연마 정지층의 역할을 하며 이를 위하여 제 1 절연막(24)은 실리콘 질화막을 이용하여 형성한다. 이후, 고농도 이온주입 공정을 실시하여 접합 영역(소오스 및 드레인 영역; 29)을 형성한다. 고농도 이온주입 공정은 이온 주사 범위가 CMP 공정 후 잔류하는 SEG층(28) 두께의 1/2 내지 3/4 정도의 깊이가 되도록 이온주입 에너지를 조절하여 실시한다. 고농도 이온주입 공정 후 급속 열처리(RTA) 공정을 실시하여 도펀트를 활성화시킨다. 급속 열처리 공정은 900 내지 1000℃의 온도에서 10 내지 30초간 실시한다. 도시된 것과 같이, 접합 영역(29)은 게이트 전극의 에지(edge) 부분에서 깊이 형성됨이 없이 균일하게 형성된 것을 알 수 있다.As shown in FIG. 2D, the facet portion of the SEG layer 28A is removed by performing a CMP process to polish the SEG layer 28A formed thicker than the gate electrode. At this time, the SEG layer 28A is removed by a thickness of 500 to 700 GPa. In the CMP process, the first insulating film 24 serves as a polishing stop layer. For this purpose, the first insulating film 24 is formed using a silicon nitride film. Thereafter, a high concentration ion implantation process is performed to form a junction region (source and drain region) 29. The high concentration ion implantation process is performed by adjusting the ion implantation energy so that the ion scanning range becomes a depth of about 1/2 to 3/4 of the thickness of the SEG layer 28 remaining after the CMP process. After the high concentration ion implantation process, a rapid heat treatment (RTA) process is performed to activate the dopant. The rapid heat treatment process is carried out for 10 to 30 seconds at a temperature of 900 to 1000 ℃. As shown, it can be seen that the junction region 29 is uniformly formed without being deeply formed at the edge portion of the gate electrode.
상술한 바와 같이 본 발명에 따르면, 선택적 에피택셜 성장(SEG)법을 이용하여 엘리베이티드(elevated) 접합 영역을 형성하는 경우, 선택적 에피택셜 성장(SEG)층을 게이트 전극보다 두껍게 형성하고 CMP 공정을 실시하여 SEG층의 패이싯 부분을 제거하므로써 균일한 두께의 접합 영역을 얕은 깊이로 형성할 수 있다. 이에 따라 반도체 소자를 고집적화할 수 있고 쇼트 채널 효과가 억제된 반도체 소자를 제조할 수 있다.As described above, according to the present invention, when forming an elevated junction region using the selective epitaxial growth (SEG) method, the selective epitaxial growth (SEG) layer is formed thicker than the gate electrode and the CMP process is performed. By removing the facet portion of the SEG layer, a junction region having a uniform thickness can be formed at a shallow depth. As a result, the semiconductor device can be highly integrated and a semiconductor device in which the short channel effect is suppressed can be manufactured.
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