KR20000076811A - 반도체 장치 및 그 제조 방법 - Google Patents

반도체 장치 및 그 제조 방법 Download PDF

Info

Publication number
KR20000076811A
KR20000076811A KR1020000011997A KR20000011997A KR20000076811A KR 20000076811 A KR20000076811 A KR 20000076811A KR 1020000011997 A KR1020000011997 A KR 1020000011997A KR 20000011997 A KR20000011997 A KR 20000011997A KR 20000076811 A KR20000076811 A KR 20000076811A
Authority
KR
South Korea
Prior art keywords
semiconductor chip
layer
forming
wiring
semiconductor device
Prior art date
Application number
KR1020000011997A
Other languages
English (en)
Korean (ko)
Inventor
이토시게야스
Original Assignee
이데이 노부유끼
소니 가부시끼 가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이데이 노부유끼, 소니 가부시끼 가이샤 filed Critical 이데이 노부유끼
Publication of KR20000076811A publication Critical patent/KR20000076811A/ko

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B31MAKING ARTICLES OF PAPER, CARDBOARD OR MATERIAL WORKED IN A MANNER ANALOGOUS TO PAPER; WORKING PAPER, CARDBOARD OR MATERIAL WORKED IN A MANNER ANALOGOUS TO PAPER
    • B31BMAKING CONTAINERS OF PAPER, CARDBOARD OR MATERIAL WORKED IN A MANNER ANALOGOUS TO PAPER
    • B31B50/00Making rigid or semi-rigid containers, e.g. boxes or cartons
    • B31B50/26Folding sheets, blanks or webs
    • B31B50/52Folding sheets, blanks or webs by reciprocating or oscillating members, e.g. fingers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B31MAKING ARTICLES OF PAPER, CARDBOARD OR MATERIAL WORKED IN A MANNER ANALOGOUS TO PAPER; WORKING PAPER, CARDBOARD OR MATERIAL WORKED IN A MANNER ANALOGOUS TO PAPER
    • B31BMAKING CONTAINERS OF PAPER, CARDBOARD OR MATERIAL WORKED IN A MANNER ANALOGOUS TO PAPER
    • B31B2100/00Rigid or semi-rigid containers made by folding single-piece sheets, blanks or webs
    • B31B2100/002Rigid or semi-rigid containers made by folding single-piece sheets, blanks or webs characterised by the shape of the blank from which they are formed
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B31MAKING ARTICLES OF PAPER, CARDBOARD OR MATERIAL WORKED IN A MANNER ANALOGOUS TO PAPER; WORKING PAPER, CARDBOARD OR MATERIAL WORKED IN A MANNER ANALOGOUS TO PAPER
    • B31BMAKING CONTAINERS OF PAPER, CARDBOARD OR MATERIAL WORKED IN A MANNER ANALOGOUS TO PAPER
    • B31B2110/00Shape of rigid or semi-rigid containers
    • B31B2110/30Shape of rigid or semi-rigid containers having a polygonal cross section
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
KR1020000011997A 1999-03-12 2000-03-10 반도체 장치 및 그 제조 방법 KR20000076811A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP6689799 1999-03-12
JP99-66897 1999-03-12

Publications (1)

Publication Number Publication Date
KR20000076811A true KR20000076811A (ko) 2000-12-26

Family

ID=13329192

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020000011997A KR20000076811A (ko) 1999-03-12 2000-03-10 반도체 장치 및 그 제조 방법

Country Status (2)

Country Link
KR (1) KR20000076811A (zh)
CN (1) CN1267087A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100595891B1 (ko) * 2004-01-27 2006-06-30 가시오게산키 가부시키가이샤 반도체장치

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7171645B2 (en) * 2002-08-06 2007-01-30 Matsushita Electric Industrial Co., Ltd. Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device of generating pattern used for semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100595891B1 (ko) * 2004-01-27 2006-06-30 가시오게산키 가부시키가이샤 반도체장치

Also Published As

Publication number Publication date
CN1267087A (zh) 2000-09-20

Similar Documents

Publication Publication Date Title
KR101858952B1 (ko) 반도체 패키지 및 이의 제조 방법
JP4934053B2 (ja) 半導体装置およびその製造方法
US7413931B2 (en) Semiconductor device manufacturing method
US6380048B1 (en) Die paddle enhancement for exposed pad in semiconductor packaging
EP0907204A2 (en) Chip size package semiconductor device and method of forming the same
JP2008091714A (ja) 半導体装置
KR20050023538A (ko) 센터 패드를 갖는 적층형 반도체 패키지 및 그 제조방법
JP2003078106A (ja) チップ積層型パッケージ素子及びその製造方法
KR101858954B1 (ko) 반도체 패키지 및 이의 제조 방법
US20040227251A1 (en) Semiconductor device and method for fabricating semiconductor device
EP3547364B1 (en) Semiconductor chip and semiconductor package including the same
KR102493465B1 (ko) 인쇄회로기판 및 이를 가지는 반도체 패키지
KR101837514B1 (ko) 반도체 패키지, 이의 제조 방법 및 시스템 인 패키지
JP2004158595A (ja) 回路装置、回路モジュールおよび回路装置の製造方法
US7193297B2 (en) Semiconductor device, method for manufacturing the same, circuit substrate and electronic device
JP4084737B2 (ja) 半導体装置
US6689637B2 (en) Method of manufacturing a multi-chip semiconductor package
US6911721B2 (en) Semiconductor device, method for manufacturing semiconductor device and electronic equipment
KR20000076811A (ko) 반도체 장치 및 그 제조 방법
KR20130050077A (ko) 스택 패키지 및 이의 제조 방법
KR100498470B1 (ko) 적층형 반도체 패키지 및 그 제조방법
JP2630294B2 (ja) 混成集積回路装置およびその製造方法
JP2005033105A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
JP2000332155A (ja) 半導体装置及びその製造方法
KR100997792B1 (ko) 반도체 패키지 및 그의 제조방법

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination