KR20000075069A - Fabricating method of semiconductor device - Google Patents
Fabricating method of semiconductor device Download PDFInfo
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- KR20000075069A KR20000075069A KR1019990019429A KR19990019429A KR20000075069A KR 20000075069 A KR20000075069 A KR 20000075069A KR 1019990019429 A KR1019990019429 A KR 1019990019429A KR 19990019429 A KR19990019429 A KR 19990019429A KR 20000075069 A KR20000075069 A KR 20000075069A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 238000000034 method Methods 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 150000004767 nitrides Chemical class 0.000 claims abstract description 40
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 13
- 238000002955 isolation Methods 0.000 claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 8
- 229920005591 polysilicon Polymers 0.000 claims abstract description 8
- 150000002500 ions Chemical class 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 238000005498 polishing Methods 0.000 claims abstract description 3
- 238000005468 ion implantation Methods 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 2
- 239000000126 substance Substances 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract 9
- 238000007254 oxidation reaction Methods 0.000 abstract 9
- 238000002347 injection Methods 0.000 abstract 1
- 239000007924 injection Substances 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 238000010301 surface-oxidation reaction Methods 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 피지아이(profiled grooved isolation : PGI) 격리영역의 격리특성을 향상시키기에 적당하도록 한 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device suitable for improving the isolation characteristics of a profiled grooved isolation (PGI) isolation region.
종래 반도체소자의 제조방법을 첨부한 도1a 내지 도1h에 도시한 수순단면도를 참조하여 상세히 설명하면 다음과 같다.A detailed description will now be made with reference to the procedure cross-sectional view shown in FIGS. 1A to 1H attached to a conventional method of manufacturing a semiconductor device.
먼저, 도1a에 도시한 바와같이 반도체기판(1)의 상부에 패드산화막(2)을 형성하고, 질화막(3)을 증착한 다음 질화막(3)의 상부에 감광막(PR1)을 도포하고, 노광 및 현상하여 감광막(PR1) 패턴을 형성한다. 이때, 감광막(PR1) 패턴은 반도체기판(1)의 격리영역에 해당하는 질화막(3)이 노출되도록 형성한다.First, as shown in FIG. 1A, the pad oxide film 2 is formed on the semiconductor substrate 1, the nitride film 3 is deposited, and then the photoresist film PR1 is coated on the nitride film 3, and exposed. And developing to form the photosensitive film PR1 pattern. In this case, the photoresist film PR1 pattern is formed so that the nitride film 3 corresponding to the isolation region of the semiconductor substrate 1 is exposed.
그리고, 도1b에 도시한 바와같이 상기 감광막(PR1) 패턴을 적용하여 질화막(3)과 패드산화막(2)을 식각한 후, 감광막(PR1) 패턴을 제거한다.As shown in FIG. 1B, the nitride film 3 and the pad oxide film 2 are etched by applying the photoresist film PR1 pattern, and then the photoresist film PR1 pattern is removed.
그리고, 도1c에 도시한 바와같이 상기 질화막(3)을 마스크로 적용하여 노출된 반도체기판(1)을 식각함으로써, PGI 영역(4)을 형성한다.1C, the exposed semiconductor substrate 1 is etched by applying the nitride film 3 as a mask, thereby forming the PGI region 4.
그리고, 도1d에 도시한 바와같이 상기 PGI 영역(4)이 채워지도록 질화막(3)의 상부까지 산화막(5)을 증착한다.As shown in FIG. 1D, the oxide film 5 is deposited to the upper portion of the nitride film 3 so that the PGI region 4 is filled.
그리고, 도1e에 도시한 바와같이 상기 산화막(5)을 질화막(3)이 노출될때까지 화학기계적 연마하여 평탄화한다.As shown in Fig. 1E, the oxide film 5 is chemically polished and planarized until the nitride film 3 is exposed.
그리고, 도1f에 도시한 바와같이 상기 질화막(3)과 패드산화막(2)을 제거하여 반도체기판(1)의 표면을 평탄화한 후, 반도체기판(1) 내에 웰 이온주입 및 채널 이온주입(미도시)을 실시하고, 반도체기판(1)의 상부전면에 게이트산화막(6)을 형성한다.1F, the surface of the semiconductor substrate 1 is planarized by removing the nitride film 3 and the pad oxide film 2, and then well ion implantation and channel ion implantation into the semiconductor substrate 1 (not shown). The gate oxide film 6 is formed on the upper surface of the semiconductor substrate 1.
그리고, 도1g에 도시한 바와같이 상기 게이트산화막(6)의 상부에 폴리실리콘(7)을 형성하고, 패터닝하여 게이트를 형성한다.As shown in FIG. 1G, a polysilicon 7 is formed on the gate oxide film 6 and patterned to form a gate.
그리고, 도1h에 도시한 바와같이 상기 폴리실리콘(7)이 패터닝되지 않은 반도체기판(1)의 액티브영역 내에 불순물이온을 주입하여 소스/드레인 영역(8)을 형성한다.1H, impurity ions are implanted into the active region of the semiconductor substrate 1 in which the polysilicon 7 is not patterned to form a source / drain region 8.
그러나, 상기한 바와같은 종래 반도체소자의 제조방법은 소스/드레인 영역과 반도체기판의 경계면이 크기 때문에 소스/드레인 영역의 누설전류가 증가하는 문제점이 있고, 이에 따라 디램(DRAM)이나 에스램(SRAM) 셀의 제조시 데이터 보존 시간(data retention time)의 감소로 인해 메모리셀의 신뢰성이 저하되는 문제점이 있었다.However, the conventional method of manufacturing a semiconductor device as described above has a problem in that the leakage current of the source / drain regions increases due to the large interface between the source / drain regions and the semiconductor substrate, and accordingly, the DRAM or SRAM ) There is a problem that the reliability of the memory cell is degraded due to the reduction of data retention time in manufacturing the cell.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 소스/드레인 영역과 반도체기판의 경계면을 최소화함과 아울러 피지아이 격리영역의 격리특성을 향상시킬 수 있는 반도체소자의 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to minimize the interface between the source / drain region and the semiconductor substrate and to improve the isolation characteristics of the PIG eye isolation region. It is to provide a method of manufacturing a device.
도1a 내지 도1h는 종래 반도체소자의 제조방법을 보인 수순단면도.1A to 1H are cross-sectional views showing a conventional method for manufacturing a semiconductor device.
도2a 내지 도2j는 본 발명의 일 실시예를 보인 수순단면도.Figures 2a to 2j is a cross-sectional view showing an embodiment of the present invention.
***도면의 주요부분에 대한 부호의 설명****** Explanation of symbols for main parts of drawing ***
11:반도체기판 12:패드산화막11: semiconductor substrate 12: pad oxide film
13:질화막 14:PGI 영역13: Nitride film 14: PGI region
15:절연막 16,17:산화막15: insulating film 16, 17: oxide film
18:게이트산화막 19:폴리실리콘18: gate oxide film 19: polysilicon
20:소스/드레인 영역 PR11:감광막20: source / drain area PR11: photosensitive film
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자의 제조방법은 반도체기판의 상부에 순차적으로 패드산화막, 질화막 및 감광막을 형성하는 공정과; 상기 감광막을 노광 및 현상하여 반도체기판 격리영역 상의 질화막이 노출되도록 감광막 패턴을 형성하고, 이를 적용하여 질화막과 패드산화막을 식각한 후, 감광막 패턴을 제거하는 공정과; 상기 질화막을 마스크로 적용하여 노출된 반도체기판을 식각한 다음 상부전면에 절연막을 형성하고, 선택적으로 식각하여 반도체기판의 식각된 측면에 절연막 측벽을 형성하는 공정과; 상기 반도체기판의 식각된 바닥면을 등방성 식각한 후, 제1산화막을 반도체기판의 등방성 식각된 영역에 성장시킨 다음 상기 절연막 측벽을 제거하고, 제2산화막을 질화막의 상부까지 증착하여 반도체기판의 식각된 영역을 채우는 공정과; 상기 산화막을 화학기계적 연마하여 평탄화하고, 질화막과 패드산화막을 제거하여 반도체기판의 표면을 평탄화한 다음 웰 이온주입 및 채널 이온주입을 실시하고, 상부전면에 게이트산화막을 형성하는 공정과; 상기 게이트산화막의 상부에 폴리실리콘을 형성하고, 패터닝하여 게이트를 형성한 다음 게이트가 형성되지 않은 반도체기판의 액티브영역 내에 불순물이온을 주입하여 소스/드레인 영역을 형성하는 공정을 구비하여 이루어지는 것을 특징으로 한다.A semiconductor device manufacturing method for achieving the object of the present invention as described above comprises the steps of sequentially forming a pad oxide film, a nitride film and a photoresist film on top of the semiconductor substrate; Exposing and developing the photoresist film to form a photoresist pattern to expose the nitride film on the semiconductor substrate isolation region, apply the same to etch the nitride film and the pad oxide film, and then remove the photoresist pattern; Etching the exposed semiconductor substrate by applying the nitride film as a mask, and then forming an insulating film on the upper front surface, and selectively etching to form an insulating film sidewall on the etched side of the semiconductor substrate; After isotropically etching the etched bottom surface of the semiconductor substrate, the first oxide film is grown on the isotropically etched region of the semiconductor substrate, the sidewalls of the insulating film are removed, and the second oxide film is deposited to the top of the nitride film to etch the semiconductor substrate. Filling the filled areas; Planarizing the oxide film by chemical mechanical polishing, removing the nitride film and the pad oxide film to planarize the surface of the semiconductor substrate, performing well ion implantation and channel ion implantation, and forming a gate oxide film on the upper surface of the semiconductor substrate; Forming a source / drain region by forming polysilicon on the gate oxide layer, patterning the gate, and implanting impurity ions into the active region of the semiconductor substrate where the gate is not formed. do.
상기한 바와같은 본 발명에 의한 반도체소자의 제조방법을 첨부한 도2a 내지 도2j에 도시한 수순단면도를 일 실시예로 하여 상세히 설명하면 다음과 같다.Referring to the cross-sectional view shown in Figure 2a to 2j attached to the method for manufacturing a semiconductor device according to the present invention as an embodiment in detail as follows.
먼저, 도2a에 도시한 바와같이 반도체기판(11)의 상부에 패드산화막(12)을 형성하고, 질화막(13)을 증착한 다음 질화막(13)의 상부에 감광막(PR11)을 도포하고, 노광 및 현상하여 감광막(PR11) 패턴을 형성한다. 이때, 감광막(PR11) 패턴은 반도체기판(11)의 격리영역에 해당하는 질화막(13)이 노출되도록 형성한다.First, as shown in FIG. 2A, the pad oxide film 12 is formed on the semiconductor substrate 11, the nitride film 13 is deposited, and then the photoresist film PR11 is coated on the nitride film 13, followed by exposure. And developing to form the photoresist film PR11 pattern. In this case, the photoresist film PR11 pattern is formed so that the nitride film 13 corresponding to the isolation region of the semiconductor substrate 11 is exposed.
그리고, 도2b에 도시한 바와같이 상기 감광막(PR11) 패턴을 적용하여 질화막(13)과 패드산화막(12)을 식각한 후, 감광막(PR11) 패턴을 제거한다.As illustrated in FIG. 2B, the nitride film 13 and the pad oxide film 12 are etched by applying the photosensitive film PR11 pattern, and then the photosensitive film PR11 pattern is removed.
그리고, 도2c에 도시한 바와같이 상기 질화막(13)을 마스크로 적용하여 노출된 반도체기판(11)을 식각함으로써, PGI 영역(14)을 형성한다. 이때, PGI 영역(14)은 종래에 비해 깊이가 얕게 형성하는 것이 바람직하다.As shown in FIG. 2C, the PGI region 14 is formed by etching the exposed semiconductor substrate 11 by applying the nitride film 13 as a mask. At this time, the PGI region 14 is preferably formed to have a shallower depth than the conventional one.
그리고, 도2d에 도시한 바와같이 상기 PGI 영역(14)이 형성된 구조물의 상부전면에 절연막(15)을 형성하고, 선택적으로 식각하여 반도체기판(11)의 식각된 측면에 절연막(15) 측벽을 형성한다. 이때, 절연막(15)은 산화막을 형성한 후, 마스크 없이 산화막을 선택적으로 식각하여 절연막(15) 측벽을 형성할 수 있으며, 다른 방법으로 산화막을 얇게 형성한 후, 질화막을 증착하고 질화막을 마스크를 사용하거나 또는 사용하지 않고 식각하여 절연막(15) 측벽을 형성할 수 있다.As shown in FIG. 2D, an insulating film 15 is formed on the upper surface of the structure on which the PGI region 14 is formed, and selectively etched to form sidewalls of the insulating film 15 on the etched side of the semiconductor substrate 11. Form. At this time, the insulating film 15 may form an oxide film and then selectively etch the oxide film without a mask to form sidewalls of the insulating film 15. Alternatively, after forming the oxide film thinly, a nitride film is deposited and the nitride film is masked. The sidewall of the insulating film 15 may be formed by etching with or without using.
그리고, 도2e에 도시한 바와같이 상기 반도체기판(11)의 식각된 바닥면을 등방성 식각한 후, 반도체기판(11)의 등방성 식각된 영역에 산화막(16)을 성장시킨다. 이때, 산화막(16)은 반도체기판(11)의 표면산화를 통해 형성한다.As shown in FIG. 2E, the etched bottom surface of the semiconductor substrate 11 is isotropically etched, and then an oxide film 16 is grown on the isotropically etched region of the semiconductor substrate 11. At this time, the oxide film 16 is formed through surface oxidation of the semiconductor substrate 11.
그리고, 도2f에 도시한 바와같이 상기 절연막(15) 측벽을 제거하고, 산화막(16)이 형성된 구조물 상에 산화막(17)을 상기 질화막(13)의 상부까지 증착하여 반도체기판(11)의 식각된 영역을 채운다. 이때, 상기 반도체기판(11)의 표면산화를 통한 산화막(16)을 형성하지 않고, 산화막(17)을 질화막(13)의 상부까지 증착하여 반도체기판(11)의 식각된 영역을 모두 채울 수 있다.As shown in FIG. 2F, the sidewalls of the insulating film 15 are removed, and the oxide film 17 is deposited on the structure of the oxide film 16 to the upper portion of the nitride film 13 to etch the semiconductor substrate 11. The filled area. In this case, the oxide layer 16 may be deposited to the upper portion of the nitride layer 13 without filling the oxide layer 16 through surface oxidation of the semiconductor substrate 11 to fill all of the etched regions of the semiconductor substrate 11. .
그리고, 도2g에 도시한 바와같이 상기 산화막(17)을 질화막(13)이 노출될때까지 화학기계적 연마하여 평탄화한다.As shown in FIG. 2G, the oxide film 17 is chemically polished and planarized until the nitride film 13 is exposed.
그리고, 도2h에 도시한 바와같이 상기 질화막(13)과 패드산화막(12)을 제거하여 반도체기판(11)의 표면을 평탄화한 후, 반도체기판(11) 내에 웰 이온주입 및 채널 이온주입(미도시)을 실시하고, 상부전면에 게이트산화막(18)을 형성한다.2H, the nitride film 13 and the pad oxide film 12 are removed to planarize the surface of the semiconductor substrate 11, and well ion implantation and channel ion implantation are performed in the semiconductor substrate 11 (not shown). ) And a gate oxide film 18 is formed on the entire upper surface.
그리고, 도2i에 도시한 바와같이 상기 게이트산화막(18)의 상부에 폴리실리콘(19)을 형성하고, 패터닝하여 게이트를 형성한다.As shown in FIG. 2I, a polysilicon 19 is formed on the gate oxide film 18 and patterned to form a gate.
그리고, 도2j에 도시한 바와같이 상기 폴리실리콘(19)이 패터닝되지 않은 반도체기판(11)의 액티브영역 내에 불순물이온을 주입하여 소스/드레인 영역(20)을 형성한다.As shown in FIG. 2J, impurity ions are implanted into the active region of the semiconductor substrate 11 where the polysilicon 19 is not patterned to form a source / drain region 20.
상기한 바와같은 본 발명에 의한 반도체소자의 제조방법은 PGI 영역의 하부에 등방성 식각을 통해 산화막을 형성함에 따라 소스/드레인 영역과 반도체기판의 경계면을 최소화하여 소스/드레인 영역의 누설전류를 감소시킴과 아울러 소자간의 격리 신뢰성을 향상시키는 효과가 있고, 이에 따라 디램이나 에스램 셀의 데이터 보존 시간을 증가시킬 수 있게 되어 메모리셀의 신뢰성을 향상시킬 수 있을 뿐만 아니라 동일한 특성에 대한 메모리셀의 크기를 감소시킬 수 있는 효과가 있다.The method of manufacturing a semiconductor device according to the present invention as described above reduces the leakage current of the source / drain region by minimizing the interface between the source / drain region and the semiconductor substrate by forming an oxide film through isotropic etching under the PGI region. In addition, there is an effect of improving the isolation reliability between devices, thereby increasing the data retention time of the DRAM or SRAM cell, thereby improving the reliability of the memory cell, and increasing the size of the memory cell with the same characteristics. There is an effect that can be reduced.
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| KR20030053553A (en) * | 2001-12-22 | 2003-07-02 | 주식회사 하이닉스반도체 | Method for forming trench isolation in semiconductor device |
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| US4654958A (en) * | 1985-02-11 | 1987-04-07 | Intel Corporation | Process for forming isolated silicon regions and field-effect devices on a silicon substrate |
| KR100198620B1 (en) * | 1995-12-27 | 1999-06-15 | 구본준 | Manufacturing method of isolation film using trench |
| US5972758A (en) * | 1997-12-04 | 1999-10-26 | Intel Corporation | Pedestal isolated junction structure and method of manufacture |
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