KR20030053553A - Method for forming trench isolation in semiconductor device - Google Patents
Method for forming trench isolation in semiconductor device Download PDFInfo
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- KR20030053553A KR20030053553A KR1020010083306A KR20010083306A KR20030053553A KR 20030053553 A KR20030053553 A KR 20030053553A KR 1020010083306 A KR1020010083306 A KR 1020010083306A KR 20010083306 A KR20010083306 A KR 20010083306A KR 20030053553 A KR20030053553 A KR 20030053553A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000002955 isolation Methods 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title claims description 21
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 150000004767 nitrides Chemical class 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 13
- 125000006850 spacer group Chemical group 0.000 claims abstract description 9
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 238000000926 separation method Methods 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- 230000000694 effects Effects 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
- H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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Abstract
Description
본 발명은 반도체 소자의 소자분리 방법에 관한 것으로, 보다 상세하게는 누설전류의 발생을 방지하는 반도체 소자의 소자분리 방법에 관한 것이다.The present invention relates to a device isolation method of a semiconductor device, and more particularly to a device isolation method of a semiconductor device for preventing the generation of leakage current.
일반적으로, 실리콘 웨이퍼에 형성되는 반도체 소자는 개개의 회로 패턴들을전기적으로 분리하기 위한 소자 분리 영역을 포함한다. 특히 반도체 소자가 고집적화 되고 미세화 되어감에 따라 각 개별 소자의 크기를 축소시키는 것뿐만 아니라 소자 분리 영역의 축소에 대한 연구가 활발히 진행되고 있다.Generally, semiconductor devices formed on silicon wafers include device isolation regions for electrically separating individual circuit patterns. In particular, as semiconductor devices become highly integrated and miniaturized, research on not only the size of each individual device is reduced but also the device isolation region is being actively conducted.
고집적화된 반도체 장치의 소자 분리에 적합한 기술로는 트렌치를 이용한 소자분리방법, 예컨대 섈로우 트렌치 분리방법(Shallow Trench Isolation: 이하, STI)이 제안되었다.As a technique suitable for device isolation of highly integrated semiconductor devices, a device isolation method using trenches, such as a shallow trench isolation method (STI), has been proposed.
이하, 종래 기술에 따른 반도체 소자의 소자분리 방법을 첨부된 도면을 참조하여 설명하도록 한다.Hereinafter, a device isolation method of a semiconductor device according to the prior art will be described with reference to the accompanying drawings.
도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자의 소자분리 방법을 설명하기 위한 공정별 단면도이다.1A to 1D are cross-sectional views of processes for describing a device isolation method of a semiconductor device according to the prior art.
종래 기술에 따른 반도체 소자의 소자분리 방법은, 도 1a에 도시된 바와 같이, 실리콘 기판(1)상에 패드 산화막(3) 및 패드 질화막(5)을 형성한 후, 포토리소그래피 공정기술을 이용한 마스크 공정 및 식각 공정으로 상기 패드 질화막(5), 패드 산화막(3) 및 실리콘 기판(1)을 선택적으로 제거하여 소자 분리용 트렌치(6)를 형성한다. 다음으로, 상기 트렌치(6)를 포함한 실리콘 기판(1) 전면상에 트렌치 매립용 산화막(7)을 형성한다.In a device isolation method of a semiconductor device according to the prior art, as shown in FIG. 1A, after forming a pad oxide film 3 and a pad nitride film 5 on a silicon substrate 1, a mask using a photolithography process technology The pad nitride film 5, the pad oxide film 3, and the silicon substrate 1 are selectively removed by a process and an etching process to form a trench 6 for device isolation. Next, an oxide film 7 for filling trenches is formed on the entire silicon substrate 1 including the trenches 6.
이어서, 도 1b에 도시된 바와 같이, 상기 트렌치 매립용 산화막(7)을 화학적 기계적 연마 공정을 통하여 평탄화된 산화막(7a)으로 형성한 후 상기 패드 질화막(5)을 제거한다.Subsequently, as shown in FIG. 1B, the trench buried oxide film 7 is formed into a planarized oxide film 7a through a chemical mechanical polishing process, and then the pad nitride film 5 is removed.
그 다음, 도 1c에 도시된 바와 같이, 상기 패드 산화막(3)까지 제거하여 상기 반도체 기판(1)내에 형성된 소자분리막(7b)을 형성하여 반도체 소자의 소자분리를 완성한다.Then, as shown in FIG. 1C, the pad oxide film 3 is removed to form a device isolation film 7b formed in the semiconductor substrate 1 to complete device isolation of the semiconductor device.
그러나, 종래 기술에 따른 반도체 소자의 소자분리 방법에 있어서는 다음과 같은 문제점이 있다.However, the device separation method of the semiconductor device according to the prior art has the following problems.
종래 기술에 있어서는 트렌치 하부의 모서리부로 전하가 집중되므로써 반도체 소자의 전기적 특성이 악화되고, 또한 트렌치 식각시 발생된 데미지 레이어(damage layer)와 기판 사이에서 누설전류(leakage current)가 증대하게 된다. 따라서, 반도체 소자의 신뢰성 및 전기적 특성이 악화되는 현상이 발생한다는 문제점이 있다.In the prior art, the electrical charge of the semiconductor device is deteriorated due to the concentration of charges at the corners of the lower portion of the trench, and the leakage current between the damage layer and the substrate generated during the trench etching is increased. Therefore, there is a problem that a phenomenon that the reliability and electrical characteristics of the semiconductor device deteriorates.
이에, 본 발명은 상기 종래 기술의 제반 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 목적은 트렌치 하부를 열공정으로 산화시켜 액티브 영역을 기판과 단절시키고 산화막을 증착함으로써 누설전류를 최소화하여 소자의 신뢰성 및 전기적 특성을 향상시키는 반도체 소자의 소자분리 방법을 제공함에 있다.Accordingly, the present invention has been made to solve the above problems of the prior art, the object of the present invention is to oxidize the lower portion of the trench by a thermal process to disconnect the active region from the substrate and deposit an oxide film to minimize the leakage current of the device It is to provide a device isolation method of a semiconductor device to improve the reliability and electrical properties.
도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자의 소자분리 방법을 나타내는 공정별 단면도.1A to 1C are cross-sectional views illustrating a device isolation method of a semiconductor device according to the related art.
도 2a 내지 도 2e는 본 발명에 따른 반도체 소자의 소자분리 방법을 나타내는 공정별 단면도.2A to 2E are cross-sectional views illustrating processes of device isolation of a semiconductor device in accordance with the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
10: 실리콘 기판20: 질화막10 silicon substrate 20 nitride film
30: 트렌치40,40a; 스페이서30: trench 40,40a; Spacer
50: 공동부60: 산화막50: cavity 60: oxide film
70: 절연막70: insulating film
상기 목적을 달성하기 위한 반도체 소자의 소자분리 방법은, 반도체 기판상에 질화막을 형성한 후 상기 질화막과 반도체 기판을 선택적으로 패터닝하여 상기 반도체 기판내에 트렌치를 형성하는 단계; 상기 트렌치 내부에 스페이서를 형성하는 단계; 상기 트렌치 하면의 반도체 기판 표면이 노출되도록 전면 식각으로 상기 스페이서를 일부 제거하는 단계; 상기 노출된 반도체 기판 표면을 등방성 식각하여공동부를 형성하는 단계; 상기 공동부를 열공정으로 산화시켜 산화막을 형성하는 단계; 및 상기 트렌치를 매립하는 절연막을 형성하는 단계를 포함하는 것을 특징으로 한다.A device isolation method of a semiconductor device for achieving the above object comprises: forming a trench in the semiconductor substrate by selectively patterning the nitride film and the semiconductor substrate after forming a nitride film on the semiconductor substrate; Forming a spacer in the trench; Partially removing the spacers by front side etching to expose a surface of the semiconductor substrate under the trench; Isotropically etching the exposed surface of the semiconductor substrate to form a cavity; Oxidizing the cavity by a thermal process to form an oxide film; And forming an insulating film filling the trench.
이하, 본 발명에 따른 반도체 소자의 소자분리 방법을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, a device isolation method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 따른 반도체 소자의 소자분리 방법을 나타내는 공정별 단면도이다.2A to 2E are cross-sectional views illustrating processes of device isolation of a semiconductor device according to the present invention.
본 발명에 따른 반도체 소자의 소자분리 방법은, 도 2a에 도시된 바와 같이, 먼저 반도체, 예를들어, 실리콘으로 구성된 기판(10)상에 질화막(20)을 약 500 내지 3,000Å 두께로 형성한다, 그다음, 상기 질화막(20)을 마스크로 상기 실리콘 기판(10)을 선택적으로 식각하여 트렌치(30)를 형성한다.In the device isolation method of the semiconductor device according to the present invention, as shown in FIG. 2A, first, the nitride film 20 is formed to a thickness of about 500 to 3,000 실리콘 on a substrate 10 made of a semiconductor, eg, silicon. Next, the trench 30 is formed by selectively etching the silicon substrate 10 using the nitride film 20 as a mask.
이어서, 도 2b에 도시된 바와 같이, 산화막이나 질화막을 상기 트렌치(30)를 매립할 정도로 충분히 상기 실리콘 기판(10)상에 증착한 다음, 상기 증착된 산화막이나 질화막을 상기 실리콘 기판(10)의 표면을 노출되도록 전면 식각하여 얇은 두께, 약 50 내지 300Å 두께의 스페이서(40a)를 형성한다.Subsequently, as illustrated in FIG. 2B, an oxide film or a nitride film is deposited on the silicon substrate 10 sufficiently to fill the trench 30, and then the deposited oxide film or nitride film is deposited on the silicon substrate 10. The entire surface is etched to expose the surface to form a spacer 40a having a thin thickness and a thickness of about 50 to about 300 microns.
이때, 상기 전면 식각시 식각제로는 CHF3, CF4, 또는 Ar을 사용한다.In this case, CHF 3 , CF 4 , or Ar is used as the etchant during the front side etching.
이어서, 도 2c에 도시된 바와 같이, 상기 실리콘 기판(10) 표면이 노출된 상기 트렌치(30) 하면부를 제거하여 소정의 형태를 지닌 공동부(50)를 형성한다. 이때, 상기 공동부(50)를 형성하는 단계는 상기 스페이서(40a)인 산화막이나 질화막에 비해 기판(10) 재료인 실리콘의 식각속도가 우수한 식각제, 예를들면, SF6, NF3, CF4, 또는 Cl2를 사용한다.Subsequently, as shown in FIG. 2C, the bottom surface of the trench 30 exposed on the surface of the silicon substrate 10 is removed to form a cavity 50 having a predetermined shape. In this case, the forming of the cavity 50 may include an etchant having an excellent etching rate of silicon, which is a material of the substrate 10, compared to the oxide film or nitride film, which is the spacer 40a, for example, SF 6 , NF 3 , CF 4 , or Cl 2 is used.
그다음, 도 2d에 도시된 바와 같이, 상기 공동부(50)를 열공정으로 산화막(60)이 형성되도록 산화시킨다. 상기 공동부(50)에 형성된 산화막(60)은 액티브 영역을 상기 기판(10)과 분리시키는 역할을 하며, SOI (silicon on insulator)와 유사한 구조로 된다.Next, as shown in FIG. 2D, the cavity 50 is oxidized to form an oxide film 60 by a thermal process. The oxide layer 60 formed in the cavity 50 serves to separate the active region from the substrate 10 and has a structure similar to that of a silicon on insulator (SOI).
이때, 상기 공동부(50)를 열공정으로 산화시킬 때의 온도는 약 700 내지 1,500℃ 정도로 한다.At this time, the temperature when the cavity 50 is oxidized in a thermal process is about 700 to 1,500 ℃.
마지막으로, 도 2e에 도시된 바와 같이, 절연막(70)으로 상기 트렌치(30)를 매립하여 소자분리를 완성한다.Finally, as shown in FIG. 2E, the trench 30 is filled with the insulating film 70 to complete device isolation.
본 발명의 원리와 정신에 위배되지 않는 범위에서 여러 실시예는 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명할 뿐만 아니라 용이하게 실시할 수 있다. 따라서, 본원에 첨부된 특허청구범위는 이미 상술된 것에 한정되지 않으며, 하기 특허청구범위는 당해 발명에 내재되어 있는 특허성 있는 신규한 모든 사항을 포함하며, 아울러 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해서 균등하게 처리되는 모든 특징을 포함한다.Various embodiments can be easily implemented as well as self-explanatory to those skilled in the art without departing from the principles and spirit of the present invention. Accordingly, the claims appended hereto are not limited to those already described above, and the following claims are intended to cover all of the novel and patented matters inherent in the invention, and are also common in the art to which the invention pertains. Includes all features that are processed evenly by the knowledgeable.
이상에서 살펴본 바와 같이, 본 발명에 따른 반도체 소자의 소자분리 방법에 있어서는 다음과 같은 효과가 있다.As described above, the device isolation method of the semiconductor device according to the present invention has the following effects.
본 발명에 있어서는, 트렌치 하부를 등방성 식각 및 열공정으로 산화막 성장시켜 트렌치 하부의 모서리부와, 트렌치 표면의 데미지 레이어(damage layer)와 기판 사이에서 누설전류가 과다하게 발생하는 것을 방지할 수 있다. 따라서, 소자의 신뢰성과 전기적 특성을 개선시키는 효과가 있으며, 부가적으로 고가의 SOI 웨이퍼와 유사한 효과를 얻을 수 있다.In the present invention, an oxide film is grown by isotropic etching and thermal processes to prevent the occurrence of excessive leakage current between the edge portion of the trench, the damage layer on the trench surface, and the substrate. Therefore, there is an effect of improving the reliability and electrical properties of the device, and can additionally obtain an effect similar to the expensive SOI wafer.
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| KR20000075069A (en) * | 1999-05-28 | 2000-12-15 | 김영환 | Fabricating method of semiconductor device |
| KR20010035661A (en) * | 1999-10-01 | 2001-05-07 | 김영환 | A method of fabricating semiconductor devices |
| KR20010081253A (en) * | 2000-02-11 | 2001-08-29 | 박종섭 | Transistor forming method |
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| KR20000075069A (en) * | 1999-05-28 | 2000-12-15 | 김영환 | Fabricating method of semiconductor device |
| KR20010035661A (en) * | 1999-10-01 | 2001-05-07 | 김영환 | A method of fabricating semiconductor devices |
| KR20010081253A (en) * | 2000-02-11 | 2001-08-29 | 박종섭 | Transistor forming method |
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