KR20000066735A - Fabricating method of semiconductor device - Google Patents
Fabricating method of semiconductor device Download PDFInfo
- Publication number
- KR20000066735A KR20000066735A KR1019990014038A KR19990014038A KR20000066735A KR 20000066735 A KR20000066735 A KR 20000066735A KR 1019990014038 A KR1019990014038 A KR 1019990014038A KR 19990014038 A KR19990014038 A KR 19990014038A KR 20000066735 A KR20000066735 A KR 20000066735A
- Authority
- KR
- South Korea
- Prior art keywords
- wsix
- film
- polysilicon
- semiconductor device
- gate
- Prior art date
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Classifications
-
- E—FIXED CONSTRUCTIONS
- E06—DOORS, WINDOWS, SHUTTERS, OR ROLLER BLINDS IN GENERAL; LADDERS
- E06B—FIXED OR MOVABLE CLOSURES FOR OPENINGS IN BUILDINGS, VEHICLES, FENCES OR LIKE ENCLOSURES IN GENERAL, e.g. DOORS, WINDOWS, BLINDS, GATES
- E06B3/00—Window sashes, door leaves, or like elements for closing wall or like openings; Layout of fixed or moving closures, e.g. windows in wall or like openings; Features of rigidly-mounted outer frames relating to the mounting of wing frames
- E06B3/04—Wing frames not characterised by the manner of movement
- E06B3/263—Frames with special provision for insulation
- E06B3/267—Frames with special provision for insulation with insulating elements formed in situ
- E06B3/2675—Frames with special provision for insulation with insulating elements formed in situ combined with prefabricated insulating elements
-
- E—FIXED CONSTRUCTIONS
- E06—DOORS, WINDOWS, SHUTTERS, OR ROLLER BLINDS IN GENERAL; LADDERS
- E06B—FIXED OR MOVABLE CLOSURES FOR OPENINGS IN BUILDINGS, VEHICLES, FENCES OR LIKE ENCLOSURES IN GENERAL, e.g. DOORS, WINDOWS, BLINDS, GATES
- E06B3/00—Window sashes, door leaves, or like elements for closing wall or like openings; Layout of fixed or moving closures, e.g. windows in wall or like openings; Features of rigidly-mounted outer frames relating to the mounting of wing frames
- E06B3/04—Wing frames not characterised by the manner of movement
- E06B3/263—Frames with special provision for insulation
- E06B3/26347—Frames with special provision for insulation specially adapted for sliding doors or windows
-
- E—FIXED CONSTRUCTIONS
- E06—DOORS, WINDOWS, SHUTTERS, OR ROLLER BLINDS IN GENERAL; LADDERS
- E06B—FIXED OR MOVABLE CLOSURES FOR OPENINGS IN BUILDINGS, VEHICLES, FENCES OR LIKE ENCLOSURES IN GENERAL, e.g. DOORS, WINDOWS, BLINDS, GATES
- E06B3/00—Window sashes, door leaves, or like elements for closing wall or like openings; Layout of fixed or moving closures, e.g. windows in wall or like openings; Features of rigidly-mounted outer frames relating to the mounting of wing frames
- E06B3/30—Coverings, e.g. protecting against weather, for decorative purposes
- E06B3/301—Coverings, e.g. protecting against weather, for decorative purposes consisting of prefabricated profiled members or glass
- E06B3/305—Covering metal frames with plastic or metal profiled members
-
- E—FIXED CONSTRUCTIONS
- E06—DOORS, WINDOWS, SHUTTERS, OR ROLLER BLINDS IN GENERAL; LADDERS
- E06B—FIXED OR MOVABLE CLOSURES FOR OPENINGS IN BUILDINGS, VEHICLES, FENCES OR LIKE ENCLOSURES IN GENERAL, e.g. DOORS, WINDOWS, BLINDS, GATES
- E06B3/00—Window sashes, door leaves, or like elements for closing wall or like openings; Layout of fixed or moving closures, e.g. windows in wall or like openings; Features of rigidly-mounted outer frames relating to the mounting of wing frames
- E06B3/30—Coverings, e.g. protecting against weather, for decorative purposes
- E06B3/301—Coverings, e.g. protecting against weather, for decorative purposes consisting of prefabricated profiled members or glass
- E06B3/307—Coverings with special provisions for insulation, e.g. foam filled
Landscapes
- Engineering & Computer Science (AREA)
- Civil Engineering (AREA)
- Structural Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 반도체소자의 게이트 또는 배선에 적용되는 WSix막의 산화를 방지하여 게이트 또는 배선의 신뢰성을 향상시키기에 적당하도록 한 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device suitable for improving the reliability of a gate or wiring by preventing oxidation of a WSix film applied to a gate or wiring of the semiconductor device.
종래 반도체소자의 제조방법은 도1a의 단면도에 도시한 바와같이 소자(미도시)가 형성된 반도체기판(1) 상에 폴리실리콘(2)을 형성한 후, 그 폴리실리콘(2)의 상부에 접착력을 강화시키기 위하여 실리콘(Si)이 풍부하게 함유된 제1WSix막(3)을 형성하고, 그 제1WSix막(3)의 상부에 저항값을 감소시키기 위하여 텅스텐(W)이 풍부하게 함유된 제2WSix막(4)의 주배선층을 형성한 다음 그 제2WSix막(4)의 상부에 다시 스트레스를 줄이기 위하여 실리콘(Si)이 풍부하게 함유된 제3WSix막(5)을 형성한다.In the conventional method of manufacturing a semiconductor device, as shown in the cross-sectional view of FIG. 1A, after the polysilicon 2 is formed on a semiconductor substrate 1 on which an element (not shown) is formed, an adhesive force is formed on the polysilicon 2. To form a first WSix film 3 rich in silicon (Si), and to increase the resistance value on top of the first WSix film 3, the second WSix rich in tungsten (W); After the main wiring layer of the film 4 is formed, a third WSix film 5 rich in silicon (Si) is formed on the second WSix film 4 to reduce stress again.
이때, 상기 제1 내지 제3WSix막(3∼5)은 폴리실리콘(2)의 상부에 화학기상증착법 또는 물리적 기상증착법을 통해 형성한다.In this case, the first to third WSix films 3 to 5 are formed on the polysilicon 2 through chemical vapor deposition or physical vapor deposition.
이후에, 상기한 바와같은 폴리실리콘(2) 및 제1 내지 제3WSix막(3∼5)의 적층 구조물을 사진식각공정을 통해 패터닝한 후, 열처리를 실시하여 제1 내지 제3WSix막(3∼5)의 저항값을 감소시키고, 안정성을 향상시켜 최종적인 게이트 또는 배선을 형성한다.Subsequently, the laminated structure of the polysilicon 2 and the first to third WSix films 3 to 5 as described above is patterned through a photolithography process, followed by heat treatment to form the first to third WSix films (3 to 3). Reduce the resistance of 5) and improve the stability to form the final gate or wiring.
그러나, 상기한 바와같은 종래 반도체소자의 제조방법은 저항값 감소 및 안정성 향상을 위해 열처리를 실시할 때, 도1b의 단면도에 도시한 바와같이 노출된 제3WSix막(5)이 산소와 결합하여 WO3또는 SiO2(6)로 산화됨에 따라 게이트 또는 배선의 단락이 발생하거나, 제1 내지 제3WSix막(3∼5)이 박리(peel-off)되어 반도체소자의 신뢰성을 저하시키는 문제점이 있었다.However, in the method of manufacturing a conventional semiconductor device as described above, when the heat treatment is performed to reduce the resistance value and improve the stability, the exposed third WSix film 5 as shown in the cross-sectional view of FIG. As the oxide is oxidized to 3 or SiO 2 (6), a short circuit occurs in the gate or the wiring, or the first to third WSix films 3 to 5 are peeled off, thereby reducing the reliability of the semiconductor device.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 반도체소자의 게이트 또는 배선에 적용되는 WSix막의 열처리에 의한 산화를 방지하여 게이트 또는 배선의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to prevent oxidation by heat treatment of a WSix film applied to a gate or wiring of a semiconductor device, thereby improving reliability of the gate or wiring. The present invention provides a method for manufacturing a semiconductor device.
도1a는 종래 반도체소자의 제조방법을 통해 형성된 게이트 또는 배선을 간략하게 보인 단면도.Figure 1a is a cross-sectional view showing a simplified view of the gate or wiring formed through a conventional method for manufacturing a semiconductor device.
도1b는 도1a에 있어서, 게이트 또는 배선을 형성한 후, 열처리공정에 의해 제3WSix막이 산화되는 것을 보인 예시도.FIG. 1B is an exemplary view showing that in FIG. 1A, after forming a gate or a wiring, the third WSix film is oxidized by a heat treatment step.
도2는 본 발명의 일 실시예를 보인 단면도.Figure 2 is a cross-sectional view showing an embodiment of the present invention.
***도면의 주요부분에 대한 부호의 설명****** Explanation of symbols for main parts of drawing ***
11:반도체기판 12:폴리실리콘11: semiconductor substrate 12: polysilicon
13∼15:제1 내지 제3WSix막 16:WSixNy막13-15: 1st-3rd WSix film 16: WSixNy film
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자의 제조방법은 소자가 형성된 반도체기판 상에 폴리실리콘을 형성하는 공정과; 상기 폴리실리콘의 상부에 다층으로 적층된 WSix막을 형성하는 공정과; 상기 WSix막의 상부에 WxSiyNz 구조의 질화막을 형성하는 공정과; 상기 질화막, WSix막 및 폴리실리콘을 패터닝한 후, 열처리하여 게이트 또는 배선을 형성하는 공정을 구비하여 이루어지는 것을 특징으로 한다.A semiconductor device manufacturing method for achieving the object of the present invention as described above comprises the steps of forming polysilicon on a semiconductor substrate on which the device is formed; Forming a WSix film laminated in multiple layers on top of the polysilicon; Forming a nitride film having a WxSiyNz structure on top of the WSix film; And patterning the nitride film, the WSix film, and the polysilicon, followed by heat treatment to form a gate or wiring.
상기한 바와같은 본 발명에 의한 반도체소자의 제조방법은 도2의 단면도에 도시한 바와같이 소자(미도시)가 형성된 반도체기판(11) 상에 폴리실리콘(12)을 형성한 후, 그 폴리실리콘(12)의 상부에 접착력을 강화시키기 위하여 실리콘(Si)이 풍부하게 함유된 제1WSix막(13)을 형성하고, 그 제1WSix막(13)의 상부에 저항값을 감소시키기 위하여 텅스텐(W)이 풍부하게 함유된 제2WSix막(14)의 주배선층을 형성한 다음 그 제2WSix막(14)의 상부에 다시 스트레스를 줄이기 위하여 실리콘(Si)이 풍부하게 함유된 제3WSix막(15)을 형성한다.In the method of manufacturing a semiconductor device according to the present invention as described above, the polysilicon 12 is formed on a semiconductor substrate 11 on which an element (not shown) is formed, as shown in the cross-sectional view of FIG. A first WSix film 13 containing abundant silicon (Si) is formed in order to enhance adhesion to the top of the 12, and tungsten (W) in order to reduce the resistance value on the first WSix film 13. After forming the main wiring layer of the richly contained second WSix film 14, the third WSix film 15 rich in silicon (Si) is formed on the second WSix film 14 to reduce stress again. do.
계속해서, 반응용기 내에서 고온으로 질소이온을 주입하거나 질소 플라즈마처리를 실시하거나 또는 WxSiyNx막을 스퍼터링방법을 통해 증착하여 상기 제3WSix막(15)을 WSixNy막(16)으로 감싸도록 한다.Subsequently, nitrogen ions are injected into the reaction vessel at a high temperature, a nitrogen plasma treatment is performed, or a WxSiyNx film is deposited through a sputtering method to surround the third WSix film 15 with the WSixNy film 16.
이때, 상기 제1 내지 제3WSix막(13∼15)은 폴리실리콘(12)의 상부에 화학기상증착법 또는 물리적 기상증착법을 통해 형성한다.In this case, the first to third WSix films 13 to 15 are formed on the polysilicon 12 by chemical vapor deposition or physical vapor deposition.
이후에, 상기한 바와같은 폴리실리콘(12), 제1 내지 제3WSix막(13∼15) 및 WSixNy막(16)의 적층 구조물을 사진식각공정을 통해 패터닝한 후, 열처리를 실시하여 제1 내지 제3WSix막(13∼15)의 저항값을 감소시키고, 안정성을 향상시켜 최종적인 게이트 또는 배선을 형성한다.Subsequently, the laminated structure of the polysilicon 12, the first to third WSix films 13 to 15, and the WSixNy film 16 as described above is patterned through a photolithography process, and then subjected to a heat treatment to perform the first to third processing. The resistance value of the third WSix films 13 to 15 is reduced, and the stability is improved to form a final gate or wiring.
상기한 바와같은 본 발명에 의한 반도체소자의 제조방법은 WxSiyNz 구조의 질화막을 WSix막의 표면에 형성하여 후속 고온공정에서 WSix막의 산화를 방지함에 따라 게이트 또는 배선의 신뢰성을 향상시킬 수 있는 효과가 있다.The method for manufacturing a semiconductor device according to the present invention as described above has the effect of improving the reliability of the gate or wiring by forming a nitride film having a WxSiyNz structure on the surface of the WSix film to prevent oxidation of the WSix film in a subsequent high temperature process.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990014038A KR20000066735A (en) | 1999-04-20 | 1999-04-20 | Fabricating method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990014038A KR20000066735A (en) | 1999-04-20 | 1999-04-20 | Fabricating method of semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR20000066735A true KR20000066735A (en) | 2000-11-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019990014038A KR20000066735A (en) | 1999-04-20 | 1999-04-20 | Fabricating method of semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100456316B1 (en) * | 2002-06-29 | 2004-11-10 | 주식회사 하이닉스반도체 | Method for forming gate in semiconductor device |
-
1999
- 1999-04-20 KR KR1019990014038A patent/KR20000066735A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100456316B1 (en) * | 2002-06-29 | 2004-11-10 | 주식회사 하이닉스반도체 | Method for forming gate in semiconductor device |
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