KR20000043049A - Semiconductor devices - Google Patents
Semiconductor devices Download PDFInfo
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- KR20000043049A KR20000043049A KR1019980059352A KR19980059352A KR20000043049A KR 20000043049 A KR20000043049 A KR 20000043049A KR 1019980059352 A KR1019980059352 A KR 1019980059352A KR 19980059352 A KR19980059352 A KR 19980059352A KR 20000043049 A KR20000043049 A KR 20000043049A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 239000012535 impurity Substances 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 claims abstract description 17
- 239000003990 capacitor Substances 0.000 claims abstract description 16
- 239000011229 interlayer Substances 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 5
- 230000000116 mitigating effect Effects 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 4
- 229910021478 group 5 element Inorganic materials 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 워드 라인(word line), 비트 라인(bit line), 캐패시터(capacitor) 전극 등과 같은 구성 요소를 갖는 반도체 소자의 제조 공정시 공정의 개선을 통해 배선간 절연에 대한 신뢰도를 높이면서, 공정의 단순화를 이루어 제품 생산 시간과 장비 소요를 줄일 수 있는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to improve wiring in a manufacturing process of a semiconductor device having components such as word lines, bit lines, and capacitor electrodes. The present invention relates to a method for manufacturing a semiconductor device that can simplify the process and reduce the production time and equipment requirements by increasing the reliability of the inter-insulation.
워드 라인, 비트 라인, 캐패시터 전극 등과 같은 구성 요소를 갖는 반도체 소자를 제조하는 기존의 공정에서는 LDD(Lightly Doped Drain) 구조와 배선간의 접촉 방지를 위하여, 워드 라인, 비트 라인, 캐패시터 전극 형성을 위한 도프트 폴리실리콘(doped polysilicon) 증착 공정 전후에 측벽 산화물을 증착하고 식각 공정을 진행한다. 이로 인하여, 공정 진행 시간이 늘어나고 장비의 소요가 늘어나 제품의 생산성 저하를 초래하였으며, 배선간의 절연 불량의 양상이 나타나기도 한다. 또한, 비트 라인 및 캐패시터 전극 형성을 위한 콘택홀에서는 측벽 산화물로 인하여 콘택홀의 크기가 작아져서 그 매립에 어려움이 따르고, 콘택홀 형성시 식각 공정에서 하부의 도핑(doping)된 입자들의 손실로 인하여 현 공정에서는 콘택 저항을 낮추기 위하여 플러그 이온 주입(plug ion implantation) 공정을 진행해야하는 등 여러 가지 공정 추가로 인하여 전체 공정 시간이 늘어나고 그에 따른 장비 운용면에서도 불리한 문제가 있다.In the conventional process of manufacturing semiconductor devices having components such as word lines, bit lines, and capacitor electrodes, the dope is formed to form word lines, bit lines, and capacitor electrodes in order to prevent contact between lightly doped drain (LDD) structures and wiring. Sidewall oxides are deposited and etched before and after the doped polysilicon deposition process. As a result, process progress time increases and equipment requirements increase, resulting in a decrease in productivity of the product, and an appearance of insulation defects between wirings may appear. In addition, in the contact hole for forming the bit line and capacitor electrode, the contact hole becomes smaller due to the sidewall oxide, which causes difficulty in embedding, and the loss of the doped particles in the etching process during the contact hole formation results in loss of current. In the process, the overall process time is increased due to the addition of various processes such as a plug ion implantation process to lower the contact resistance, and there is a disadvantage in terms of equipment operation.
따라서, 본 발명은 워드 라인, 비트 라인, 캐패시터 전극 등과 같은 구성 요소를 갖는 반도체 소자의 제조 공정시 공정의 개선을 통해 배선간 절연에 대한 신뢰도를 높이면서, 공정의 단순화를 이루어 제품 생산 시간과 장비 소요를 줄일 수 있는 반도체 소자의 제조 방법을 제공함에 그 목적이 있다.Accordingly, the present invention improves the reliability of the inter-wire insulation through the improvement of the process of manufacturing a semiconductor device having components such as word lines, bit lines, capacitor electrodes, etc., while simplifying the process to improve the production time and equipment It is an object of the present invention to provide a method for manufacturing a semiconductor device, which can reduce the requirement.
이러한 목적을 달성하기 위한 본 발명이 반도체 소자의 제조 방법은 채널 영역 양측의 반도체 기판에 제 1 및 제 2 저농도 불순물 영역을 각각 형성하는 단계; 상기 채널 영역과 상기 제 1 및 제 2 저농도 불순물 영역의 일부를 제외한 나머지 제 1 및 제 2 저농도 불순물 영역 각각에 제 1 및 제 2 고농도 불순물 영역을 각각 형성하고, 이로 인하여 LDD 구조의 드레인 및 소오스가 형성되는 단계; 상기 채널 영역 상에 게이트 산화막 및 워드 라인을 형성하고, 상기 워드 라인 형성과 동시에 상기 드레인 및 소오스 각각의 일부분에 제 1 및 제 2 패드를 각각 형성하는 단계; 제 1 층간 절연막을 형성한 후, 상기 드레인 상에 형성된 상기 제 1 패드가 노출되는 제 1 콘택홀을 형성하고, 상기 제 1 콘택홀을 통해 상기 제 1 패드와 연결되는 비트 라인을 형성하는 단계; 및 제 2 층간 절연막을 형성한 후, 상기 소오스 상에 형성된 제 2 패드가 노출되는 제 2 콘택홀을 형성하고, 상기 제 2 콘택홀을 통해 상기 제 2 패드와 연결되는 캐패시터 전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including forming first and second low concentration impurity regions on a semiconductor substrate on both sides of a channel region; First and second high concentration impurity regions are formed in each of the first and second low concentration impurity regions, except for the channel region and a portion of the first and second low concentration impurity regions, so that the drain and source of the LDD structure Forming; Forming a gate oxide film and a word line on the channel region, and forming first and second pads on portions of each of the drain and the source at the same time as the word line is formed; Forming a first contact hole through which the first pad formed on the drain is exposed and forming a bit line connected to the first pad through the first contact hole after forming a first interlayer insulating film; And forming a second contact hole through which the second pad formed on the source is exposed, after forming the second interlayer insulating film, and forming a capacitor electrode connected to the second pad through the second contact hole. It is characterized by comprising.
도 1a 내지 도 1e는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위한 소자의 단면도.1A to 1E are cross-sectional views of a device for explaining a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1: 반도체 기판 2: 필드 산화막1: semiconductor substrate 2: field oxide film
3: 채널 영역 4: 드레인3: channel region 4: drain
4A: 제 1 저농도 불순물 영역 4B: 제 1 고농도 불순물 영역4A: first low concentration impurity region 4B: first high concentration impurity region
5: 소오스 5A: 제 2 저농도 불순물 영역5: source 5A: second low concentration impurity region
5B: 제 2 고농도 불순물 영역 6: 게이트 산화막5B: second high concentration impurity region 6: gate oxide film
7: 게이트 전극(워드 라인) 7A: 제 1 패드7: gate electrode (word line) 7A: first pad
7B: 제 2 패드 8: 제 1 층간 절연막7B: second pad 8: first interlayer insulating film
9A: 제 1 콘택홀 9B: 제 2 콘택홀9A: first contact hole 9B: second contact hole
11: 비트 라인 12: 제 2 층간 절연막11: bit line 12: second interlayer insulating film
13: 캐패시터 전극 21: 제 1 포토레지스트막13: Capacitor Electrode 21: First Photoresist Film
22: 제 2 포토레지스트막22: second photoresist film
이하, 본 발명을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, the present invention will be described with reference to the accompanying drawings.
도 1a 내지 도 1e는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위한 소자의 단면도이다.1A to 1E are cross-sectional views of devices for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 1a를 참조하면, 반도체 기판(1)에 필드 산화막(2)을 형성하여 액티브 영역을 정의한다. 소오스 및 드레인이 형성될 액티브 영역의 반도체 기판(1)이 개방되고 채널 영역(3)을 덮는 제 1 포토레지스트막(21)을 형성한 후, 저농도의 불순물 이온을 주입하고, 이로 인하여 제 1 저농도 불순물 영역(4A)과 제 2 저농도 불순물 영역(5A)이 반도체 기판(1)에 형성된다.Referring to FIG. 1A, a field oxide film 2 is formed on a semiconductor substrate 1 to define an active region. After the semiconductor substrate 1 of the active region in which the source and drain are to be formed is opened and the first photoresist film 21 covering the channel region 3 is formed, a low concentration of impurity ions are implanted, thereby causing the first low concentration. The impurity region 4A and the second low concentration impurity region 5A are formed in the semiconductor substrate 1.
상기에서, 제 1 및 제 2 저농도 불순물 영역(4A 및 5A)은 제 3 족, 제 5 족 또는 제 3 족과 제 5 족 원소의 화합물을 도핑시켜 형성된다.In the above, the first and second low concentration impurity regions 4A and 5A are formed by doping a compound of Group 3, Group 5 or Group 3 and Group 5 elements.
도 1b를 참조하면, 제 1 포토레지스트막(21)을 제거한 후, LDD 구조를 형성하기 위해 제 1 저농도 불순물 영역(4A)과 제 2 저농도 불순물 영역(5A)의 대부분이 개방되고 채널 영역(3) 및 채널 영역(3) 쪽의 제 1 저농도 불순물 영역(4A)과 제 2 저농도 불순물 영역(5A) 각각의 일부를 덮는 제 2 포토레지스트막(22)을 형성한다. 제 2 포토레지스트막(22)을 이온 주입 마스크로한 고농도의 불순물 이온을 주입한 후 확산 공정을 진행하고, 이로 인하여 제 1 고농도 불순물 영역(4B)이 제 1 저농도 불순물 영역(4A)에 중첩되어 LDD 구조의 드레인(4)이 형성되고, 제 2 고농도 불순물 영역(5B)이 제 2 저농도 불순물 영역(5A)에 중첩되어 LDD 구조의 소오스(5)가 형성된다.Referring to FIG. 1B, after removing the first photoresist film 21, most of the first low concentration impurity region 4A and the second low concentration impurity region 5A are opened to form the LDD structure, and the channel region 3 is removed. ) And a second photoresist film 22 covering part of each of the first low concentration impurity region 4A and the second low concentration impurity region 5A on the channel region 3 side. After implanting a high concentration of impurity ions using the second photoresist film 22 as an ion implantation mask, a diffusion process is performed, whereby the first high concentration impurity region 4B overlaps the first low concentration impurity region 4A. A drain 4 of the LDD structure is formed, and the second high concentration impurity region 5B overlaps the second low concentration impurity region 5A to form a source 5 of LDD structure.
상기에서, 제 1 및 제 2 고농도 불순물 영역(4B 및 5B)은 제 3 족, 제 5 족 또는 제 3 족과 제 5 족 원소의 화합물을 도핑시켜 형성된다.In the above, the first and second high concentration impurity regions 4B and 5B are formed by doping a compound of Group 3, Group 5 or Group 3 and Group 5 elements.
도 1c를 참조하면, 채널 영역(3) 상에 게이트 산화막(6) 및 워드 라인인 게이트 전극(7)을 형성한다. 게이트 전극(7)은 도프트 폴리실리콘을 증착한 후 패터닝 하여 형성된다. 이때 비트 라인 및 캐패시터 전극의 콘택홀이 형성될 부위인 드레인(4) 및 소오스(5) 각각의 일부분에 도프트 폴리실리콘으로 된 제 1 패드(7A) 및 제 2 패드(7B)가 동시에 개별적으로 형성된다.Referring to FIG. 1C, a gate oxide film 6 and a gate electrode 7, which is a word line, are formed on the channel region 3. The gate electrode 7 is formed by depositing doped polysilicon and patterning it. At this time, the first pad 7A and the second pad 7B made of doped polysilicon are simultaneously simultaneously disposed on portions of the drain 4 and the source 5, which are portions at which the contact holes of the bit line and the capacitor electrode are to be formed. Is formed.
상기의 공정을 통해 LDD 구조를 갖는 트랜지스터가 완성된다.Through the above process, a transistor having an LDD structure is completed.
도 1d를 참조하면, 트랜지스터가 형성된 반도체 기판(1)의 전체 구조상에 제 1 층간 절연막(8)을 형성한다. 비트 라인용 콘택홀 형성 공정으로 제 1 층간 절연막(8)의 일부분을 식각하여 제 1 패드(7A)가 노출되는 제 1 콘택홀(9A)을 형성하고, 제 1 콘택홀(9A)을 통해 제 1 패드(7A)와 연결되는 비트 라인(11)을 형성한다. 비트 라인(11)은 제 1 패드(7A)를 통해 드레인(4)에 전기적으로 연결된다.Referring to FIG. 1D, the first interlayer insulating film 8 is formed on the entire structure of the semiconductor substrate 1 on which the transistor is formed. A portion of the first interlayer insulating film 8 is etched by forming a bit line contact hole to form a first contact hole 9A through which the first pad 7A is exposed, and then through the first contact hole 9A. The bit line 11 connected to the first pad 7A is formed. The bit line 11 is electrically connected to the drain 4 through the first pad 7A.
상기에서, 제 1 콘택홀(9A)을 형성한 후, 콘택 저항을 낮추기 위해 도프트 폴리실리콘으로 된 제 1 패드(7A)에 불순물 이온 주입 공정을 실시하는 것을 포함할 수 있다. 이때, 제 1 패드(7A)에는 제 3 족, 제 5 족 또는 제 3 족과 제 5 족 원소의 화합물을 도핑 시킨다.After the first contact hole 9A is formed, an impurity ion implantation process may be performed on the first pad 7A made of doped polysilicon to lower the contact resistance. At this time, the first pad 7A is doped with a compound of Group 3, Group 5 or Group 3 and Group 5 elements.
도 1e를 참조하면, 비트 라인(11)을 포함한 제 1 층간 절연막(8)상에 제 2 층간 절연막(12)을 형성한다. 캐패시터 전극용 콘택홀 형성 공정으로 제 2 층간 절연막(12)의 일부분을 식각하여 제 2 패드(7B)가 노출되는 제 2 콘택홀(9B)을 형성하고, 제 2 콘택홀(9B)을 통해 제 2 패드(7B)와 연결되는 캐패시터 전극(13)을 형성한다. 캐패시터 전극(13)은 제 2 패드(7B)를 통해 소오스(5)에 전기적으로 연결된다.Referring to FIG. 1E, a second interlayer insulating film 12 is formed on the first interlayer insulating film 8 including the bit line 11. A part of the second interlayer insulating film 12 is etched by forming a contact hole for the capacitor electrode, thereby forming a second contact hole 9B through which the second pad 7B is exposed, and forming a second contact hole 9B through the second contact hole 9B. The capacitor electrode 13 connected to the two pads 7B is formed. The capacitor electrode 13 is electrically connected to the source 5 via the second pad 7B.
상기에서, 제 2 콘택홀(9B)을 형성한 후, 콘택 저항을 낮추기 위해 도포트 폴리실리콘으로 된 제 2 패드(7B)에 불순물 이온 주입 공정을 실시하는 것을 포함할 수 있다. 이때, 제 2 패드(7B)에는 제 3 족, 제 5 족 또는 제 3 족과 제 5 족 원소의 화합물을 도핑 시킨다.In the above, after the second contact hole 9B is formed, an impurity ion implantation process may be performed on the second pad 7B made of doped polysilicon to lower the contact resistance. At this time, the second pad 7B is doped with a compound of Group 3, Group 5 or Group 3 and Group 5 elements.
이후, 금속 배선 공정 및 보호막 형성 공정 등과 같은 기존 공정을 진행하여 반도체 소자를 제조한다.Thereafter, a semiconductor device is manufactured by performing a conventional process such as a metal wiring process and a protective film forming process.
상술한 바와 같이, 본 발명은 액티브 영역에 먼저 LDD 구조의 소오스 및 드레인을 먼저 형성하고, 소오스와 드레인 사이를 지나는 워드 라인을 형성할 때, 비트 라인 및 캐패시터 전극의 콘택홀 형성 부위에 도프트 폴리실리콘 패드를 각각 남기고, 층간 절연막을 형성한 후 콘택홀 형성 공정을 실시하여 도프트 폴리 실리콘 패드 각각이 노출되는 콘택홀을 형성하므로써, 배선간 절연에 대한 신뢰도를 높일 수 있으며, 워드 라인, 비트 라인, 캐패시터 전극 형성시 기존의 스페이서 산화막을 형성하기 위한 측벽 산화물 증착 공정 및 식각 공정 등을 생략할 수 있어 제품 생산 시간과 장비 소요를 줄일 수 있다.As described above, in the present invention, when the source and the drain of the LDD structure are first formed in the active region first, and the word line passing between the source and the drain is formed, the doped poly is formed in the contact hole forming portion of the bit line and the capacitor electrode. By leaving the silicon pads behind, forming an interlayer insulating film, and then performing a contact hole forming process to form contact holes where each of the doped polysilicon pads is exposed, reliability of inter-wire insulation can be increased, and word lines and bit lines can be improved. In addition, since the sidewall oxide deposition process and the etching process for forming a conventional spacer oxide layer may be omitted when forming the capacitor electrode, product production time and equipment requirements may be reduced.
Claims (3)
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