KR20000043049A - Semiconductor devices - Google Patents

Abstract

PURPOSE: A fabrication of the semiconductor device is provided by improving an inter-wiring dielectric through a process mitigation, when manufacturing the semiconductor device having the structures of a word line, a bit line, and a capacitor. CONSTITUTION: A fabrication method of the semiconductor device contains the following steps: a step to form the source and the drain of a lightly doped drain structure at first to the active regions having the low and high concentrations of an impurity region; a step to form a gate oxide and a word line on the channel region; a step to form the first pads to a partial sections of every drain and source when forming the word line; a step to form the bit line being connected with the first pad on the drain, after forming the first inter layer dielectric; and a step to form a capacitor electrode being connected with the second pad on the source, after forming the second inter layer dielectric.

Description

Manufacturing Method of Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to improve wiring in a manufacturing process of a semiconductor device having components such as word lines, bit lines, and capacitor electrodes. The present invention relates to a method for manufacturing a semiconductor device that can simplify the process and reduce the production time and equipment requirements by increasing the reliability of the inter-insulation.

In the conventional process of manufacturing semiconductor devices having components such as word lines, bit lines, and capacitor electrodes, the dope is formed to form word lines, bit lines, and capacitor electrodes in order to prevent contact between lightly doped drain (LDD) structures and wiring. Sidewall oxides are deposited and etched before and after the doped polysilicon deposition process. As a result, process progress time increases and equipment requirements increase, resulting in a decrease in productivity of the product, and an appearance of insulation defects between wirings may appear. In addition, in the contact hole for forming the bit line and capacitor electrode, the contact hole becomes smaller due to the sidewall oxide, which causes difficulty in embedding, and the loss of the doped particles in the etching process during the contact hole formation results in loss of current. In the process, the overall process time is increased due to the addition of various processes such as a plug ion implantation process to lower the contact resistance, and there is a disadvantage in terms of equipment operation.

Accordingly, the present invention improves the reliability of the inter-wire insulation through the improvement of the process of manufacturing a semiconductor device having components such as word lines, bit lines, capacitor electrodes, etc., while simplifying the process to improve the production time and equipment It is an object of the present invention to provide a method for manufacturing a semiconductor device, which can reduce the requirement.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including forming first and second low concentration impurity regions on a semiconductor substrate on both sides of a channel region; First and second high concentration impurity regions are formed in each of the first and second low concentration impurity regions, except for the channel region and a portion of the first and second low concentration impurity regions, so that the drain and source of the LDD structure Forming; Forming a gate oxide film and a word line on the channel region, and forming first and second pads on portions of each of the drain and the source at the same time as the word line is formed; Forming a first contact hole through which the first pad formed on the drain is exposed and forming a bit line connected to the first pad through the first contact hole after forming a first interlayer insulating film; And forming a second contact hole through which the second pad formed on the source is exposed, after forming the second interlayer insulating film, and forming a capacitor electrode connected to the second pad through the second contact hole. It is characterized by comprising.

1A to 1E are cross-sectional views of a device for explaining a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

1: semiconductor substrate 2: field oxide film

3: channel region 4: drain

4A: first low concentration impurity region 4B: first high concentration impurity region

5: source 5A: second low concentration impurity region

5B: second high concentration impurity region 6: gate oxide film

7: gate electrode (word line) 7A: first pad

7B: second pad 8: first interlayer insulating film

9A: first contact hole 9B: second contact hole

11: bit line 12: second interlayer insulating film

13: Capacitor Electrode 21: First Photoresist Film

22: second photoresist film

Hereinafter, the present invention will be described with reference to the accompanying drawings.

1A to 1E are cross-sectional views of devices for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1A, a field oxide film 2 is formed on a semiconductor substrate 1 to define an active region. After the semiconductor substrate 1 of the active region in which the source and drain are to be formed is opened and the first photoresist film 21 covering the channel region 3 is formed, a low concentration of impurity ions are implanted, thereby causing the first low concentration. The impurity region 4A and the second low concentration impurity region 5A are formed in the semiconductor substrate 1.

In the above, the first and second low concentration impurity regions 4A and 5A are formed by doping a compound of Group 3, Group 5 or Group 3 and Group 5 elements.

Referring to FIG. 1B, after removing the first photoresist film 21, most of the first low concentration impurity region 4A and the second low concentration impurity region 5A are opened to form the LDD structure, and the channel region 3 is removed. ) And a second photoresist film 22 covering part of each of the first low concentration impurity region 4A and the second low concentration impurity region 5A on the channel region 3 side. After implanting a high concentration of impurity ions using the second photoresist film 22 as an ion implantation mask, a diffusion process is performed, whereby the first high concentration impurity region 4B overlaps the first low concentration impurity region 4A. A drain 4 of the LDD structure is formed, and the second high concentration impurity region 5B overlaps the second low concentration impurity region 5A to form a source 5 of LDD structure.

In the above, the first and second high concentration impurity regions 4B and 5B are formed by doping a compound of Group 3, Group 5 or Group 3 and Group 5 elements.

Referring to FIG. 1C, a gate oxide film 6 and a gate electrode 7, which is a word line, are formed on the channel region 3. The gate electrode 7 is formed by depositing doped polysilicon and patterning it. At this time, the first pad 7A and the second pad 7B made of doped polysilicon are simultaneously simultaneously disposed on portions of the drain 4 and the source 5, which are portions at which the contact holes of the bit line and the capacitor electrode are to be formed. Is formed.

Through the above process, a transistor having an LDD structure is completed.

Referring to FIG. 1D, the first interlayer insulating film 8 is formed on the entire structure of the semiconductor substrate 1 on which the transistor is formed. A portion of the first interlayer insulating film 8 is etched by forming a bit line contact hole to form a first contact hole 9A through which the first pad 7A is exposed, and then through the first contact hole 9A. The bit line 11 connected to the first pad 7A is formed. The bit line 11 is electrically connected to the drain 4 through the first pad 7A.

After the first contact hole 9A is formed, an impurity ion implantation process may be performed on the first pad 7A made of doped polysilicon to lower the contact resistance. At this time, the first pad 7A is doped with a compound of Group 3, Group 5 or Group 3 and Group 5 elements.

Referring to FIG. 1E, a second interlayer insulating film 12 is formed on the first interlayer insulating film 8 including the bit line 11. A part of the second interlayer insulating film 12 is etched by forming a contact hole for the capacitor electrode, thereby forming a second contact hole 9B through which the second pad 7B is exposed, and forming a second contact hole 9B through the second contact hole 9B. The capacitor electrode 13 connected to the two pads 7B is formed. The capacitor electrode 13 is electrically connected to the source 5 via the second pad 7B.

In the above, after the second contact hole 9B is formed, an impurity ion implantation process may be performed on the second pad 7B made of doped polysilicon to lower the contact resistance. At this time, the second pad 7B is doped with a compound of Group 3, Group 5 or Group 3 and Group 5 elements.

Thereafter, a semiconductor device is manufactured by performing a conventional process such as a metal wiring process and a protective film forming process.

As described above, in the present invention, when the source and the drain of the LDD structure are first formed in the active region first, and the word line passing between the source and the drain is formed, the doped poly is formed in the contact hole forming portion of the bit line and the capacitor electrode. By leaving the silicon pads behind, forming an interlayer insulating film, and then performing a contact hole forming process to form contact holes where each of the doped polysilicon pads is exposed, reliability of inter-wire insulation can be increased, and word lines and bit lines can be improved. In addition, since the sidewall oxide deposition process and the etching process for forming a conventional spacer oxide layer may be omitted when forming the capacitor electrode, product production time and equipment requirements may be reduced.

Claims (3)

Forming first and second low concentration impurity regions on semiconductor substrates on both sides of the channel region, respectively; First and second high concentration impurity regions are formed in each of the first and second low concentration impurity regions, except for the channel region and a portion of the first and second low concentration impurity regions, so that the drain and source of the LDD structure Forming; Forming a gate oxide film and a word line on the channel region, and forming first and second pads on portions of each of the drain and the source at the same time as the word line is formed; Forming a first contact hole through which the first pad formed on the drain is exposed and forming a bit line connected to the first pad through the first contact hole after forming a first interlayer insulating film; And After forming a second insulating interlayer, forming a second contact hole through which the second pad formed on the source is exposed, and forming a capacitor electrode connected to the second pad through the second contact hole. The semiconductor device manufacturing method characterized by the above-mentioned. The method of claim 1, The word line, the first pad and the second pad is a semiconductor device manufacturing method, characterized in that formed of doped polysilicon. The method of claim 1, And forming an impurity ion implantation step to lower contact resistance after forming the first contact hole and the second contact hole.