KR20000042408A - Method of forming contact hole of semiconductor device - Google Patents
Method of forming contact hole of semiconductor deviceInfo
- Publication number
- KR20000042408A KR20000042408A KR1019980058573A KR19980058573A KR20000042408A KR 20000042408 A KR20000042408 A KR 20000042408A KR 1019980058573 A KR1019980058573 A KR 1019980058573A KR 19980058573 A KR19980058573 A KR 19980058573A KR 20000042408 A KR20000042408 A KR 20000042408A
- Authority
- KR
- South Korea
- Prior art keywords
- contact hole
- forming
- semiconductor device
- gas
- conductive layer
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000001312 dry etching Methods 0.000 claims abstract description 18
- 239000011229 interlayer Substances 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 21
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 2
- 229910052731 fluorine Inorganic materials 0.000 claims description 2
- 239000011737 fluorine Substances 0.000 claims description 2
- 238000009616 inductively coupled plasma Methods 0.000 claims description 2
- 239000000654 additive Substances 0.000 claims 1
- 230000000996 additive effect Effects 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 9
- 229920005591 polysilicon Polymers 0.000 abstract description 9
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 5
- 238000000151 deposition Methods 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 13
- 239000011521 glass Substances 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- BSYNRYMUTXBXSQ-UHFFFAOYSA-N Aspirin Chemical compound CC(=O)OC1=CC=CC=C1C(O)=O BSYNRYMUTXBXSQ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001000 micrograph Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 기술에 관한 것으로, 특히 콘택 저항을 줄이기 위한 반도체 소자의 콘택홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a method of forming contact holes in a semiconductor device for reducing contact resistance.
일반적으로, 반도체 소자는 다층의 적층 구조를 취하며, 이러한 다층 구조간의 전기적 연결을 위하여 콘택홀을 이용한 수직 배선법을 사용하고 있다. 반도체 소자의 고집적화에 따라 콘택홀의 콘택홀 크기가 작아지고 있으며 단차비(aspect ratio) 또한 증가하고 있다. 이에 따라 콘택 저항이 반도체 소자 개발에 중요한 이슈(issue)로 대두되었다.In general, a semiconductor device has a multilayer structure, and a vertical wiring method using contact holes is used for electrical connection between the multilayer structures. As the integration of semiconductor devices increases, the size of contact holes in contact holes decreases, and the aspect ratio also increases. Accordingly, contact resistance has emerged as an important issue for semiconductor device development.
콘택 저항은 콘택 면적에 따라 민감하게 변하기 때문에 콘택 면적을 크게 하면 개선시킬 수 있으나, 고집적화된 반도체 소자에서는 더 이상 콘택 크기를 증가시키기 어렵다. 또한, 콘택홀의 단차비가 증가함에 따라 콘택홀 하부의 면적을 확보하기가 더욱 어려워졌다.Since the contact resistance changes sensitively depending on the contact area, it can be improved by increasing the contact area, but it is difficult to increase the contact size any more in highly integrated semiconductor devices. In addition, as the stepped ratio of the contact hole increases, it becomes more difficult to secure an area under the contact hole.
첨부된 도면 도 1은 종래기술에 따라 형성된 콘택홀 단면의 주사전자현미경(SEM) 사진을 도시한 것으로, 종래에는 통상적으로 하부 전도층이 형성된 전체구조 상부에 층간절연막을 형성하고 이를 선택적으로 건식 식각하거나, 건식 식각 전에 콘택홀 입구 부분의 습식 식각을 진행하여 와인 글래스(wine glass) 형태의 콘택홀을 형성하는 것이었다.1 is a scanning electron microscope (SEM) photograph of a cross section of a contact hole formed according to the prior art, and conventionally, an interlayer insulating film is formed on an entire structure in which a lower conductive layer is formed, and dry etching is selectively performed. Alternatively, wet etching of the contact hole inlet portion before dry etching was performed to form a contact glass in the form of wine glass.
그러나, 도시된 바와 같이 이러한 통상적인 종래기술에 따라 형성된 콘택홀은 그 하부로 갈수록 홀 크기가 크게 줄어들고 있어, 콘택 저항의 증가를 어렵지 않게 예상할 수 있다.However, as shown, the contact hole formed according to this conventional prior art has greatly reduced the hole size toward the bottom thereof, so that an increase in contact resistance can be expected without difficulty.
본 발명은 레이아웃 상의 콘택홀 크기를 증가시키지 않고 콘택 면적을 증가시켜 콘택 저항을 줄일 수 있는 반도체 소자의 콘택홀 형성방법을 제공하는데 그 목적이 있다.It is an object of the present invention to provide a method for forming a contact hole in a semiconductor device capable of reducing contact resistance by increasing a contact area without increasing a contact hole size on a layout.
도 1은 종래기술에 따라 형성된 콘택홀 단면의 주사전자현미경(SEM) 사진도.1 is a scanning electron microscope (SEM) photograph of a contact hole cross section formed according to the prior art.
도 2a 및 도 2b는 본 발명의 일 실시예에 따른 콘택홀 형성 공정도.2A and 2B are diagrams illustrating a contact hole forming process according to an embodiment of the present invention.
도 3은 본 발명의 일 실시예에 따라 형성된 콘택홀 단면의 주사현미경 사진도.3 is a scanning microscope photograph of a cross-section of a contact hole formed in accordance with one embodiment of the present invention.
도 4는 종래기술과 본 발명의 일 실시예에 따라 형성된 콘택홀의 크기에 따른 콘택 저항을 측정한 결과를 도시한 그래프.Figure 4 is a graph showing the result of measuring the contact resistance according to the size of the contact hole formed in accordance with the prior art and an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
20 : 실리콘 기판20: silicon substrate
21 : 폴리실리콘 게이트21: polysilicon gate
22 : 층간절연막22: interlayer insulating film
23 : 포토레지스트 패턴23 photoresist pattern
콘택 저항은 그 면적에 민감하게 반응한다. 이론적으로 콘택 저항은 콘택 면적에 반비례한다. 그러나, 고집적화된 반도체 소자에서는 레이아웃(layout) 상의 콘택 크기를 증가시키는 것이 거의 불가능하므로, 본 발명은 콘택홀의 레이아웃 크기의 증가를 억제하면서 실질적인 콘택 면적을 넓혀주는 관점에서 착안하였다. 이에 본 발명은 통상적인 공정을 통해 콘택홀을 형성하고, 이후 등방성 건식 식각을 실시하여 콘택홀 하부의 크기를 증가시키고 하부 전도층의 프로파일(profile)을 곡선화하여 콘택 면적을 증가시키는 기술이다.Contact resistance is sensitive to its area. In theory, contact resistance is inversely proportional to the contact area. However, since it is almost impossible to increase the contact size on the layout in a highly integrated semiconductor device, the present invention has been conceived in view of increasing the actual contact area while suppressing an increase in the layout size of the contact hole. Accordingly, the present invention is a technique for forming a contact hole through a conventional process, and then performing isotropic dry etching to increase the size of the lower contact hole and to curve the profile of the lower conductive layer to increase the contact area.
상기 기술적 과제를 달성하기 위하여 본 발명으로부터 제공되는 반도체 소자의 콘택홀 형성방법은, 소정의 하부 전도층이 형성된 반도체 기판 상에 층간절연막을 형성하는 제1 단계; 상기 층간절연막을 선택적으로 비등방성 건식 식각하여 상기 하부 전도층을 노출시키는 콘택홀을 형성하는 제2 단계; 및 상기 층간절연막에 대한 상기 하부 전도층의 식각률이 높은 등방성 건식 식각 공정을 상기 콘택홀에 선택적으로 적용하는 제3 단계를 포함하여 이루어진다.According to an aspect of the present invention, there is provided a method of forming a contact hole in a semiconductor device, the method comprising: forming an interlayer insulating film on a semiconductor substrate on which a predetermined lower conductive layer is formed; Selectively anisotropic dry etching the interlayer dielectric layer to form a contact hole exposing the lower conductive layer; And a third step of selectively applying an isotropic dry etching process having a high etching rate of the lower conductive layer to the interlayer insulating layer to the contact hole.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
첨부된 도면 도 2a 및 도 2b는 본 발명의 일 실시예에 따른 콘택홀 형성 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.2A and 2B illustrate a contact hole forming process according to an embodiment of the present invention, which will be described below with reference to the drawings.
본 실시예에 따른 콘택홀 형성 공정은, 우선 도 2a에 도시된 바와 같이 폴리실리콘 게이트(21)가 형성된 실리콘 기판(20) 상에 층간절연막(22)을 증착하고, 그 상부에 콘택홀 형성을 위한 포토레지스트 패턴(23)을 형성한 다음, 이를 식각 마스크로 사용하여 층간절연막(22)을 비등방성 건식 식각하여 폴리실리콘 게이트(21) 및 실리콘 기판(20)(정확하게는 접합 영역)을 노출시키는 콘택홀을 형성한다. 이때, 층간절연막(22)은 BPSG(borophospho silicate glass), PSG(phospho silicate glass), BSG(boro silicate glass) 등의 도핑된 산화막(doped oxide)과 TEOS(tetraethyl ortho silicate), MTO(medium temperature oxide), HTO(high temperature oxide), LTO(low temperature oxide) 등의 비도핑 산화막(undoped oxide) 모두가 적용될 수 있으며, 질화막이나 SOG(spin on glass) 등이 포함될 수 있다.In the contact hole forming process according to the present embodiment, first, as shown in FIG. 2A, an interlayer insulating layer 22 is deposited on a silicon substrate 20 on which a polysilicon gate 21 is formed, and contact hole formation is formed thereon. After forming the photoresist pattern 23 for the etching process, anisotropic dry etching of the interlayer dielectric layer 22 is performed using the photoresist pattern 23 to expose the polysilicon gate 21 and the silicon substrate 20 (preferably the junction region). A contact hole is formed. In this case, the interlayer insulating layer 22 may be a doped oxide such as borophospho silicate glass (BPSG), phospho silicate glass (PSG), boro silicate glass (BSG), tetraethyl ortho silicate (TEOS), and medium temperature oxide (MTO). ), All of the undoped oxides such as high temperature oxide (HTO) and low temperature oxide (LTO) may be applied, and may include a nitride film or a spin on glass (SOG).
계속하여, 도 2b에 도시된 바와 같이 층간절연막(22)에 대해서는 낮은 식각률(etch rate)을 가지며 폴리실리콘 게이트(21)에 대해서는 높은 식각률을 갖는 등방성 건식 식각을 실시한다.Subsequently, as shown in FIG. 2B, an isotropic dry etching having a low etch rate for the interlayer insulating film 22 and a high etch rate for the polysilicon gate 21 is performed.
이때, 접합 영역이 노출되므로 접합 특성을 저하시키는 않는 범위 내에서 적절한 식각 타겟(target)을 설정하여야 하며, 비등방성 건식 식각과 인-시츄(in-situ)로 진행할 수 있다. 또한, O2가스 등을 더 사용하여 등방성 식각과 함께 포토레지스트 패턴(23)의 제거 공정이 동시에 수행되도록 할 수 있다.In this case, since the junction region is exposed, an appropriate etching target should be set within a range that does not degrade the bonding characteristic, and the process may proceed to anisotropic dry etching and in-situ. In addition, the removal process of the photoresist pattern 23 may be simultaneously performed with isotropic etching using an O 2 gas or the like.
등방성 건식 식각은 ECR(electron cyclotron resonance) 방식, TCP(transformer coupled plasma) 방식, HELICON 방식 등 거의 모든 건식 식각 장비에서 이루어질 수 있으나, 본 실시예에서는 ICP(induced coupled plasma) 방식의 챔버(chamber)에서 다음과 같은 상세 공정 조건(recipe)을 사용하여 실시한다.Isotropic dry etching can be performed in almost all dry etching equipment, such as electron cyclotron resonance (ECR), transformer coupled plasma (TCP), and HELICON, but in this embodiment, in an chamber of an induced coupled plasma (ICP) method It is carried out using the following detailed process recipe.
가) -10∼100℃ 범위의 웨이퍼 온도.A) Wafer temperature in the range of -10 to 100 ° C.
나) 300∼1200W 범위의 RF 전원(radio frequency power).B) RF power (radio frequency power) in the range 300-1200W.
다) 0.1∼1.0Torr 범위의 압력.C) Pressure in the range of 0.1 to 1.0 Torr.
라) 주 식각 가스 및 유량(flow rate) : NF3가스, 10∼70SCCM.D) Main etching gas and flow rate: NF 3 gas, 10 ~ 70SCCM.
마) 식각 선택비 조절용 가스 유량 : N2가스, 50∼250SCCM 및 He 가스 100∼400SCCM(O2가스도 식각 선택비 조절용 가스로 사용될 수 있음).E) Gas flow rate for adjusting the etching selectivity: N 2 gas, 50-250SCCM and He gas 100-400SCCM (O 2 gas may also be used as the gas for controlling the etching selectivity).
바) 전체 가스 유량 : 180∼700SCCM.F) Total gas flow rate: 180 ~ 700SCCM.
이와 같은 공정 조건으로 등방성 건식 식각을 진행하게 되면, 실리콘:산화막의 선택비가 3:1 이상을 나타내기 때문에 콘택홀의 레이아웃 상의 크기 증가가 매우 적으며, 콘택홀 하부의 크기를 증가시키고 폴리실리콘 게이트(21) 및 실리콘 기판(22)이 등방성 식각되어 곡선 프로파일을 가지므로 이후 콘택되는 도전층과의 콘택 면적을 증가시킬 수 있다.When the isotropic dry etching is performed under such process conditions, the selectivity ratio of silicon to oxide is 3: 1 or more, so the increase in size of the contact hole layout is very small, and the size of the contact hole lower is increased and the polysilicon gate ( 21 and the silicon substrate 22 are isotropically etched to have a curved profile, thereby increasing the contact area with the conductive layer to be subsequently contacted.
첨부된 도면 도 3은 본 발명의 일 실시예에 따라 형성된 콘택홀 단면의 주사현미경 사진을 도시한 것으로, 본 실시예에 따라 등방성 건식 식각을 더 수행한 경우, 상기 도 1과 비교하여 홀 하부의 크기가 커지고 콘택 면적이 더 넓어짐을 확인할 수 있다.3 is a view illustrating a scanning micrograph of a contact hole cross section formed according to an embodiment of the present invention. In the case where an isotropic dry etching is further performed according to the present embodiment, a lower portion of the hole is compared with FIG. It can be seen that the size is larger and the contact area is wider.
첨부된 도면 도 4는 종래기술과 본 발명의 일 실시예에 따라 형성된 콘택홀의 크기에 따른 콘택 저항을 측정한 결과를 도시한 그래프로서, 본 발명의 일 실시예에 따라 등방성 식각을 실시한 경우, 같은 콘택 크기에서 콘택 저항이 크게 개선됨을 확인할 수 있다.4 is a graph illustrating a result of measuring contact resistance according to a size of a contact hole formed according to an exemplary embodiment of the present invention and the prior art. When isotropic etching is performed according to an embodiment of the present invention, It can be seen that the contact resistance is greatly improved in the contact size.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
예를 들어, 전술한 실시예에서는 폴리실리콘 게이트 및 접합 영역의 콘택 저항을 개선하는 경우를 일례로 들어 설명하였으나, 본 발명은 금속 배선간의 콘택홀(비아홀) 형성시와 같이 다른 구조 및 다른 물질의 콘택을 형성하는 경우에도 적용할 수 있다.For example, in the above-described embodiment, the case where the contact resistance of the polysilicon gate and the junction region is improved has been described as an example. However, the present invention is not limited to other structures and materials, such as when forming contact holes (via holes) between metal wirings. The same applies to the case of forming a contact.
또한, 전술한 실시예에서는 주 식각 가스로서 NF3가스를 사용하는 경우를 일례로 들어 설명하였으나, 본 발명은 등방성 건식 식각 공정에 통상적으로 사용되고 있는 CF4, C2F6, C3F8, C4F8, C5F8, CHF3, CH2F2, CHF3등의 다른 불소(fluorine)계 가스를 주 식각 가스로 사용하는 경우에도 적용할 수 있다.In addition, in the above-described embodiment, the case where NF 3 gas is used as the main etching gas has been described as an example. However, the present invention uses CF 4 , C 2 F 6 , C 3 F 8 , It is also applicable to the case where other fluorine-based gases such as C 4 F 8 , C 5 F 8 , CHF 3 , CH 2 F 2 and CHF 3 are used as the main etching gas.
전술한 본 발명은 등방성 건식 식각 기술을 이용하여 콘택홀 하부의 크기를 증가시키고 하부 도전층의 프로파일을 곡선화함으로써 콘택 면적을 증가시키는 효과가 있으며, 이로 인하여 콘택 저항을 개선하고 반도체 소자의 동작 속도를 향상시키는 효과가 있다.The present invention described above has the effect of increasing the contact area by increasing the size of the lower contact hole and curved profile of the lower conductive layer using an isotropic dry etching technique, thereby improving the contact resistance and operating speed of the semiconductor device Has the effect of improving.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980058573A KR20000042408A (en) | 1998-12-24 | 1998-12-24 | Method of forming contact hole of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980058573A KR20000042408A (en) | 1998-12-24 | 1998-12-24 | Method of forming contact hole of semiconductor device |
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| Publication Number | Publication Date |
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| KR20000042408A true KR20000042408A (en) | 2000-07-15 |
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| KR1019980058573A KR20000042408A (en) | 1998-12-24 | 1998-12-24 | Method of forming contact hole of semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111653476A (en) * | 2020-05-13 | 2020-09-11 | 上海华虹宏力半导体制造有限公司 | Etching method and structure of contact hole |
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1998
- 1998-12-24 KR KR1019980058573A patent/KR20000042408A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111653476A (en) * | 2020-05-13 | 2020-09-11 | 上海华虹宏力半导体制造有限公司 | Etching method and structure of contact hole |
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