KR20000041596A - Semiconductor device for outputting data of high speed - Google Patents

Abstract

PURPOSE: A semiconductor device for outputting data of high speed is provided to operate a bypass read via a bypass path before writing data in a memory cell. CONSTITUTION: In a logical 'low' level of a second bypass control signal(BYPB), a self reset control unit(600) generates a logical 'low' first enable signal and a logical 'high' second enable signal. A main sense amplifier(100) and a level shifter(200) are disabled. A bypass unit(500) bypasses data from a data input buffer into a data output buffer(300) while a first bypass control signal maintains the logical 'high' level. The bypassed data are latched in nodes of the data output buffer(300). In sequentially activating a data patch signal and an output enable signal in the logical 'high' level, the bypassed data are outputted to an outside of a chip via an off chip driver(400) and a data input/output pad.

Description

High speed data output semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for high speed data output, and more particularly to a semiconductor device for high speed data output capable of outputting data at high speed by having a salp latch and a reset function.

1 is a block diagram illustrating a conventional high speed data output semiconductor device. As shown in the drawing, a main sense amplifier 10 for sensing and amplifying data read from a memory cell (not shown), and a main sense And a level shifter 20 for level converting sensing data SAS and SASB from the amplifier 10 and outputting level shifting data DATAA and DATAAB, and a first latch and a second latch. SLP latches (DATAA, DATAAB) to the first latch, latches the data latched to the first latch to the second latch in response to the data patch signal KDATA, and responds to the output enable signal OE. 2 and 1 and 2 in response to the data output buffer 30 outputting the data latched in the latch through the off-chip driver 40, the first control signal MSAENP and the level shifting data DATAA and DATAAB. Generate enable signals (MSAEN, KDPRECB), The main sense amplifier 10 and the data sensed by the first and second enable signals MSAEN and KDPRECB so that the data sensed by the main sense amplifier 10 may be reset immediately after they are latched to the first latch of the output buffer 30. It is composed of a salp reset controller 50 for controlling the level shifter 20.

As shown in FIG. 2, the salp reset control unit 50 includes a NOA gate OR for negating OR of the level shifting data DATAA and DATAAB, an output signal of the NOA gate OR, and a first control signal MSAENP. Generates a first enable signal MSAEN for enabling the main sense amplifier 10 by inverting the NAND gate 51 and the output signal of the NAND gate 51, and the NAND gate 51. A multi-stage inverter (INV1, INV2, INV3, INV4) for generating a second enable signal (KDPRECB) for enabling the level shifter as a delay of the output signal.

The NAND gate 51 is coupled between the power supply voltage and the output terminal and is coupled between the PMOS transistor MP1 driven in response to the output signal of the NOR gate NOR and the first control signal MSAENP. NMOS transistors MN1 coupled in series between the output terminal and ground and driven in correspondence to the output signals of the first control signal MSAENP and the NOR gate NOR. , MN2).

The semiconductor device for high-speed data output having the above-described configuration has a number of clock latches and a cell reset function, thereby reducing the number of clocks, thereby outputting data at high speed without limiting cycle time, and in particular, generating level shifting data DATAA and DATAAB. As a result, the pulse widths of the first enable signal MSAEN and the second enable signal KDPRECB are adjusted to perform stable and fast operation even under various conditions such as temperature, process, and power supply voltage.

However, the conventional technology as described above has a problem in that the bus efficiency is lowered because the cell data read operation is supported but the bypass read operation is not supported. Here, the bypass read operation refers to a read operation that occurs when data is written to a memory cell but data is not yet written to the memory cell and the data is to be read. In other words, if it is determined that data related to the write address has not been written to the memo cell yet by comparing the write address with the read address, the data in the data input buffer cannot be read from the memory cell through the main sense amplifier. Is to output through data output buffer directly.

On the other hand, in the field of semiconductor memory devices that perform pipeline operations, a research has been made to improve bus utilization efficiency by providing a latency during read operations as the cycle timing becomes short and at the same time by providing a standby time during write operations. In progress, a representative example is NtRAM. In the semiconductor memory device having such write latency, it is preferable to support the bypass read in order to increase the bus use efficiency.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a high speed data output semiconductor memory device capable of a bypass read operation that reads data through a bypass path before writing data to a memory cell. Is in.

In order to achieve the above object, the semiconductor device for high-speed data output according to the present invention includes a main sense amplifier for sensing data read from a memory cell and outputting sensing data, and an output driver for outputting data. A semiconductor device comprising: level shifting means for level converting sensing data from the main sense amplifier to output level shifting data; A first latch and a second latch, and latching the level shifting data to the first latch, latching the data latched to the first latch to the second latch in response to a data patch signal, and outputting Data output buffering means for outputting data latched in the second latch through the output driver in response to an enable signal; Bypass means for bypassing data provided from an input buffer to said data output buffering means in response to a first bypass control signal; And generating first and second enable signals for controlling the main sense amplifier and the level shifting means in response to the first control signal, the second bypass control signal, and the level shifting data. The main sense amplifier and the level shifting means are controlled so as to reset the sensing data after they are latched to the data output buffering means, and data bypassed from the bypass means is latched to the data output buffering means during a bypass read operation. And a reset reset control means for controlling the main sense amplifier and the level shifting means.

1 is a block diagram for explaining a conventional high speed data output semiconductor device.

FIG. 2 is a detailed circuit diagram illustrating the salp reset control unit of FIG. 1. FIG.

3 is a block diagram for explaining a high speed data output semiconductor device according to the present invention;

4 is a detailed circuit diagram illustrating the level shifter of FIG. 3.

FIG. 5 is a detailed circuit diagram illustrating a data output buffer and an off chip driver of FIG. 3. FIG.

6 is a detailed circuit diagram illustrating a bypass unit of FIG. 3.

FIG. 7 is a detailed circuit diagram illustrating the salp reset controller of FIG. 3. FIG.

8 is a waveform diagram at the time of cell data read operation according to the present invention;

Fig. 9 is a waveform diagram at the time of a pie pass operation according to the present invention;

* Explanation of symbols for the main parts of the drawings

100; Main sense amplifier 200; Level shifter

300; Data output buffer 301; First latch

302; Second latch 400; Off-chip driver

500; Bypass unit 600; Salp Reset Control

601; Nandgate 602; Precha branch

Hereinafter, one preferred embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram illustrating a semiconductor device for high-speed data output according to an embodiment of the present invention. As shown in the drawing, sensing data (SAS, SASB) is output by sensing cell data read from a memory cell (not shown). A level shifter 200 for level converting the sensing data SAS and SASB from the main sense amplifier 100 to the level shifting data DATAA and DATAAB and outputting the level shifting data DATAA and DATAAB; And latching shifting data DATAA and DATAAB to the first latch, and latching data latched to the first latch to the second latch in response to a data patch signal KDATA. In response to the output enable signal OE, the data output buffer 400 outputs the data latched in the second latch through the off-chip driver 500 and in response to the first bypass control signal BYP_pul. Data provided by the input buffer (DINREG ) In response to the bypass unit 500 bypassing the data output buffer 300, the first control signal MSAENP, the second bypass control signal BYPB, and the level shifting data DATAA and DATAAB. First and second enable signals MSAEN and KDPRECB for controlling the sense amplifier 100 and the level shifting unit 200 are generated, and the sensing data SAS and SASB are level converted during a cell data read operation. The level shifting unit 200 is controlled so that the data output buffer unit 300 can be latched and reset, and the data DATAP and DATAPB bypassed from the bypass unit 500 during the bypass read operation are stored in the data output buffer ( And a salp reset control unit 600 that controls the main sense amplifier 100 and the level shifting unit 200 to be latched to 300.

The first control signal MSAENP is a clock signal which is a basic signal for generating the first enable signal MSAEN for enabling the main sense amplifier 100. The signal is always generated during the cell data read operation and the bypass read operation. to be.

The first bypass control signal BYP_pul is a type of clock signal for transmitting data in the data input buffer to the data output buffer 300 during the bypass read operation.

The second bypass control signal BYPB is active at a logic " low " level during the bypass read operation, and is a fixed signal that continuously maintains the logic " low " level when the bypass read operation is performed two consecutive times.

As shown in FIG. 4, the level shifter 20 includes a PMOS transistor MP1 having a source coupled to a power supply voltage source and driven in response to a second enable signal KDPRECB, and a source having a PMOS transistor MP1. PMOS transistors MP2 and MP3 commonly coupled to the drain of the main sense amplifier 10 and driven by the output data SAS and SASB of the main sense amplifier 10, and between the drain and ground of the pair of PMOS transistors MP2 and MP3. NMOS transistors MN1 and MN2 coupled to the drains of the PMOS transistors MP2 and MP3, respectively, and an output node N1 which is a connection point between the PMOS transistor MP2 and the NMOS transistor MN1. ) Is coupled between the output node N2, which is a connection point of the PMOS transistor pin MP3 and the NMOS transistor MN2, and ground, respectively, and responds to the second enable signal KDPRECB. NMOS transistor to pull down N2) to ground level (MN3, MN4).

As shown in FIG. 5, the data output buffer 300 includes inverters INV1, INV2, INV3, INV4, INV5, INV6, INV7, INV8, INV9, and INV10, and PMOS transistors MP4, MP5, MP6, and the like. MP7, MP8, MP9, MP10, MP11, NMOS transistors MN5, MN6, MN7, MN8, MN9, MN10, and NAND gates ND1, ND2.

The inverter pairs INV3 and INV4 and the inverter pairs INV7 and INV8 form a first latch 301 and a second latch 302, respectively.

As shown in FIG. 5, the off-chip driver 400 includes an NMOS transistor MN11 for pulling up the output node N3 to a power supply voltage level in response to an output signal DOU of the data output buffer 300; The NMOS transistor MN12 pulls down the output node N3 to the ground level in response to the output signal DOD of the data output buffer 300.

As shown in FIG. 6, the bypass unit 500 includes an inverter INV11 for inverting the data signal DINREG provided from the input buffer, an inverter INV12 for inverting the output signal of the inverter INV11, and 1 The inverter INV13 inverting the bypass control signal BYP_pul and the power supply voltage and the output node N3 are coupled in series and driven in response to the output signal of the inverter INV2 and the output signal of the inverter INV13. NMOS transistors coupled in series between the PMOS transistors MP12 and MP13 and the output node N3 and ground and driven in correspondence to the first bypass control signal BYP_pul and the output signal of the inverter INV12 ( PMOS transistors MP14 and MP15 coupled in series between the MN13 and MN14, the power supply voltage and the output node N4, and driven in correspondence to the output signal of the inverter INV11 and the output signal of the inverter INV13; First bypass control coupled in series between output node N4 and ground Corresponding to the output signal of the call (BYP_pul) and an inverter (INV11) and consists of NMOS transistor driven (MN15, MN16).

Output data DATAP and DATAPB of the bypass unit 500 are coupled corresponding to an input terminal of the first latch 301.

As illustrated in FIG. 7, the salp reset control unit 600 includes a NOR gate NOR1 that performs an NOR operation on the level shifting data DATAA and DATAAB, an output signal of the NOR gate NOR1, and a first control signal MSAENP. Inverts the NAND gate 601 which negates AND, the precharge unit 502 which precharges the output terminal of the NAND gate 601 to the power supply voltage level during the bypass read operation, and the output signal of the NAND gate 601. The NAND gate ND3 and the NAND gate ND3 output by inverting the output signal of the inverter INV15, the output signal of the inverter INV15 and the second bypass control signal BYBP, and output the main sense. Inverter INV16 generating the first enable signal MSAEN for enabling the amplifier 100 and a second inverter for enabling the level shifting unit 200 by inverting the output signal of the inverter INV16. Consists of inverter INV17 that generates the enable signal KDPRECB do.

The NAND gate 601 is coupled between a power supply voltage and an output terminal thereof and is coupled between a PMOS transistor MP16 driven in response to an output signal of the NOA gate NOR1, and is coupled between the power supply voltage and an output terminal and connected to a first control signal ( PMOS transistor MP17 driven by MSAENP and NMOS transistors coupled in series between the output terminal and ground and driven in correspondence to the output signals of first control signal MSAENP and NOR gate NOR1. MN17, MN18).

The precharge unit 502 includes a noar gate NOR2 that negates the first control signal MSAENP and the second bypass control signal BYPB, and an inverter INV14 that inverts the output signal of the noar gate NOR2. And a PMOS transistor MP18 coupled between the power supply voltage and the output terminal of the NAND gate 601 and driven to the output signal of the inverter INV14.

The operation of the semiconductor device for high speed data output configured as described above is as follows.

Referring to FIG. 3, a cell data read operation according to an exemplary embodiment of the present invention may include the main sense amplifier 100 in response to a first enable signal MSAEN having a logic "high" level. After sensing and amplifying the data read from the (not shown) to generate the sensing data (SAS, SASB), the level shifter 200 in response to the second enable signal KDPRECB of the logic "low" level The sensing data SAS and SASB transmitted from the amplifier 100 are converted into a complementary metal oxide silicon (CMOS) logic level to generate level shifting data DATAA and DATAAB. The level shifting data DATAA and DATAAB are transmitted to the data output buffer 300 and the salp reset control unit 600, respectively.

The level shifting data DATAA and DATAAB transmitted from the level shifter 200 are salp latched to the data output buffer 300, and the data patch signal KDATA is at a logic "high" level, and the output enable signal OE Are sequentially activated to a logic " high " level and then output to an external input / output (I / O) pad via off-chip driver 400.

On the other hand, the level shifting data DATAA and DATAAB have been logic latched in the data output buffer 300 and then the level shifting data DATAA and DATAAB have different logic levels, and the first control signal MSAENP has a logic “low”. The level of the second bypass signal BYPB is a "low" level only in the case of a bypass lead, and a signal of "high" level in the other cases. The four reset signals 600 generate the first enable signal MSAEN at the logic "low" level and the first enable signal KDPRECB at the logic "high" level, and sequentially turn the main sense amplifier on. The 100 and the level shifter 200 are disabled. At this time, the data output buffer 300 is reset.

Next, referring to the bypass read operation according to an embodiment of the present invention, first, when the second bypass control signal BYPB is at a logic "low" level, the salp reset control unit 600 may be configured. A first enable signal MSAEN of a logic "low" level and a second enable signal KDPRECB of a logic "high" level are generated, whereby the main sense amplifier 100 and the level shifter 200 are disabled. In this case, the bypass unit 500 supplies the data DINREG provided from the data input buffer (not shown) while the first bypass control signal BYP_pul maintains the logic "high" level. Bypass 300. The bypassed data DATAP and DATAPB are latched to the nodes DATAB and DATAB of the data output buffer 300, and the bypass data is obtained by a logic " high " At the "level," the output enable signal OE is sequentially activated to a logic "high" level. At this time, the chip is output to the outside of the chip via the off-chip driver 400 and the data input / output (I / O) pad.

Referring to FIG. 4, the operation of the level shifter 200 will be described in more detail. When the second enable signal KDPRECB maintains the "low" level during the cell data read operation, the PMOS transistor MP1 is set to zero. The PMOS transistor MP2 and the PMOS transistor MP3 are turned on in response to the two enable signals KDPRECB, and the PMOS transistor MP2 and the PMOS transistor MP3 are turned on according to the sensing data SAS and SASB from the main sense amplifier 100. For example, when the sensing data SAS is at a logic "high" level, the PMOS transistor MP2 is turned off, the PMOS transistor MP3 is turned on, and the NMOS transistor MN1 is sequentially turned on, and the NMOS transistor is sequentially turned on. MN2 is turned off. Accordingly, the level shifter 200 generates level shifting data DATAAB of logic "low" level and level shifting data DATAA of logic "high" level through output nodes N1 and N2, respectively, and outputs the data. In addition to the buffer 300, it is provided to the salp reset control unit 600.

As described above, since the second enable signal KDPRECB is a logic " high " level after the level shifting data DATAA and DATAAB are being latch latched to the data output buffer 300, the NMOS transistors MN3 and MN4. Is turned on, so that the potentials of the point shift points N1 and N2 are pulled down to the ground level.

Referring to FIG. 5, the operation of the data output buffer 300 will be described in more detail. First, the state of the first latch 301 during the cell data read operation depends on the logic levels of the level shifting data DATAA and DATAAB. Is determined. For example, when the level shifting data DATAA and DATAAB have different logic levels, data DATABB and DATAB inverting the level shifting data DATAA and DATAAB are latched in the first latch 301. On the other hand, when the level shifting data DATAA and DATAAB have the same logic " low " level, only the transistors MP4 and MP6 are turned on so that the input terminal of the first latch 301 is in a floating state, and thus the first latch 301 ) Retains the previous data.

When the level shifting data DATAA and DATAAB are latched in the first latch 301, the latched data DATABB and DATAB are next to each other when the data patch signal KDATA is activated to a logic " high " level. Is transmitted to the second latch 302 and latched. Here, the data DATAC and DATACB latched in the second latch 302 are data whose phase is inverted with respect to the data DATAA and DATAAB latched in the latch 301 in the first latch. The latch data DATAC and DATACB are off-chip via a combination circuit consisting of the NAND gates ND1 and ND2 and the inverters INV9 and INV10 when the output enable signal OE is activated to a logic “high” level. It is output to the driver 400.

Next, during the bypass read operation, the level shifter 200 is disabled and all of the level shifting data DATAA and DATAAB maintain the same level of logic " low, " Bypass data DATAP and DATAPB supplied from 500 are latched. Subsequent output operations are the same as the cell data read operations, and will be omitted below.

Referring to FIG. 5, the off-chip driver 400 is driven in response to the output signals DOU and DOD from the data output buffer 300 and transmits final output data to an external data input / output bus. For example, when the output signal DOU is at the logic "high" level, the NMOS transistor MN11 is turned on so that the potential of the output terminal is pulled up to the power supply voltage level. On the other hand, when the output signal DOD is at the logic "high" level, the NMOS transistor is (MN12) is turned on so that the potential at the output stage is pulled down to ground level.

Referring to FIG. 6, the operation of the bypass unit 500 will be described in more detail. For example, the data of the data input buffer (not shown) is at a logic “high” level, and the first bypass control signal BYP_pul is applied. When active at a logic "low" level, inverter INV11 signals a logic "low" level, inverter INV12 signals a logic "high" level, and inverter INV13 signals a logic "high" level. Since the NMOS transistors MN13 and MN14 and the PMOS transistors MP14 and MP15 are turned on, the logic "low" level data DATAPB and the logic "high" level data DATAP are turned on. ) Is output.

Referring to FIG. 7, the operation of the salp reset control unit 600 will be described in more detail. First, since the level shifting data DATAA and DATAAB all maintain the logical " low " level during the cell data read operation, The NOR gate NOR outputs a logic "high" level signal. At this time, when the first control signal MSAENP maintains a logic "high" level, the NAND gate 601 outputs a signal of a logic "low" level. This output signal is inverted by the inverter INV15 and then input to the NAND gate ND3.

In this state, according to the embodiment of the present invention, the second bypass control signal BYPB maintains a logic "low" level. Thus, the NAND gate ND3 generates an output signal of logic " high " level. This output signal is inverted by the inverter INV16 and then output as the first enable signal MSAEN of logic "high" level, while the logic "low" level after a predetermined time delay via the inverters INV16 and INV17. Is output as the second enable signal KDPRECB. Thus, the main sense amplifier 100 and the level shifter 200 are enabled.

On the other hand, since the level shifting data DATAA and DATAAB have different logic levels after the level shifting data DATAA and DATAAB have been latch latched as described above, the NOR gate NOR generates a "low" level signal. The NAND gate 601 then outputs a logic "high" level signal. This output signal is inverted by the inverter INV15 and then input to the NAND gate ND3. As a result, the reset reset controller 600 generates the first enable signal MSAEN of logic "low" level and the second enable signal KDPRECB of logic "high" level to generate the main sense amplifier 100 and the level shifter. Disable 200.

Next, when the cell data read operation is switched to the bypass read operation, the second bypass control signal BYPB maintains a logic " low " level, so that the first enable signal MSAEN and the second enable signal are changed. The enable signal KDPRECB becomes a logic "low" level and a logic "high" level, respectively, so that the main sense amplifier 100 and the level shifter 200 are disabled.

As described above, the salp reset control unit 600 generates the first enable signal MSAEN and the second enable signal KDPRECB that are the same as the logic level at the time of the reset during the bypass read operation. Since the potential of the output terminal of the NAND gate 601 is in the logic "low" state by the first control signal MSAENP, it is necessary to precharge to the logic "high" level again for the next cell data read operation. However, the conventional salp reset control circuit unit does not provide such an operation. This is because the PMOS transistor MP17 has a small size, thus almost no pull-up function, and the output terminal of the NAND gate 601 can be pulled up to the "high" level only by the PMOS transistor MP16. Accordingly, the reset control circuit unit 600 of the present invention separately provides a precharge unit 602 to precharge the output terminal of the NAND gate 601 during the bypass operation.

According to an exemplary embodiment of the present invention, the precharge unit 602 supplies a power supply voltage to the output terminal of the NAND gate 601 when both the first control signal MSAENP and the second bypass control signal BYPB are at a logic "low" level. Precharge to level. The reason why the first control signal MSAENP is used for the precharge unit 602 is to precharge only the second bypass control signal BYPB so that the first control signal MSAENP is brought to a logic " high " level. This is because a DC pass is formed during the process, causing unnecessary current consumption.

Fig. 8 is a waveform diagram in the cell data read operation according to the present invention, and Fig. 9 is a waveform in the pipe pass read operation according to the present invention, respectively.

As can be seen from the waveform diagram of Fig. 9, the address signal (not shown) and the control signal BYPB are generated before the data in the bypass read operation. From this, it is possible to determine whether the current read operation is a bypass read operation or a cell data read operation. Therefore, the main sense amplifier 100 and the level shifter 200 can be prevented from being enabled when the control signal BYPB generated in the inner block is activated to a logic "low" level.

In addition, as can be seen in the waveform diagram of FIG. 9, in the embodiment of the present invention, even when the first control signal MSAENP is activated to a logic "high" level, the first enable signal MSAEN and the second enable signal ( KDPRECB) ensures no change. By doing so, it is possible to suppress the current consumption of the main sense amplifier.

This invention is not limited to the above-mentioned embodiment, It can change and implement in various ways within the range which does not deviate from the summary.

Accordingly, in the present invention, the cell latch read and the cell reset functions can be used to output data at a high speed during a cell data read operation, and by using a bypass read function, the bus use efficiency can be improved.

Claims (4)

A semiconductor device for a high speed data output having a main sense amplifier for sensing data read from a memory cell and outputting sensing data, and an output driver for outputting data. Level shifting means for level converting sensing data from the main sense amplifier to output level shifting data; A first latch and a second latch, and latching the level shifting data to the first latch, latching the data latched to the first latch to the second latch in response to a data patch signal, and outputting Data output buffering means for outputting data latched in the second latch through the output driver in response to an enable signal; Bypass means for bypassing data provided from an input buffer to said data output buffering means in response to a first bypass control signal; And Generating first and second enable signals for controlling the main sense amplifier and the level shifting means in response to a first control signal, a second bypass control signal, and the level shifting data; The main sense amplifier and the level shifting means are controlled so that they are reset after data has been latched to the data output buffering means, and the data bypassed from the bypass means is latched to the data output buffering means during a bypass read operation. And a reset reset control means for controlling the main sense amplifier and the level shifting means. The method of claim 1, wherein the bypass means A first inverter for inverting the data signal provided from the input buffer, a second inverter for inverting the output signal of the first inverter, a third inverter for inverting the first bypass control signal, a power supply voltage and a first The first and second PMOS transistors which are coupled in series between output nodes and driven in response to the output signal of the second inverter and the output signal of the third inverter, and are coupled in series between the first output node and ground. First and second NMOS transistors driven in correspondence with a first bypass control signal and an output signal of the second inverter, a series coupled between a power supply voltage and a second output node, and the output signal of the first inverter and the first The third and fourth PMOS transistors are driven in correspondence with the output signal of the third inverter, and are serially coupled between the second output node and the ground, and the first bypass control signal and the Which is driven in response to the output signal of the first inverter and the third high-speed data output semiconductor device characterized in that the 4 en composed of MOS transistors. The method of claim 1, wherein the salp reset control means A first NAND gate that performs an NOR on the level shifting data, a first NAND gate that performs an AND logic on the output signal of the first NOR gate, and the first control signal, and an output terminal of the first NAND gate during a bypass read operation. A precharge unit for precharging the voltage to a power supply voltage level, a fourth inverter for inverting the output signal of the first NAND gate, an output signal of the fourth inverter and the second bypass control signal, A second NAND gate, a fifth inverter configured to invert the output signal of the second NAND gate to generate the first enable signal, and an output signal of the fifth inverter to be inverted to generate the second enable signal. And a sixth inverter configured for high speed data output. The method of claim 2, wherein the precharge section Between a second NOR gate that negates the first control signal and the second bypass control signal, a seventh inverter that inverts the output signal of the second NOR gate, and a power supply voltage and an output terminal of the first NAND gate. And a fifth PMOS transistor coupled to and driven by an output signal of the seventh inverter.