KR100855269B1 - Semiconductor memory device including write driver control circuit - Google Patents

Abstract

The present invention relates to a write driver control circuit for controlling a write driver for amplifying data input from the outside during a write operation and providing the same to a memory cell, wherein the circuit 200 for controlling the write driver 300 is a single type. type) consists of a latch structure.

Description

Semiconductor memory device including write driver control circuit {SEMICONDUCTOR MEMORY DEVICE INCLUDING WRITE DRIVER CONTROL CIRCUIT}

1 is a circuit diagram showing a general light driver control circuit 10 and a light driver 20. FIG.

2 is a waveform diagram for explaining the operation of FIG.

3 is a circuit diagram illustrating a semiconductor memory device including the single type latch type write driver control unit 200 according to an exemplary embodiment of the inventive concept.

4 is a circuit diagram illustrating an example of the single type latch type light driver control unit 200 of FIG. 3.

FIG. 5 is a circuit diagram illustrating another example of the single type latch type write driver control unit 200 of FIG. 3.

FIG. 6 is a circuit diagram illustrating an example of the write driver 300 of FIG. 3.

FIG. 7 is a waveform diagram illustrating the operation of the single type latch type write driver control unit 200 of FIG. 3 and the write driver 300 of FIG. 6.

FIG. 8 is a waveform diagram illustrating the operation of the single type latch type write driver control unit 200 of FIG. 3 when the write driver enable signal BWEN is delayed input.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a write driver control circuit for controlling a write driver that amplifies data input from the outside during a write operation and provides them to a memory cell.

In general, a semiconductor memory device includes a write driver that amplifies data input from the outside during a write operation and transfers the data to a local input / output line. The operation of the write driver is controlled by the write driver control circuit 10 as shown in FIG. 1. do.

Specifically, as shown in FIG. 1, the write driver control circuit 10 includes four latch parts 11 to 14, and the write driver 20 includes two driver parts 21 and 22. The configuration and operation thereof will be described below with reference to FIGS. 1 and 2.

The first latch unit 11 is turned on by data transmitted from the global input / output bar line GIOB and transferred from the PMOS transistor P1 and the global input / output bar line GIOB to raise the node ND1 to the power supply voltage VDD level. An NMOS transistor N1 that is turned on by the data to be connected between the node ND1 and the NMOS transistor N2, and an NMOS transistor that is turned on by the write driver enable signal BWEN to lower the node ND1 to the ground voltage VSS level. N2 and two inverters INV1 and INV2 that latch data transferred to the node ND1 and output the latched data DATA_LATB.

 The first latch unit 11 having such a configuration latches data transmitted from the global input / output bar line GIOB by the write driver enable signal BWEN to secure a timing margin for transferring data.

The second latch unit 12 is turned on by data transmitted from the global input / output true line (GIOT) and transferred from the PMOS transistor P2 and the global input / output true line (GIOT) to raise the node ND2 to the power supply voltage VDD level. The NMOS transistor N3, which is turned on by the data to be connected between the node ND2 and the NMOS transistor N4, and the NMOS transistor N4, which lowers the node ND2 to the ground voltage VSS level by the write driver enable signal BWEN. ) And two inverters INV3 and INV4 for latching data transferred to the node ND2 and outputting the latched data to the latched data DATA_LAT.

The second latch unit 12 having such a configuration latches data transmitted from the global input / output true line GIOT by the write driver enable signal BWEN to secure timing margin for transferring data.

The third latch unit 13 is turned on by the precharge control signal PCG and delayed to be enabled at the time when the PMOS transistor P3 for raising the node ND3 to the power supply voltage VDD level, the latched data DATA_LATB and DATA_LAT are output. NMOS transistor N5, which is turned on by the write driver enable signal DBWEN and connects between node ND3 and NMOS transistor N6, and turned on by latched data DATA_LATB, which causes node ND3 to fall to ground voltage VSS level. NMOS transistor N6, two inverters INV5 and INV6 that latch and output the data transferred to node ND3 as latched data PRE_DRV, and the inverted latch signal LATB and driver signal DRV by inverting and delaying latched data PRE_DRV. Inverters (INV7, INV8) for outputting each can be configured.

The third latch unit 13 having such a configuration transmits data to the node ND3 using the delayed write driver enable signal DBWEN, the precharge control signal PCG, and the signal DATA_LATB output from the first latch unit 11. By latching, the inverted latch signal LATB and driver signal DRV for controlling the write driver operation are generated.

The fourth latch unit 14 is turned on by the precharge control signal PCG to turn on the node ND4 to the power supply voltage VDD level, and is turned on by the delayed write driver enable signal DBWEN to the node ND4. And NMOS transistor N7 connecting between NMOS transistor N8, NMOS transistor N8, which is turned on by latched data DATA_LAT and lowers node ND4 to ground voltage VSS level, data transferred to node ND4. Two inverters (INV9 and INV10) for latching and outputting the latched data PRE_DRVB, and inverters (INV11 and INV12) for inverting and delaying the latched data PRE_DRVB and outputting the latch signal LAT and the inverted driver signal DRVB, respectively. have.

The fourth latch unit 14 having such a configuration transmits the data transferred to the node ND4 using the delayed write driver enable signal DBWEN, the precharge control signal PCG, and the signal DATA_LAT output from the second latch unit 12. By latching, the latch signal LAT and the inverted driver signal DRVB for controlling the write driver operation are generated.

The first driver unit 15 is turned on by the latch signal LAT to raise the local input / output true line LIOT to the core voltage VCORE level, and the local input / output true line LIOT turned on by the driver signal DRV. ) May be configured as an NMOS transistor N9 that lowers the level to the ground voltage VSS level.

The first driver 21 having such a configuration amplifies the data of the global input / output true line GIOT by the latch signal LAT and the driver signal DRV, and transfers the data to the local input / output true line LIOT.

The second driver unit 22 is turned on by the inverted latch signal LATB to raise the local I / O bar line LIOB to the core voltage VCORE level, and the PMOS transistor P6 is turned on by the inverted driver signal DRVB to turn on the local I / O bar line. The NMOS transistor N17 may lower the LIOB to the ground voltage VSS level.

The second driver unit 22 having such a structure amplifies the data of the global input / output bar line GIOB by the inversion latch signal LATB and the inversion driver signal DRVB, and transfers the data to the local input / output bar line LIOB.

As described above, the write driver control circuit 10 as shown in FIG. 1 latches data of the global input / output line pairs GIOT and GIOB, and the write driver 20 outputs a signal output from the write driver control circuit 10. Local I / O line pairs (LIOT, LIOB) are driven by LAT, PRV, LATB, and PRVB.

However, the write driver control circuit 10 latches data of the global input / output line pairs GIOT and GIOB through four latch units 11 to 14 to control the write driver 20. Since LATB and PRVB are generated, the area occupied by the write driver control circuit 10 in the semiconductor memory device may increase.

In addition, since the write driver control circuit 10 as shown in FIG. 1 controls the write driver 20 by latching data transmitted from the global input / output line pairs GIOT and GIOB through the four latch units 11 to 14, Due to such a latch operation, there is a problem that current consumption may increase during a write operation.

Accordingly, an object of the present invention is to reduce the area occupied by the write driver control circuit in a semiconductor memory device.

In addition, an object of the present invention is to reduce the current consumption due to the light driver control circuit during the write operation.

A write driver control circuit according to an embodiment of the present invention for achieving the above object, a write for controlling the operation of the write driver to amplify the data of the global input / output line pairs and transfer the data to the local input / output line pairs during the write operation In the driver control circuit, in the write operation, a first output signal is output to a first output node by comparing first and second data of the global input / output line pairs having a first differentially input state, and a differential input second is output. A single type latch unit for comparing the first and second data in a state and outputting a second output signal to a second output node; A precharge controller for equalizing and precharging the first and second output nodes during a precharge operation; And outputting first and second driver signals and first and second latch signals for controlling the write driver using the first and second output signals during the write operation, and the first and second latch signals during the write operation. And a latch type output unit configured to latch a state of the second output node.

In the configuration of the write driver control circuit, the single type latch unit compares first data of a high level and second data of a low level as data of the first state and outputs the first output signal as the first output signal, and the second state. The first data of the low level and the second data of the high level may be output as the second output signal, and the single type latch unit may compare the potential difference between the first and second data. Preferably, the latch is a cross coupled type that outputs the first and second output signals and latches the states of the first and second output nodes.

In the configuration of the write driver control circuit, the single type latch unit includes: first pull-down means for turning on by a write driver enable signal enabled during the write operation to lower the common node to a ground level; First switching means turned on by the first data to connect between a first node and the common node; Second switching means turned on by the second data to connect between a second node and the common node; First pull-up means for turning on by the potential of the second output node to raise the first output node to a power supply voltage level; Third switching means turned on by a potential of the second output node to connect between the first output node and the first node; Second pull-up means for turning on by the potential of the first output node to raise the second output node to a power supply voltage level; And fourth switching means turned on by a potential of the first output node to connect between the second output node and the second node, wherein the driver control signal is transmitted through the first and second output nodes. It is preferable to output them.

In the configuration of the single type latch unit, it is preferable that the first pull-down means and the first to fourth switching means each comprise an NMOS transistor, and the first and second pull-up means each comprise a PMOS transistor. .

In the configuration of the write driver control circuit, the precharge control unit includes: third pull-up means for turning on the first output node to a power supply voltage level by being turned on by a precharge control signal enabled during the precharge operation; Fourth pull-up means for turning on the precharge control signal to raise the second output node to a power supply voltage level; And fifth switching means turned on by the precharge control signal to equalize the first and second output nodes.

In the configuration of the precharge control unit, it is preferable that the third and fourth pull-up means and the fifth switching means each comprise a PMOS transistor.

In the configuration of the write driver control circuit, the latch type output unit includes: first inverter means for inverting the first output signal and outputting the first driver signal; Second inverter means for inverting the first driver signal and outputting the first latch signal; Second pull-down means for turning on by the first driver signal to lower the first output node to a ground voltage level; Third inverter means for inverting the second output signal and outputting the second driver signal; Fourth inverter means for inverting the second driver signal and outputting the second latch signal; And third pull-down means for turning on by the second driver signal to lower the second output node to a ground voltage level.

In the configuration of the latch type output section, the second and third pull-down means are preferably composed of NMOS transistors, respectively.

In the configuration of the write driver control circuit, the latch type output unit includes: first inverter means for inverting the first output signal and outputting the first driver signal; Second inverter means for inverting the first driver signal and outputting the first latch signal; First combining means for combining the latch control signal and the first output signal to maintain an enable state during the write operation; Fourth pull-down means for turning on by the signal output from the first combining means to lower the first output node to a ground voltage level; Third inverter means for inverting the second output signal and outputting the second driver signal; Fourth inverter means for inverting the second driver signal and outputting the second latch signal; Second combining means for combining the latch control signal and the second output signal; And fifth pull-down means for turning on by the signal output from the second combining means to lower the second output node to the ground voltage level.

In the configuration of the latch output unit, the first combining means includes: fifth inverter means for inverting the latch control signal; And a first NOR gate for NOR combining the first output signal and the signal output from the fifth inverter means.

In the configuration of the latch output unit, the second combining means includes: sixth inverter means for inverting the latch control signal; And a second NOR gate for NOR-combining the second output signal and the signal output from the sixth inverter means.

In the configuration of the latch type output section, the fourth and fifth pull down means are preferably composed of NMOS transistors, respectively.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The structure of FIG. 3 is disclosed as an embodiment of the present invention, and in the embodiment of the present invention, the circuit 200 for controlling the write driver 300 has a single type latch structure.

In detail, the embodiment of FIG. 3 includes a buffer unit 100, a single type latch type write driver control unit 200, a write driver 300, and a column selector 400.

The buffer unit 100 buffers the data DATA input from the outside and transfers the data DATA to the global input / output line GIO.

The single type latch type write driver controller 200 amplifies the data transmitted from the global input / output line (GIO) during the write operation and outputs the signals DRV, LAT, DRVB, and LATB for controlling the write driver, and before the precharge operation. Up to latch the states of signals DRV, LAT, DRVB, and LATB, and precharge signals DRV, LAT, DRVB, and LATB during precharge operation.

For example, as illustrated in FIG. 4, the single type latch type write driver control unit 200 may include a precharge control unit 210, a single type latch unit 220, and a latch type output unit 230. have.

Here, the precharge control unit 210 is turned on by the precharge control signal PCG to raise the node ND_A to the power supply voltage VDD level, and is turned on by the precharge control signal PCG to turn on the node ND_B. A PMOS transistor P8 that raises the power supply voltage VDD level, and a PMOS transistor P9 that is turned on by the precharge control signal PCG to connect between the node ND_A and the node ND_B.

In addition, the single type latch unit 220 is turned on by the write driver enable signal BWEN and is applied to the data transferred from the NMOS transistor N11 and the global input / output true line GIOT that lowers the node ND_C to the ground voltage VSS level. NMOS transistor N12 that is turned on by the NMOS transistor N11 and the NMOS transistor N14, and is turned on by data transmitted from the global input / output bar line GIOB, thereby turning on the NMOS transistor N11 and the NMOS transistor N15. It is turned on by the potentials of the NMOS transistor N13 and the node ND_B connected therebetween, and is turned on by the potentials of the NMOS transistor N14 and the node ND_B connecting the NMOS transistor N12 and the PMOS transistor P10. To be turned on by the potential of the node ND_A to raise the node ND_A to the power supply voltage VDD level, thereby connecting the NMOS transistor N13 and the PMOS transistor P11. It may be composed of a NMOS transistor (N15), and a PMOS transistor (P11) which are turned on by the potential of the node (ND_A) increases the node (ND_B) to the power supply voltage VDD level.

In addition, the latch type output unit 230 is turned on by the inverter INV13 for inverting the potential of the node ND_A and outputting the inverted driver signal DRVB and the inverted driver signal DRVB to turn the node ND_A to the ground voltage VSS level. An inverter that inverts the potential of the node ND_B and the inverter INV14 that inverts the inverted driver signal DRVB output from the falling NMOS transistor N16, the inverter INV13, and outputs the latch signal LAT, and outputs the driver signal DRV ( INV15), an NMOS transistor N17 that is turned on by the driver signal DRV to lower the node ND_B to the ground voltage VSS level, and an inverter that inverts the driver signal DRV output from the inverter INV15 and outputs the inverted latch signal LATB. (INV16).

At this time, the latch type output unit 230 may be configured as shown in FIG.

Referring to FIG. 5, the latch type output unit 230 inverts the potential of the node ND_A and outputs the inverted driver signal DRVB to the inverter INV13 and the inverted driver signal DRVB output from the inverter INV13. Inverter INV14 outputting the signal LAT, inverter INV17 inverting the latch control signal LAT_CTRL, NOR gate NR1, and NOR gate NR1 combining the potential of the node ND_A with the output signal of the inverter INV17. Inverters INV15 and INV15 that turn on by the output signal of the inverter and invert the potentials of the NMOS transistor N18 and node ND_B that lower the node ND_A to the ground voltage VSS level and output the driver signal DRV. Inverter (INV16) that inverts the driver signal DRV outputted from the inverter) and outputs the inverted latch signal LATB, the inverter INV18 that inverts the latch control signal LAT_CTRL, and the potential of the node ND_B and the output signal of the inverter INV18. Noah to combine And an NMOS transistor N19 that is turned on by the output signal of the gate NR2 and the NOR gate NR2 to lower the node ND_B to the ground voltage VSS level. At this time, the write driver enable signal BWEN or the precharge control signal PCG may be used as the latch control signal LAT_CTRL.

As shown in FIG. 6, the write driver 300 includes a local input / output true line driver 310 and a local input / output bar line driver 320.

Here, the local input / output true line driver unit 310 is turned on by the driver control signal LAT to raise the local input / output true line LIOT to the core voltage VCORE level, which is the memory cell voltage, and the driver control signal DRV. The NMOS transistor N20 may be configured to be turned on to lower the local input / output true line LIOT to the ground voltage VSS level.

In addition, the local input / output bar line driver 320 is turned on by the driver control signal LATB and is turned on by the PMOS transistor P13 for raising the local input / output bar line LIOB to the core voltage VCORE level and the driver control signal DRVB. The NMOS transistor N21 may be configured to lower the local input / output bar line LIOB to the ground voltage VSS level.

The column selector 400 transfers data of the local input / output line LIO to the bit line BL by the column select signal YI.

An operation of an embodiment of the present invention having such a configuration will be described below with reference to FIG. 7.

First, during the precharge operation, all of the PMOS transistors P7 to P9 are turned on by the precharge control signal PCG, so that the node ND_A and the node ND_B are precharged to the power supply voltage level VDD.

Thereafter, the NMOS transistor N11 is turned on by the write driver enable signal BWEN during the write operation, so that an embodiment of the present invention senses, amplifies, and latches a potential difference of data transferred from the global input / output line pairs GIO and GIOB. do.

For example, when high level data is transferred from the global input / output true line GIOT and low level data is transferred from the global input / output bar line GIOB, the NMOS transistor N12 is turned on and the NMOS transistor N13 is turned on. Is turned off.

When the NMOS transistor N12 is turned on, a current path is formed from the node ND_A through the NMOS transistors N14, N12, and N11 to the ground voltage VSS line, so that the potential of the node ND_A reaches the ground voltage VSS level. Descend.

When the NMOS transistor N13 is turned off, since no current path is formed from the node ND_B to the ground voltage VSS line, the potential of the node ND_B maintains the core voltage VCORE level.

Therefore, since the driver control signal DRV becomes low level and the PMOS transistor P12 of the local input / output true line driver 310 is turned on, the local input / output true line LIOT rises to the core voltage VCORE level.

Then, since the driver control signal DRVB becomes high level and the NMOS transistor N21 of the local input / output bar line driver 320 is turned on, the local input / output line LIOB falls to the ground voltage VSS level.

On the other hand, when low level data is transferred from the global I / O true line GIOT and high level data is transferred from the global I / O bar line GIOB, the potential of the node ND_A maintains the power supply voltage VDD level, The potential of ND_B drops to the ground voltage VSS level.

Therefore, since the driver control signal DRV becomes high level and the NMOS transistor N20 of the local input / output true line driver 310 is turned on, the local input / output true line LIOT falls to the ground voltage VSS level.

Then, since the driver control signal DRVB becomes low level and the PMOS transistor P13 of the local input / output bar line driver unit 320 is turned on, the local input / output bar line LIOB rises to the core voltage VCORE level.

On the other hand, the node ND_A and the node ND_B are latched by the inverters INV13 and INV15 and the NMOS transistors N16 and N17 to a constant potential until the precharge control signal PCG is enabled in FIG. 4.

For example, as shown in FIG. 7, the write driver enable signal BWEN is enabled when the write driver enable signal BWEN is delayed and the global input / output true line (GIOT) transitions from the high level to the low level. It may occur to keep.

In this case, since the latch type output unit 230 of FIG. 4 latches the potential of the node ND_A from the time when the inverting driver signal DRVB is enabled, the node ND_A does not float.

That is, when the write driver enable signal BWEN is enabled while the global input / output true line GIOT is at the high level, the node ND_A is at a low level and the inversion driver signal DRVB is at a high level.

When the inversion driver signal DRVB goes high, the NMOS transistor N16 is turned on to lower the node ND_A to the ground voltage VSS level. The node ND_A is latched to the low level state by the inverter INV13 and the NMOS transistor N16.

Therefore, even when the global input / output true line GIOT transitions from the high level to the low level, the potential of the node ND_A is maintained at the low level, so that the node ND_A does not float.

Similarly, when the write driver enable signal BWEN remains enabled when the write driver enable signal BWEN is delayed and the global input / output bar line GIOB transitions from the high level to the low level, the node ND_B Since the potential is latched by the inverter INV15 and the NMOS transistor N17 from the time when the driver signal DRV is enabled, the node ND_B does not float.

As such, the latch type output unit 230 of FIG. 4 receives the driver signal DRV and the inverted driver signal DRVB to latch the nodes ND_A and ND_B, thereby delaying input of the write driver enable signal BWEN. The output nodes ND_A and ND_B of 220 are prevented from floating.

Similarly, the latch type output unit 230 of FIG. 5 maintains the write driver enable signal BWEN at a time when the write driver enable signal BWEN is delayed and the level of the global input / output lines GIOT and GIOB transitions. In this case, the potential of the nodes ND_A and ND_B is prevented from floating by latching the potentials of the output nodes ND_A and ND_B of the single type latch unit 220 while the latch control signal LAT_CTRL is enabled. have.

As described above, the embodiment of the present invention secures the timing margin of the data through the single type latch type write driver control unit 200 to transfer data input from the outside to the memory cell during the write operation, and operates the write driver 300. To control.

Here, the single type latch unit 210 may be configured in a cross-coupled form for comparatively amplifying and latching data transferred from the global input / output line pairs GIO and GIOB.

Therefore, since the single type latch type write driver control unit 200 has an area smaller than that of the conventional write driver control circuit 10 of FIG. 1, the area occupied by the semiconductor memory device may be reduced. have.

In addition, the embodiment of the present invention latches data at a time through the PMOS transistors P10 and P11 and the NMOS transistors N14 and N15 that are connected in a cross-coupled form during the write operation. There is an effect that can reduce the current consumption for.

In addition, the embodiment of the present invention does not need to use the delayed write driver enable signal DBWEN as shown in FIG. 1 during the latch operation, thereby reducing current consumption and area waste caused by using the delayed write driver enable signal DBWEN. Is effective.

As described above, since the circuit for controlling the write driver is configured as a circuit having a single latch type, the area occupied by the semiconductor memory device can be reduced.

In addition, since the present invention controls the write driver by latching data input through a circuit connected in the form of a single type latch, current consumption may be reduced during the write operation.

While the invention has been shown and described with reference to specific embodiments, the invention is not limited thereto, and the invention is not limited to the scope of the invention as defined by the following claims. Those skilled in the art will readily appreciate that modifications and variations can be made.

Claims (13)

A write driver control circuit for controlling an operation of a write driver that amplifies data of a global input / output line pair and transfers the data to a local input / output line pair during a write operation, In the write operation, a first output signal is output to a first output node by comparing first and second data of the global input / output line pairs having a differentially inputted first state, and outputting a first output signal to the first output node. A single type latch unit for comparing the second data and outputting a second output signal to the second output node; A precharge controller for equalizing and precharging the first and second output nodes during a precharge operation; And Outputting first and second driver signals and first and second latch signals for controlling the write driver using the first and second output signals during the write operation, and the first and second signals during the write operation. And a latch type output unit configured to latch a state of two output nodes. The method of claim 1, The single type latch unit compares first data of a high level and second data of a low level as data of the first state and outputs the first output signal, and first data of a low level as data of the second state. And a second data of high level and comparing the second data to the second output signal to output the second data. The method of claim 2, The single type latch unit is a cross-coupled latch for comparing the potential difference between the first and second data and outputting the first and second output signals, and latching states of the first and second output nodes. Light driver control circuit. The method of claim 3, wherein The single type latch unit, First pull-down means that is turned on by a write driver enable signal enabled during the write operation to lower the common node to ground level; First switching means turned on by the first data to connect between a first node and the common node; Second switching means turned on by the second data to connect between a second node and the common node; First pull-up means for turning on by the potential of the second output node to raise the first output node to a power supply voltage level; Third switching means turned on by a potential of the second output node to connect between the first output node and the first node; Second pull-up means for turning on by the potential of the first output node to raise the second output node to a power supply voltage level; And And fourth switching means turned on by a potential of the first output node to connect between the second output node and the second node. And outputting the driver control signals through the first and second output nodes. The method of claim 4, wherein And said first pull-down means and said first to fourth switching means are each composed of NMOS transistors, and said first and second pull-up means are each composed of PMOS transistors. The method of claim 1, The precharge control unit, Third pull-up means for turning on the first output node to a power supply voltage level by being turned on by a precharge control signal enabled during the precharge operation; Fourth pull-up means for turning on the precharge control signal to raise the second output node to a power supply voltage level; And And fifth switching means for turning on the precharge control signal to equalize the first and second output nodes. The method of claim 6, And said third and fourth pull-up means and said fifth switching means each comprise a PMOS transistor. The method of claim 1, The latch type output unit, First inverter means for inverting the first output signal and outputting the first driver signal; Second inverter means for inverting the first driver signal and outputting the first latch signal; Second pull-down means for turning on by the first driver signal to lower the first output node to a ground voltage level; Third inverter means for inverting the second output signal and outputting the second driver signal; Fourth inverter means for inverting the second driver signal and outputting the second latch signal; And And third pull-down means for turning on the second driver signal to lower the second output node to a ground voltage level. The method of claim 8, And said second and third pull-down means each comprise an NMOS transistor. The method of claim 1, The latch type output unit, First inverter means for inverting the first output signal and outputting the first driver signal; Second inverter means for inverting the first driver signal and outputting the first latch signal; First combining means for combining the latch control signal and the first output signal to maintain an enable state during the write operation; Fourth pull-down means for turning on by the signal output from the first combining means to lower the first output node to a ground voltage level; Third inverter means for inverting the second output signal and outputting the second driver signal; Fourth inverter means for inverting the second driver signal and outputting the second latch signal; Second combining means for combining the latch control signal and the second output signal; And And fifth pull-down means which is turned on by the signal output from the second combining means to lower the second output node to the ground voltage level. The method of claim 10, The first combining means, Fifth inverter means for inverting said latch control signal; And And a first NOR gate for NOR-combining the first output signal and the signal output from the fifth inverter means. The method of claim 10, The second combining means, Sixth inverter means for inverting the latch control signal; And And a second NOR gate for NOR-combining the second output signal and the signal outputted from the sixth inverter means. The method of claim 10, And said fourth and fifth pull-down means are each composed of NMOS transistors.

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