KR100388225B1 - Output control circuit of sense amplifier - Google Patents

Abstract

PURPOSE: An output control circuit of a sense amplifier is provided to transfer an output signal of the sense amplifier to an output buffer within a short period of time by minimizing delay factor and reducing the loss of current. CONSTITUTION: A memory device includes a plurality of sense amplifiers(10A-10N) for amplifying data of a corresponding bit line and an output buffer(2) for transferring output data of the sense amplifiers(10A-10N) to peripheral devices. An output control circuit of the sense amplifier includes a plurality of level control circuits(100A,100B) and a plurality of signal matching circuits. The level control circuits(100A,100B) are installed at an arbitrary position of a common output node of the sense amplifiers in order to maintain a voltage of the common output node in a particular state. The signal matching circuits perform a process for matching a delay time by delaying the data loaded on the memory bit line.

Description

Sensor amplifier output adjustment circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to sense amplifier output adjustment, and more particularly, to a sensor amplifier output adjustment circuit suitable for a high speed SRAM system requiring a fast access time in a circuit configuration for quickly delivering a sensor amplifier output to an output buffer.

In general, a sense amplifier or a sense amplifier refers to a circuit that detects a voltage or current level of an input signal as a threshold value, and then amplifies and outputs the input signal, and may also include a function of detecting only an input signal in a specific time domain. do.

Such a sense amplifier is generally used for a micro output signal such as a storage device, but an example of the case applied to the storage device is shown in FIG.

Referring to FIG. 1, the outputs of the sensor amplifiers are commonly tied to the output terminals of the sensor amplifiers 1A to 1N of different blocks, and are provided as inputs of the output buffer 2.

Therefore, the output signals of the respective sensor amplifiers 1A to 1N are transmitted to the output buffer 2 through a common output node. There are two kinds of initial conditions of the common output nodes of the sense amplifiers 1A to 1N. It can be a full voltage of V, or a half voltage of VCC.

At this time, if the initial condition according to the output of the sense amplifier is maintained at the full voltage state of VCC. For example, if the VCC voltage is assumed to be 5V and the low state is assumed to be the ground potential, the output state of the sense amplifier is 5V. As switching to 0V causes a problem that the delay factor increases in the transmission of the output signal of the sensor amplifier.

On the other hand, when the initial condition according to the output of the sense amplifier is maintained at the half voltage of the VCC, the delay time according to the voltage switching is reduced, but depending on the method of making the sensor amplifier output signal or the half voltage of the VCC, The output signal switching is different, which also causes a problem that the delay factor is increased in the transmission of the output signal of the sensor amplifier.

An object of the present invention for solving the above problems is to use a method of maintaining the initial condition according to the output of the sense amplifier to the half-voltage state of the VCC, but adding a switching circuit to control the output signal of the sensor amplifier Therefore, the present invention provides a sensor amplifier output adjustment circuit for quickly transferring the sensor amplifier output to an output buffer.

In order to achieve the above object, a feature of the present invention is a one-to-one connection to a plurality of memory bit lines, and a plurality of sense amplifiers for amplifying and outputting data carried on the corresponding bit lines, and connected to a common output terminal of the sense amplifier. In a memory device having an output buffer for transmitting data output from an arbitrary sense amplifier to another peripheral device:

A predetermined number of level adjusting units provided at arbitrary positions of the common output node of the sense amplifier and maintaining the voltage of the common output node in a specific state for a predetermined time from the time when an address change is detected. In addition, a plurality of delay times for matching data delayed at the amplification output of a corresponding memory amplifier to the common output node in response to the time delay generated by the level adjuster are delayed. It includes a signal matching unit.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2 is an exemplary view showing a position where the sensor amplifier output adjustment circuit according to the present invention is occupied, which is located at both ends of the output nodes of the sensor amplifiers 10A to 10N and is positioned at the position of adjusting the level of the sensor amplifier output node as a whole. Thus less impact.

The detailed configuration of the sensor amplifier output adjustment circuit according to the present invention as described above will be described with reference to FIG. 3.

First, the characteristics of each of the input signals A to F will be described. The signals represented by reference numerals A, B, and D are signals related to address transition detectors (hereinafter referred to as ADTs). It is a signal that is changed to a low signal for a predetermined time and then restored to a high state at the portion where the address change is detected.

The signal denoted by reference number C is a signal for distinguishing a lead from a light. The signal is maintained in a high state in the read mode and a low state in the write mode.

The signal represented by reference numeral E is a signal for enabling the output operation of the sequencer amplifier. When the signal is in a high state, it is enabled.

In addition, the signal represented by the reference number F is an actual output signal of the sensor amplifier.

Looking at the configuration of the sensor amplifier output adjustment circuit according to the present invention shown in Figure 3, it can be seen that it is largely composed of a level adjusting circuit (100A) and a signal matching unit additionally provided to each sense amplifier.

At this time, the level adjusting circuit 100A receives the first signal A and the second signal B generated from an ADT (not shown), performs a negative AND operation, and outputs the calculated value. A first inverter INV1 that receives the output signal of the first NAND gate NAND1 and inverts the output signal, a second inverter INV2 that receives the read / write signal C, and inverts the output signal; A third inverter INV3 that receives the output signal of the second inverter INV2 and inverts the output signal, a fourth inverter INV4 that receives the inverted output signal of the first inverter INV1 and outputs the inverted signal; A fifth inverter (INV5) for receiving the output signal of the third inverter (INV3) and inverts the output signal and the input and output signals of the fifth inverter (INV5) as a control signal to turn on / off operation, the fifth inverter ( When the output signal of INV5) is low, Turn on / off the first transmission gates P1 and N1 and the input / output signal of the fourth inverter INV4 as a control signal, and turn on / off when the input signal of the fourth inverter INV4 is low. Second vibration gates P2 and N2 for receiving and outputting output signals of the first transmission gates P1 and N1 and input signals of the first transmission gates P1 and N1 to satisfy an initial voltage condition. 6 to 8 inverters INV6 to INV8 and the second transfer gates P2 and N2 provided to the output terminal of the second transfer gates P2 and N2 by repeating the delay for a predetermined time and repeating the inversion process. The ninth inverter INV9 receives and outputs the output signal and inverts it to the input terminal of the first transfer gates P1 and N1.

In this case, the first transfer gates P1 and N1 include a first PMOS transistor P1 and a first NMOS transistor N1, and the second transfer gates P2 and N2 include a second PMOS transistor P2. And the first NMOS transistor N2.

In addition, the signal matching unit included in the output node of each sense amplifier receives the third signal D generated by the ADT and the sensor amplifier enable signal E, and performs a negative AND operation to output the calculated value. The NAND2, the tenth inverter INV10 that receives the inverted output signal F of the actual sensor amplifier and inverts the output signal, and the eleventh inverter that receives the inverted output signal of the tenth inverter INV10 and outputs the inverted signal. Turn on / off according to the state of INV11, the twelfth invert INV12 that receives the inverted output signal of the second NAND gate NAND2, and outputs the inverted signal, and the input / output signal of the twelfth inverter INV12. In operation, when the output signal of the twelfth inverter INV12 is in a high state, it is turned on and is configured of third transmission gates PA and PN that receive and output the output signal of the eleventh inverter INV11.

In this case, the third transfer gates PA and PN may include a PMOS transistor PA and an NMOS transistor NA, and the output signal of the third transfer gates PA and PN may be controlled by the level adjustment circuit 100A. It is provided as an input to the first transfer gates P1 and N1.

Looking at the preferred operation of the sensor amplifier output adjustment circuit according to the present invention configured as described above are as follows.

When an address change is detected in an ATD (not shown), the first signal A, the second signal B, and the third signal D fall to a low state.

At this time, the output signal of the first NAND gate NAND1 is switched to the high state, and thus the output signal of the first inverter INV1 is turned to the low state. Since the output signal of the first first inverter INV1 is low, the second PMOS transistor P2 of the second transfer gates P2 and N2 is turned on.

In addition, the second NMOS transistor N2 of the second transfer gates P2 and N2 also maintains a turn-on state. The reason is that the output signal of the fourth inverter INV4 receiving the output signal of the first inverter INV1 is input. Since the output signal of the first inverter INV1 is low, the fourth inverter INV4 is output. This is because the output signal of becomes high.

Since the time at which the sense amplifier is operated is the read operation mode, it is assumed that the read / write signal C proceeds to the high state, that is, the read operation mode, when the address change is detected by the ATD as described above.

Accordingly, a signal input to the fifth inverter through the second inverter INV2 and the third inverter INV is maintained in a high state, and the transistors constituting the first transfer gates P1 and N2 are controlled by the signal state. They are all turned on.

As described above, all transistors constituting the first and second transfer gates are turned on for a predetermined time by the first signal A and the second signal B generated from the time when the address change is detected by the ATD. Done.

At this time, it is assumed that the data previously output from the sense amplifier is transferred to the output buffer through the third transmission gates PA and NA, and it is assumed that the logic state of the data previously transmitted to the output buffer is high.

Accordingly, since data input to the data input terminal of the first transfer gates P1 and N1 is in a high state, data output from the sixth inverter INV6 is converted into a low state, and then an output state of the seventh inverter INV7 is changed. Is switched to the high state again, and then the output terminal of the second transfer gates P2 and N2 receives the low state, which is the output signal of the eighth inverter INV8.

In this case, since the sixth inverter INV6 is small in size, that is, the resistance is large, the sixth inverter INV6 serves to reduce the flow of current at the voltage position in the half-high state, and at the same time, delay the signal with the seventh inverter INV7. It plays a role in keeping time.

This delay of the signal can quickly maintain the state of the half VCC voltage at the output node of the sense amplifier. That is, when the width of the signal generated by the ATD is small, the overall switching width of the output signal of the sense amplifier is determined by how quickly the output node of the sense amplifier moves to the half VCC.

As a result, even when the state of the input signal of the sixth inverter INV6 is low or high, when the first and second transfer gates are turned on, the sixth to eighth inverters INV6 to INV8 are connected to each other. The output nodes of the commonly sensed amplifiers maintain the state of the half VCC voltage.

Because, due to the operation characteristics of the transfer gate, the voltage state of the input / output terminal maintains the coin state in the turn-on state, so that the output node of the sense amplifier is the initial voltage half through the loop composed of the sixth to eighth inverters INV6 to INV8. The state of the VCC voltage is maintained.

On the other hand, the output of the ninth inverter INV9 maintains a short circuit state because the voltage is not applied to the input terminal when the transfer gate is turned on. However, when the transfer gate is turned off, the sixth to eighth inverters are turned off. A loop is formed to compensate for the output signal of the sense amplifier that changes due to INV6 to INV8.

In response to the operation of the level adjustment circuit operating in this manner, the signal matching unit simply performs a function of matching a signal output from the sense amplifier to a time delayed by the level adjustment circuit.

Providing the sensor amplifier output adjustment circuit according to the present invention operating as described above, while using the method of maintaining the initial condition according to the output of the sense amplifier in the half voltage state of VCC, the delay element can be reduced as much as possible and the current loss is reduced. Can be reduced.

In addition, the output signal of the sensor amplifier can be quickly transmitted to the output buffer.

1 is a diagram illustrating a connection configuration between a conventional sense amplifier and an output buffer.

2 is a diagram illustrating a connection configuration between a sense amplifier and an output buffer according to the present invention.

3 is a detailed circuit diagram of the configuration of FIG. 2 for adjusting the sensor amplifier output according to the present invention.

* Explanation of symbols for main parts of the drawings

INV1 to INV12: Inverter

NAND1, NAND2: NAND Gate

P1, P2, PA: PMOS transistor

N1, N2, NA: NMOS transistor

Claims (9)

A plurality of sense amplifiers, which are connected one-to-one to a plurality of memory bit lines and amplify and output data carried on the corresponding bit lines, are connected to a common output terminal of the sense amplifier, and the data output from any sense amplifier is different. In a memory device having an output buffer for delivery to peripheral devices: A predetermined number of level adjusting units provided at arbitrary positions of the common output node of the sense amplifier and maintaining the voltage of the common output node in a specific state for a predetermined time from the time when an address change is detected; Delay time that is additionally provided in each sense amplifier and delays the time in amplifying output of the data in the memory bit line to the common output node in response to the time delay generated in the level adjuster. Sensor amplifier output adjustment circuit comprising a plurality of signal matching for matching the. The method of claim 1, The level adjusting unit may include: a first transmission gate configured to receive a signal output through the signal matching unit according to the first control signal input thereto and to output the signal during turn-on operation; A second transmission gate receiving an output signal of the first transmission gate and outputting the output signal during a turn-on operation according to an input second control signal; First control signal generation means for generating a first control signal for turning on / off control of said first transfer gate when reading data carried on a memory bit line; Second control signal generating means for generating a second control signal for turning on / off control of the second transfer gate when detecting a change in address; And When the first transmission gate and the second transmission gate are turned on, the input signal of the first transmission gate is input and inverted after a predetermined time delay to the output terminal of the second transmission gate. And a voltage holding means for maintaining a voltage level of the signal at a voltage level of the output terminal of the second transfer gate. The method of claim 2, And a compensation means for compensating for the output signal of the sense amplifier distorted by the voltage holding means when the first and second transfer gates are turned off. The method of claim 2, The second control signal generating means includes: a first NAND gate which receives a first signal and a second signal generated when an address change is detected, performs an AND logic operation, and outputs an operation value; A first inverter which receives the output signal of the first NAND gate, inverts the output signal, and outputs the inverted output to the first control signal input terminal of the second transfer gate; And And a second inverter configured to receive the output signal of the first inverter, invert it, and output the inverted signal to the second control signal input terminal of the second transmission gate. The method of claim 2, The first control signal generating means includes: a third inverter which receives a signal according to a read or write operation of a memory, receives an input, and inverts the output; A fourth inverter that receives the output signal of the third inverter, inverts the output signal, and outputs the inverted output to the second control signal input terminal of the first transmission gate; And And a fifth inverter configured to receive the output signal of the fourth inverter, invert the output signal, and output the inverted signal to the first control signal input terminal of the first transmission gate. The method of claim 2, The voltage holding means includes a delay element for receiving a signal output from the signal matching unit and delaying the signal for a predetermined time and maintaining the signal at the specific voltage; A drive for receiving the output signal of the delay element and inverting the voltage of the phase opposite to the voltage applied to the input terminal of the first transfer gate during turn-on operation of the first and second transfer gates and providing the output signal to the output terminal of the second transfer gate. Sensor amplifier output adjustment circuit, characterized in that consisting of elements. The method of claim 6, The delay device has a very small invert device and a relatively large invert device are connected in series, and an input terminal of the very small invert device receives a signal output from the signal matching unit, and has a large invert device. The output terminal of the sensor amplifier output adjustment circuit, characterized in that connected to the data input terminal of the drive element. The method according to any one of claims 1 to 7, And said specific voltage means a voltage per half of a driving power supply. The method of claim 1, Each of the signal matching units may include a transmission gate configured to receive a signal amplified by a sense amplifier during a turn-on operation according to an input control signal, and transmit the received signal to the common output node; A control signal generator which receives a signal generated at the time of detecting the address change and a sense amplifier enable signal and provides a control signal of the transmission gate; And And a time delay element for matching the signal output from the sense amplifier to a time delayed by the level adjustment unit and transmitting the signal to the transmission gate.