KR970071811A - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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Publication number
KR970071811A
KR970071811A KR1019960012000A KR19960012000A KR970071811A KR 970071811 A KR970071811 A KR 970071811A KR 1019960012000 A KR1019960012000 A KR 1019960012000A KR 19960012000 A KR19960012000 A KR 19960012000A KR 970071811 A KR970071811 A KR 970071811A
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KR
South Korea
Prior art keywords
unit
level
adjusting
bias
nmos transistors
Prior art date
Application number
KR1019960012000A
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Korean (ko)
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KR100214477B1 (en
Inventor
신종수
Original Assignee
문정환
Lg 반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 문정환, Lg 반도체주식회사 filed Critical 문정환
Priority to KR1019960012000A priority Critical patent/KR100214477B1/en
Publication of KR970071811A publication Critical patent/KR970071811A/en
Application granted granted Critical
Publication of KR100214477B1 publication Critical patent/KR100214477B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14—Dummy cell management; Sense reference voltage generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits

Abstract

본 발명의 반도체 메모리장치는, 게이트가 접지된 다수개의 엔모스트랜지스터를 직렬연결한 하이셀부와, 게이트가 전압(Vcc)와 접속된 다수개의 엔모스 트랜지스터를 직렬연결한 로우셀부와, 상기 하이셀부의 전압 레벨을 조절하기 위한 제1바이어스부와, 상기 로우셀부의 전압레벨을 조절하기 위한 제2바이어스부와, 상기 제1 및 제2바이어스부의 출력을 입력으로 하여 중간레벨을 갖도록 조정하고 이를 상기 메인 센스 엠프부로 출력하여 하이데이타와 로우데이타를 정확히 센싱할 수 있도록 하기 위한 레퍼런스 레벨 조정부를 포함하여 구성되며, 상기 레퍼런스 레벨 조정부를 통해 상기 메인 센스 엠프부에 입력되는 레퍼런스 레벨을 하이셀과 로우셀의 중간레벨로 정확히 저정함으로써 센싱의 신뢰성을 높일 수 있는 효과가 있다.A semiconductor memory device according to the present invention includes a high-cell portion in which a plurality of NMOS transistors having a gate connected in series are serially connected, a low-cell portion in which a plurality of NMOS transistors having a gate connected to a voltage Vcc are connected in series, A second bias unit for adjusting the voltage level of the row cell unit; and a second bias unit for adjusting the voltage level of the first and second bias units to have an intermediate level, And a reference level adjusting unit for outputting the main level data to the main sense amplifier unit and accurately sensing the high data and the low data. The reference level inputted to the main sense amplifier unit through the reference level adjusting unit is referred to as a high- So that the reliability of the sensing can be improved.

Description

반도체 메모리장치Semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제3도는 본 발명에 의한 반도체 메모리장치의 구성을 도시한 것이고, 제4도는 제2도의 상세회로를 도시한 것이다.FIG. 3 shows a configuration of a semiconductor memory device according to the present invention, and FIG. 4 shows a detailed circuit of FIG.

Claims (2)

게이트가 접지된 다수개의 엔모스 트랜지스터를 직렬연결한 하이셀부와, 게이트가 전압(Vcc)와 접속된 다수개의 엔모스 트랜지스터를 직렬연결한 로우셀부와, 상기 하이셀부의 전압 레벨을 조절하기 위한 제1바이어스부와, 상기 로우셀부의 전압레벨을 조절하기 위한 제2바이어스부와, 상기 제1 및 제2바이어스부의 출력을 입력으로 하여 중간레벨을 갖도록 조정하고, 이를 상기 메인 센스 엠프부로 출력하여 하이데이타와 로우데이타를 정확히 센싱할 수 있도록 하기 위한 레퍼런스 레벨 조정부를 포함하여 구성된 것을 특징으로 하는 반도체 메모리장치.A high-cell section in which a plurality of NMOS transistors having a gate connected to each other are serially connected, a low-cell section in which a plurality of NMOS transistors having a gate connected to a voltage Vcc are connected in series, A second bias unit for adjusting a voltage level of the row cell unit and an output of the first and second bias units to have an intermediate level and outputting the intermediate level signal to the main sense amplifier unit, And a reference level adjusting unit for accurately sensing data and low data. 제1항에 있어서, 상기 레퍼런스 레벨 조정부는 상기 제1 및 제2바이어스부의 출력측 사이에 두개의 동일한 저항을 직렬연결하여 구성된 것을 특징으로 하는 반도체 메모리장치.2. The semiconductor memory device according to claim 1, wherein the reference level adjusting unit is configured by serially connecting two identical resistances between the output sides of the first and second bias units. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960012000A 1996-04-19 1996-04-19 Semiconductor memory device KR100214477B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960012000A KR100214477B1 (en) 1996-04-19 1996-04-19 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960012000A KR100214477B1 (en) 1996-04-19 1996-04-19 Semiconductor memory device

Publications (2)

Publication Number Publication Date
KR970071811A true KR970071811A (en) 1997-11-07
KR100214477B1 KR100214477B1 (en) 1999-08-02

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Application Number Title Priority Date Filing Date
KR1019960012000A KR100214477B1 (en) 1996-04-19 1996-04-19 Semiconductor memory device

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KR (1) KR100214477B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100388225B1 (en) * 1996-11-12 2003-10-04 주식회사 하이닉스반도체 Output control circuit of sense amplifier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100388225B1 (en) * 1996-11-12 2003-10-04 주식회사 하이닉스반도체 Output control circuit of sense amplifier

Also Published As

Publication number Publication date
KR100214477B1 (en) 1999-08-02

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