JP2690060B2 - Semiconductor circuit - Google Patents

Description

The present invention relates to a semiconductor circuit that uses a signal pair of an intermediate level with respect to a power supply voltage, and facilitates the connection of each circuit so that the original performance of each circuit can be sufficiently exhibited. A circuit comprising first and second MOS transistors of the same conductivity type connected in series between a first power supply and a second power supply having a lower potential, wherein A first input signal having an intermediate potential between the first power supply and the second power supply is input to the gate of the first MOS transistor, and the gate of the second MOS transistor receives the first input signal. A second input signal, which is at an intermediate potential between the power supply and the second power supply and has a phase opposite to that of the first input signal, is input, and from the node of the first and second MOS transistors,
The current of each of the first and second MOS transistors is set so that an output signal which is an intermediate potential between the first power supply and the second power supply and which is a level of the first input signal is output. It is characterized in that the driving ability is set.

[Industrial applications]

The present invention relates to a semiconductor circuit that utilizes an intermediate level signal pair with respect to a power supply voltage.

Many circuits generate an intermediate level output of 2.5V, 3.5V, etc. when the power supply voltage is 5V. Also, when one output is H (high), the other is L (low), and a pair of signals with opposite phase is input / output. There are many circuits that do.

[Conventional technology]

When constructing a circuit using a pair of intermediate level signals, it is necessary to optimize the signal potential between the circuits. For example, in order to input the circuit A which produces the output of the intermediate level V ₁ to the circuit C, the input level of the circuit C is set to V ₁ , or if the input level of the circuit C is the intermediate level V ₃ , the output level of the circuit A is V ₃
Or both of them, that is, the input / output level is set to the intermediate level V ₄ and the output level of the circuit A and the circuit C are changed.
It is necessary to set the input level of V to V ₄ .

Conventionally, in order to optimize the circuit input / output signal potential, the circuit constants of the circuit input / output section are optimized. However, if this is done, there are problems such that the original performance of each circuit cannot be sufficiently exhibited, and the circuit configuration is restricted.

Also, the output is at the intermediate level V ₁ and the output is at the intermediate level.
In some cases, each output of the circuit B of V ₂ is input to the circuit C. In this case, the method of optimizing by changing the circuit constants of the input / output section of each circuit is a matter of matching Occurs and is quite troublesome.

[Problems to be solved by the invention]

As described above, according to the conventional method, it is impossible to freely configure a circuit when configuring a semiconductor circuit using an intermediate level signal pair, and a complicated circuit is required to configure a high performance circuit.

Therefore, the present invention facilitates the connection of the respective circuits,
The purpose is to ensure that the original performance of each circuit is fully exerted.

[Means for solving the problem]

The configuration of the semiconductor circuit of the present invention comprises a circuit in which two MOS transistors of the same conductivity type are connected in series between a first power source and a second power source, and a circuit between the first power source and the second power source is provided. Is added to the gates of the two MOS transistors, and the connection point of the two MOS transistors serves as the output end of the level-shifted signal pair.

FIG. 1 shows a semiconductor circuit of the present invention. (A) is an intermediate level shift circuit that lowers the intermediate level input signal pair S, to a desired intermediate level signal pair S _N , _N , and (b) is the intermediate level input signal pair S, It is an intermediate level shift circuit that raises the signal pair _SP , _{P of a} higher desired intermediate level.

In these figures, T _N is an N-channel MOS transistor, T _P is a P-channel MOS transistor ( ₁ , ₂ , ... Are subscripts for distinguishing each other), and as shown in FIG. b) is composed of two sets of two P-channel MOS transistors connected in series, the gate of each transistor receives the input signal S, and the series connection point of each set serves as an output terminal.

In (a), the signal S is a series connection circuit T _N1 and T _N2 , T _N3 and T _N4
Power supply side transistor T _N1 and ground side transistor T _N4
In addition, the signal is applied to the ground side transistor T _N2 and the power supply side transistor T _N3, that is, the power supply side and the ground side are reversed. The same applies to (b), and the signal S, is the series connection circuit T _P1.
, And the gates of T _P2 , T _P3, and T _P4 are added to S, with the power supply side and the ground side reversed.

[Action]

In this circuit, when the input signal pair S, is at an intermediate level with respect to the power supply V _{CC as} shown in FIG. 2, the signal pair S _N , _N having a lower potential is output in FIG. 1 (a), In FIG. 1 (b), a signal pair S _P , _P having a higher potential is output. The degree of high / low is determined by the ratio of the current drivability of a pair of transistors connected in series.

Current drive capacity is transistor size (gate length),
In the series connection circuit, the level shift amount of the output signal pair with respect to the input signal pair can be set to a desired value because it is determined depending on whether the transistor is on the power supply side or the ground side (gate-source voltage). However, since the N-channel transistor is used in (a), the output signal S _N , _N drops below the threshold voltage of the transistor from the input signal S, and in (b) the P-channel transistor is used, the output Signals S _P and _P are input signals
It rises above S, above the threshold voltage of the transistor, and cannot go above or below it.

By using this circuit, in the circuit utilizing the intermediate level signal pair, the input / output signal potential can be optimized without changing the configuration of the input / output section of the circuit. For example, if the output signal levels of the circuits A and B are V ₁ and V ₂ , and the optimum input signal level of the circuit C that receives these signals is V ₃ , then V ₁ → V ₃ , through the circuit of FIG. It suffices to perform the level shift of V ₂ → V ₃ , and it is not necessary to change the circuit configuration of the input / output section of the circuits A to C.

〔Example〕

FIG. 3 shows an embodiment of the present invention. Some memory chips have a plurality of cell arrays, and in this example, there are four cell arrays. The read output of each cell array is the sense amplifiers 11-14.
Output SA and ▲ ▼ to SE and ▲ ▼, one of the read outputs of these cell arrays is selected and input to the sense amplifier 16, and the outputs SF and ▲ ▼ of the amplifier are output to the outside of the chip. Due to the arrangement of the cell array on the chip, the cell array 4 is close to the output end (sense amplifier 16), but the cell arrays 1 to 3 are far from the output end, and signal attenuation may occur. In such a case, a method of intermediate amplification is adopted. The sense amplifier 15 is for the intermediate amplification. When the intermediate amplification is performed, a significant level difference may occur as compared with the case where it is not performed, and the sense amplifier has a characteristic that the output level changes depending on the input level. In such a case, the level shift circuit of the present invention is effective. is there. Transistors TS ₁ and TS ₂ , TS ₃ and TS ₄ , TS ₅ and TS ₆ ,, T
S ₇ and TS ₈ are the level shift circuits, and sense amplifier 1
Input 6 at the same level and at an optimum level for the sense amplifier. TT ₇ and TT ₈ , TT ₉ and TT ₁₀ are transistors forming a selection gate, and D and E are selection signals.

Only one of the signals A to C becomes H, whereby one output pair of the sense amplifiers 11 to 13 is selected and added to the sense amplifier 15. Further, one of the signals D and E becomes H, which causes the output pair SD of the sense amplifiers 14 and 15 to be
One of ▼, SE and ▲ ▼ that is level-shifted is selected and added to the sense amplifier 16. Level shift circuit TS ₁
By adding ~ TS ₄ , TS ₅ ~ TS ₈ , the level of the signal input to the sense amplifier 16 can be made the same, and the sense amplifier 16 can be set to the optimum circuit constant for that one input signal level. .

The level shift circuit shown in FIG. 1 can be used for purposes other than matching the input signal levels. For example, in a transfer gate using an N-channel MOS transistor, it is preferable that the source / drain potential is lower than the gate potential because there is no problem such as V _th drop, but for this purpose, transfer is performed using the first level shift circuit. It is effective to lower the signal potential.

FIG. 4 shows a circuit example of the sense amplifier of FIG. It is composed of P-channel MOS transistor T ₁ through T ₄ and N-channel MOS transistor T ₅ through T ₁₀ as shown. T ₁ and
T ₂ , T ₃ and T _{4 form} a current mirror, and T ₅ and T ₆ , T ₇ and T ₈ are driver transistors for receiving the input signal pair S _i and _i . The transistors T ₉ and T ₁₀ expand the operating margin by preventing the potential of the virtual ground point (common source of T ₅ and T ₆ , T ₇ and T ₈ ) from fluctuating much even if the power supply voltage fluctuates. The output signal pair S ₀ , ₀ is an expanded version of the input signal pair S _i , _i , which is higher than its high potential side and lower than its low potential side.

FIG. 5 shows another embodiment of the present invention, in which transistors T _N5 , T _N6 , T _P5 and T _P6 are added to the circuit of FIG. 1, which are ground side in (a) and power source side in (b). Are inserted in series.
With this, in (a) of the transistor on the ground side,
In (b), the current drive capability of the transistor on the power supply side is reduced, and the level shift amount is small. These may be connected in parallel instead of being connected in series, and this increases the current drive capability of the transistors on the ground side and the power supply side and increases the level shift amount.

〔The invention's effect〕

As described above, according to the present invention, the level of the intermediate level signal pair can be shifted up / down, and in the semiconductor circuit utilizing the intermediate level signal pair, the connection of the input and output terminals of each circuit can be simplified. Can be done,
The input / output section of each circuit can have an optimum circuit configuration without considering the input / output levels, and the original performance of each circuit can be sufficiently exhibited.

[Brief description of the drawings]

1 is a circuit diagram showing a semiconductor circuit of the present invention, FIG. 2 is a characteristic diagram for explaining the operation, FIG. 3 is a circuit diagram showing an embodiment of the present invention, FIG. 4 is a circuit diagram of a sense amplifier, FIG. 5 is a circuit diagram showing another embodiment of the present invention. In FIG. 1, T _N is an N-channel MOS transistor, T _P is a P-channel MOS transistor, S, is an input signal pair, S _N , _N and
S _P and _P are output signal pairs.

Claims (2)

(57) [Claims] 1. A first power supply and a second power supply of the same conductivity type connected in series between a first power supply and a second power supply having a lower potential.
A first input signal having an intermediate potential between the first power supply and the second power supply is input to the gate of the first MOS transistor, A second input signal, which has an intermediate potential between the first power supply and the second power supply and has a phase inverted from that of the first input signal, is input to the gate of the MOS transistor. And a potential midway between the first power supply and the second power supply from the node of the second MOS transistor,
The current driving capability of each of the first and second MOS transistors is set so that an output signal that is a level of the input signal of 1 is output. 2. A circuit comprising third and fourth MOS transistors of the same conductivity type connected in series between the first power supply and the second power supply, the gate of the third MOS transistor. Is input with the second input signal, the gate of the fourth MOS transistor is input with the first input signal, and the output from the node of the third and fourth MOS transistors It is characterized by further comprising a second circuit in which the current driving capability of each of the third and fourth MOS transistors is set so that a second output signal whose phase is inverted from that of the signal is output. The semiconductor circuit according to claim 1.