JPH0385817A - Semiconductor circuit - Google Patents

Abstract

PURPOSE:To facilitate a circuit connection and to sufficiently enhance the substantial performance of each circuit by constituting each series connection point of 2 sets of series connection circuits to be output terminals for signal pairs subjected to level shift. CONSTITUTION:An intermediate level shift circuit (a) decreasing an input signal pair S, the inverse of S of an intermediate level into a signal pair SN, the inverse of SN of a lower desired intermediate level is by employing 2 sets of series circuits each comprising 2 N-channel MOS transistor(TR) TN, and an intermediate level shift circuit (b) increasing the input signal pair S, the inverse of S of the intermediate level into a signal pair SP, the inverse of SP of a higher desired intermediate level is constituted by employing 2 sets of series circuits each composed 2 P-channel MOS transistor(TR) TP. Then the gates of the TRs TN, TP receive the input signals S, the inverse of S and series connecting points of each set are used as output terminals. Thus, the connection of respective circuits is facilitated and the substantial performance of each circuit is sufficiently enhanced.

Description

[Detailed Description of the Invention] [Summary of the Invention] Regarding a semiconductor circuit that uses intermediate level signal pairs with respect to a power supply voltage, an object of the present invention is to facilitate the connection of each circuit and to fully utilize the original performance of each circuit. In order to achieve The output of a pair of signals is added to the gate of each transistor on the side so that the power supply side and the ground side are reversed in one set and the other set, and the level of each series connection point of these two sets of series connection circuits is shifted. This is the configuration that serves as the end.

(Industrial Application Field) The present invention relates to a semiconductor circuit that utilizes a signal pair at an intermediate level with respect to a power supply voltage.

There are many circuits that generate intermediate level outputs such as 2.5V and 3.5V when the power supply voltage is 5■, and one of the outputs is H (
There are many circuits that input/output pairs of signals that are in opposite phases, such as when one signal is high (high), the other signal is low (low).

[Prior Art] When configuring a circuit that uses a pair of intermediate level signals, it is necessary to optimize the signal potential between the circuits.For example, circuit A that produces an output of intermediate level 1 is input to circuit C. To do this, either set the input level of circuit C to V, or if the input level of circuit C is an intermediate level (3), change the output level of circuit A to (3), or do both of these, i.e., change the input/output level to an intermediate level. It is necessary to set the level V4 and the output level of circuit A and the input level of circuit C to 4.

Conventionally, in order to optimize the circuit input/output signal potential, circuit constants of the circuit input/output section are optimized.

However, if this is done, there are problems such as not being able to fully demonstrate the original performance of each circuit, and restrictions on the circuit configuration.

There are also cases where the outputs of circuit A, whose output is at intermediate level ■, and circuit B, whose output is at intermediate level v2, are input to circuit C. In this case, the circuit constants of the input/output sections of each circuit may be changed. However, the method of optimizing based on the target results in the problem of deciding which one to match, which is quite troublesome.

[Problems to be Solved by the Invention] As described above, in the conventional method, when configuring a semiconductor circuit that uses intermediate level signal pairs, it is not possible to configure the circuit freely, and it is difficult to configure a high-performance circuit. ? ! It required a complicated circuit.

The object of the present invention is to facilitate the connection of each circuit so that the original performance of each circuit can be fully exhibited.

[Means to solve the problem]

FIG. 1 shows a semiconductor circuit of the present invention. (a) shows a pair of input signals S at an intermediate level. 100 is an intermediate level shift circuit for downgrading the signal pair Ss and SN to a lower desired intermediate level, and (b) shows the input signal pair S at an intermediate level. This is an intermediate level shift circuit that shifts the signal pair SP, SF to a higher desired intermediate level.

In these figures, TN is an N-channel MO3) transistor, and T
, is a P-channel MOS transistor (1+2+・
... is a subscript that distinguishes each other), as shown in the figure, (a) is N
Channel MO3) transistor, (b) P channel M
O3) Consists of two transistors 21 connected in series, the gate of each transistor receives the input signal S, and the series connection point of each set becomes an output terminal.

In (a), the signal S is connected to the series connected circuits T1 and T. %TN3
The signal 100 is applied to the power supply side transistor TNl and the ground side transistor T)14 of TN4 and TN4, and the signal 100 is applied to the ground side transistor TN and the power supply side transistor TN3, that is, the power supply side and the ground side are reversed. (b) is similar, signal S
. 100 is a series connection circuit TPl and TP! l TF3 and TP4
For S, 100, add the power supply side and the ground side to the gate of each transistor with the power supply side and ground side reversed.

[Effect]

In this circuit, the input signal pair S. 100 is at an intermediate level with respect to the power supply vce as shown in FIG. 2, in FIG.
In the figure (g)), a signal pair SP, Sp with a higher potential than that is output. The degree of high/low is determined by the ratio of current driving capabilities of a pair of series-connected transistors.

The current drive capability is determined by the size of the transistor (gate length), and whether the transistor is on the power supply side or the ground side (gate-source voltage) in a series-connected circuit, so these factors determine the output signal pair relative to the input signal pair. The amount of level shift can be set to a desired value. However, since a) uses an N-channel transistor,
The output signal S8, 100, is lower than the dark voltage of the transistor than the input signal S, 100, and since a P-channel transistor is used in (1)), the output signal SP+Sr is equal to the input signal S. The voltage exceeds the dark voltage of the transistor by 100,
It cannot be more or less.

By using this circuit, input/output signal potentials can be optimized in a circuit that uses intermediate level signal pairs without changing the configuration of the input/output section of the circuit.

For example, the output signal level of circuits A and B is V l + V 2
, the optimal input signal level of the circuit C that receives these signals is ■, then by interposing the circuit shown in FIG.
, V2→■, and the circuit A-
There is no need to change the circuit configuration of the input/output section of C.

[Example] FIG. 3 shows an example of the present invention. Some memory chips have a plurality of cell arrays, and in this example, there are four. The readout output of each cell array is sense amplifier 11 to 1.
One of the readout outputs of these cell arrays is selected and input to the sense amplifier 16, and the outputs SF and SF of the amplifier are output outside the chip. Due to the above arrangement problem of the cell array, cell array 4 is close to the output end (sense amplifier 16), but cell arrays 1 to 3 are far from the output end, and signal attenuation may be a concern. In such cases, intermediate amplification is used. A sense amplifier 15 is used for intermediate amplification. Intermediate amplification may result in a significant level difference compared to one without intermediate amplification, and sense amplifiers have the characteristic that their output level changes depending on the input level.In such cases, the level shift circuit of the present invention is useful. It is valid. Transistors TS, and TS, TS, and T
S, , TS, TSi, TS7 and T S tr are level shift circuits, and input to the sense amplifier 16 at the same level, which is the optimum level for the sense amplifier. TT, and TT.

TT, and TT. is a transistor forming a selection gate, and D and E are selection signals.

Only one of the signals A-C becomes H, so that one output pair of the sense amplifiers 11-13 is selected and applied to the sense amplifier 15. Another signal.

One of E becomes H, which causes sense amplifier 1
One of the level-shifted output pairs of 4.15 SD and SD and SE and SE is selected and applied to the sense amplifier 16. Level shift circuit TS.

By adding ~TS, TS, ~TS, the level of the signal input to the sense amplifier 16 can be made the same, and the sense amplifier 16 can be set to the optimum circuit constant for that one input signal level. .

The level shift circuit shown in FIG. 1 can be used for purposes other than adjusting input signal levels. For example, in a transfer gate using an N-channel MOS transistor, it is preferable for the source-drain potential to be lower than the gate potential to avoid problems such as Vth drop, but for this purpose, the level shift circuit shown in FIG. It is effective to lower the signal potential.

FIG. 4 shows an example of the circuit of the sense amplifier shown in FIG.

As shown, this is a P-channel MO3) transistor T1
~T4 and N channel MOS transistors T, ~T,.

Consists of. T1 and T, ,T, and T4 constitute a current mirror, and T, and T&, T'r and T, are the input signal pair S
, and is a driver transistor that receives Si. Transistors T and Tl (1 expands the operating margin by preventing the potential of the virtual ground point (common source of T, T6゜T, and T) from changing too much even if the voltage changes.Output The signal pair So, S. is an enlarged version of the input signal pair Si+St, higher than its high potential side and lower than its low potential side.

FIG. 5 shows another embodiment of the present invention, in which transistors T s s + T N b + T P s are added to the circuit of FIG.
+ T p b is added, and this is inserted in series on the ground side in (a) and on the power supply side in (b). with this,(
In (a), the current driving ability of the transistor on the ground side is reduced, and in (b), the current driving ability of the transistor on the power supply side is reduced, and the amount of level shift becomes small.

These may be connected in parallel instead of in series.
This increases the current drive capability of the transistors on the ground and power supply sides, increasing the amount of level shift.

[Effects of the Invention] As explained above, in the present invention, the level of the intermediate level signal pair can be shifted up/down.
In semiconductor circuits that use intermediate-level signal pairs, connections between each circuit's personnel and output terminals can be easily made, and the optimal circuit configuration can be achieved without considering the personnel, output section, or output level of each circuit. This allows each circuit to fully demonstrate its original performance.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a semiconductor circuit of the present invention, FIG. 2 is a characteristic diagram for explaining operation, FIG. 3 is a circuit diagram showing an embodiment of the present invention, FIG. 4 is a circuit diagram of a sense amplifier, FIG. 5 is a circuit diagram showing another embodiment of the present invention. In the figure, TN is an N-channel MOS transistor, T is a P-channel MO3) transistor, S is an input signal pair,
3N, SN and SP, SP are output signal pairs. Applicant: Fujitsu Limited

Claims (1)

[Claims] 1. Two MOS transistors of the same conductivity type (T_N_1
and T_N_2,...) are connected in series,
Input signal pair (S, @S@
) is added to the gates of each transistor on the power supply side and the ground side of the two sets of series-connected circuits so that the power supply side and the ground side are reversed in one set and the other set, and these two sets are connected in series. A semiconductor circuit characterized in that each series connection point of the circuit serves as an output terminal of a level-shifted signal pair (S_N and @S@_N, . . . ).