KR940010839B1 - Data output buffer circuit - Google Patents

Abstract

The a data output buffer is charged at a high voltage, Vpp, after the gate voltage of NMOS pull-up transistor is pre-charged at a constant level. This circuit comprises of a reverse gate G2 which inputs the control signal, a transistor Q12 which operates dependently on the output signal of the reverse gate G2 in order to pre-charge the gate of pull-up transistor Q10, and a pull-up transistor which makes the output node a high signal, responding to the input of the pull-up signal PU.

Description

Data output buffer circuit

1 is a conventional data output buffer circuit diagram.

2 is a waveform diagram for explaining the operation of FIG.

3 is a data output buffer circuit diagram according to the present invention.

* Explanation of symbols for main parts of the drawings

Q1 to Q13: transistors G1 and G2: inverting gates

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data output buffer circuit, and more particularly, to precharge the gate terminal voltage of an NMOS pull-up transistor of a data output buffer to a constant level at ground potential, and then charge-up to a high voltage Vpp of Vcc or higher by a charge pump. The present invention relates to an output buffer circuit.

In general, in a dynamic random access memory (DRAM), a data output buffer circuit uses an NMOS transistor instead of a driver using a CMOS transistor to prevent latch-up at an input / output port when outputting data during a read cycle. Is configured as a pull-up and pull-down structure, and the data output buffer circuit of this structure is shown in FIG.

FIG. 1 is a conventional data output buffer circuit diagram. Referring to FIG. 2, a control signal as shown in FIG. 2 in a standby state is shown. Since is high, transistors Q4 and Q3 are on. Transistor Q2 is turned on while transistor Q1 is turned off so that the potential at node N1 is at Vpp. (The potential of the node N2 is the ground potential.) Therefore, the transistors Q5 and Q6 are turned off, the Q7 and Q8 are turned on, and the pull-up transistor Q10 is also turned off, so the output Dout becomes a standby state.

For example, when the sensed data in the sense amplifier (not shown) is "1" and the read time is the control signal. Transition from high to low state turns transistors Q4 and Q3 off while transistors Q9 and Q13 turn on to conduct transistor Q1. Therefore, node N1 becomes the ground potential and node N2 becomes the Vpp potential. In addition, transistors Q8 and Q7 are off and transistors Q5 and Q6 are on. Therefore, transistor Q10 is on, so the output Dout is Will print When the data sensed by the sense amplifier is "1", the control signal PD is low, so the pull-down transistor Q11 is turned off.

This prior art uses a pull-up NMOS transistor with a large driving current value to drive a Dout load, for example, 100PF, which charge-ups the gate potential of the pull-up NMOS transistor from ground potential to Vpp potential at one time. In this case, the loss charge generates the Vpp potential by the charge pump, which consumes a lot of power.

Accordingly, the present invention provides a data output buffer in which the gate potential of the pull-up NMOS transistor is first precharged from the ground potential to the (Vcc-VT) potential and then finally charged up to the Vpp potential to solve the above-mentioned disadvantage. The purpose is to provide a circuit.

The data output buffer circuit of the present invention is a control signal In the data output buffer circuit for bringing the gate terminal of the pull-up transistor Q10 into the Vpp potential and causing the output Dout to be high, the control signal. And a transistor Q12 connected between the inverted gate G2 for inverting the Vcc and the gate terminal of the pull-up transistor Q10 and operating in accordance with the output signal of the inverted gate G2 to precharge the gate terminal of the pull-up transistor Q10. It features.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

3 is a data output buffer circuit diagram according to the present invention, in the standby state, the same operation as the above-described first embodiment, but the control signal Transitioning from the high state to the low state causes the output of the inverting gate G2 to go high to turn on the transistor Q12. Therefore, the gate terminal potential of transistor Q10 is first precharged to Vcc-Vth (threshold voltage of transistor Q12), and secondly, transistors Q5 and Q6 are turned on so that the gate terminal potential of transistor Q10 is at Vcc-Vth level. The transistor Q10 is turned on by rising to the Vpp level. Therefore, the output Dout goes high.

As described above, the present invention has an excellent effect of reducing power consumption when raising the gate potential of the pull-up transistor stepwise to raise the pull-up transistor from the ground potential using the Vpp charge to the Vpp potential at a time.

Claims (1)

Control signal In the data output buffer circuit for setting the output Dout high with the gate terminal of the pull-up transistor Q10 at Vpp potential, the control signal A transistor Q12 connected between an inverting gate G2 for inputting a signal, a Vcc, and a gate terminal of the fly-up transistor Q10 and operating in accordance with an output signal of the inverting gate G2 to precharge the gate terminal of the pull-up transistor Q10; And a pull-up transistor Q10 that pulls up the output node to a high signal in response to an input of a signal PU.