KR930014592A - Data output buffer circuit - Google Patents

Data output buffer circuit Download PDF

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Publication number
KR930014592A
KR930014592A KR1019910022434A KR910022434A KR930014592A KR 930014592 A KR930014592 A KR 930014592A KR 1019910022434 A KR1019910022434 A KR 1019910022434A KR 910022434 A KR910022434 A KR 910022434A KR 930014592 A KR930014592 A KR 930014592A
Authority
KR
South Korea
Prior art keywords
buffer circuit
data output
output buffer
transistor
pull
Prior art date
Application number
KR1019910022434A
Other languages
Korean (ko)
Other versions
KR940010839B1 (en
Inventor
김영희
Original Assignee
정몽헌
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정몽헌, 현대전자산업 주식회사 filed Critical 정몽헌
Priority to KR1019910022434A priority Critical patent/KR940010839B1/en
Publication of KR930014592A publication Critical patent/KR930014592A/en
Application granted granted Critical
Publication of KR940010839B1 publication Critical patent/KR940010839B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type

Abstract

본 발명은 DRAM의 데이타 출력 버퍼회로에 관한 기술로, 데이타 출력버퍼 회로의 풀업트랜지스터 게이트 단자전위를 단계적으로 상승시킴으로서 소비전력이 감소되도록 한 기술이다.The present invention relates to a data output buffer circuit of a DRAM, in which power consumption is reduced by increasing the pull-up transistor gate terminal potential of the data output buffer circuit step by step.

Description

데이타 출력 버퍼회로Data output buffer circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 따른 데이타 출력 버퍼 회로도.3 is a data output buffer circuit diagram according to the present invention.

Claims (1)

제어신호에 따라 풀업트랜지스터 Q10의 게이트 단자를 VPP 전위로 하여 출력 Dout을 High 상태로 하기 위한 데이타 출력버퍼 회로에 있어서, 상기 제어신호을 반전시키는 반전게이트 G2와 VCC 및 상기 풀업트랜지스터 Q10의 게이트 단자간에 접속되되 상기 반전게이트 G2의 출력신호에 따라 ON동작하여 상기 풀업 트랜지스터 Q10의 게이트 단자를 프리차지하기 위한 트랜지스터 Q12를 포함하는 것을 특징으로 하는 데이타 출력버퍼회로.Control signal In the data output buffer circuit for setting the output Dout high with the gate terminal of the pull-up transistor Q10 at VPP potential, the control signal And a transistor Q12 connected between an inverting gate G2 and VCC for inverting the VCC and a gate terminal of the pull-up transistor Q10 and operating ON according to an output signal of the inverting gate G2 to precharge the gate terminal of the pull-up transistor Q10. Data output buffer circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910022434A 1991-12-09 1991-12-09 Data output buffer circuit KR940010839B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910022434A KR940010839B1 (en) 1991-12-09 1991-12-09 Data output buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910022434A KR940010839B1 (en) 1991-12-09 1991-12-09 Data output buffer circuit

Publications (2)

Publication Number Publication Date
KR930014592A true KR930014592A (en) 1993-07-23
KR940010839B1 KR940010839B1 (en) 1994-11-17

Family

ID=19324382

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910022434A KR940010839B1 (en) 1991-12-09 1991-12-09 Data output buffer circuit

Country Status (1)

Country Link
KR (1) KR940010839B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100406579B1 (en) * 2000-11-01 2003-11-21 주식회사 하이닉스반도체 Circuit of output driver in rambus dram

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100406579B1 (en) * 2000-11-01 2003-11-21 주식회사 하이닉스반도체 Circuit of output driver in rambus dram

Also Published As

Publication number Publication date
KR940010839B1 (en) 1994-11-17

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