KR100557591B1 - Data output buffer - Google Patents

Abstract

The present invention relates to a data output buffer, in particular connected to the output terminal in parallel with the first pull-up means to pull up the output terminal potential with an internal power supply voltage, but selectively pull-up with the first pull-up means. Second pull-up means for performing an operation; By further comprising a control means for comparing the internal power supply voltage and the output terminal potential and controlling whether the second pull-up means is activated according to the comparison value, the potential level of the high level output signal is set to the internal power supply voltage. The present invention relates to a data output buffer that not only increases the operation speed during data transition by limiting the level, but also suppresses the occurrence of noise at the ground end.

Description

Data output buffer

The present invention relates to a data output buffer, and more particularly, by limiting the potential level of a high level output signal to an internal voltage level, not only increases the operation speed at the time of data transition, but also suppresses the occurrence of noise at the ground end. It is about output buffer.

Generally, a data output buffer is a device that buffers data processed by a semiconductor integrated circuit so that the data has a voltage level sufficient to drive an external peripheral circuit.

Thus, a pull-up driver stage for amplifying the first logic of the data to have the power supply voltage Vcc and a pull-down for amplifying the second logic of the data to have the ground voltage Vss. A driver stage may be provided, and the pull-up driver stage may include NMOS and PMOS transistors, and the pull-down driver stage may comprise NMOS transistors.

However, since the NMOS type pull-up driver stage limits the voltage on the output line to be smaller than the voltage on the input line due to a threshold voltage loss, the first logic value of the data in the input line is limited to the power supply voltage Vcc. A separate circuit for boosting to a larger voltage is required, which not only lowers the operation speed of the data output buffer but also causes a problem of increasing current consumption in the standby mode.

On the other hand, since the PMOS type pull-up driver stage does not require a separate boost circuit, it is possible to prevent the operation speed of the data output buffer and the current consumption in the standby mode.

For this reason, it is common for the pull-up driver stage to use a PMOS transistor.

FIG. 1 is a block diagram showing a conventional data output buffer. The data signal (/ data: in the case of the same figure) is a data signal that is shifted according to an address change under the control of a clock signal c1 applied from the outside. Data register means (10) for selectively transmitting a complementary signal because the phase is opposite to that of the complementary signal; The 'high' and 'low' potentials are respectively received by receiving the data signal / data2 transferred through the data register means 10 and the clock signal c2 which enables the data output buffer during data read operation. Pull-up and pull-down control means (20, 30) for outputting pull-up and pull-down operation control signals (pu, pd) at the output stage to form a data output path having a level; A pull-up and pull-down means 40 for selectively turning on in accordance with the pull-up and pull-down operation control signals pu and pd to pull-up and pull-down the output terminal potential; 50).

The clock signal c1 is a signal generated by using a / cas (/ column address strobe) signal as a clock signal for passing the changed data when data changes due to an address change, and another clock signal c2. Is a signal to enable the data output buffer during read operation.The / ras (/ row address strobe) signal, / cas (/ column address strobe) signal, / we (/ write enable) signal, / oe (/ output Enable) is a clock signal generated by a combination of signals.

In addition, the pull-up means 40 includes a PMOS transistor MP1 having an output signal pu of the pull-up control means 20 applied to a gate terminal and a source terminal connected to an external power supply voltage Vext applied terminal. Is made of.

In addition, the pull-down means 50 has an output signal pd of the pull-down control means 30 applied to a gate terminal, and a source terminal thereof is connected to the drain terminal of the PMOS transistor MP1 and the drain terminal thereof. The grounded NMOS transistor MN1 is formed.

FIG. 4A illustrates an operation timing diagram of the data output buffer shown in FIG. 1, and FIG. 5A shows data when both clock signals c1 and c2 are enabled in the data output buffer shown in FIG. 1. The simulation result diagram is shown with varying.

However, as shown in FIG. 4A, when the input data signal data is high (when the / data signal is low), the pull-up and pull-down control means 20 and 30 shown in FIG. The output signals pu and pd of the Ns become 'logic low' to turn on the pull-up means 40 connected to the rear stage and turn off the pull-down means 50.

When the data signal data is low (when the / data signal is high), the reverse operation is performed.

By the above operation, the output terminal potential rises to the external power supply voltage Vext applied from the pull-up means 40 when the 'high' data is output. In the DRAM, the output speed of the 'high' data is usually increased. It is common to use a high external power supply voltage (Vext) to increase the voltage.

Thus, as shown in the simulation result diagram of FIG. 5A, a voltage higher than necessary is applied to the output terminal during data read operation (see (b) of FIG. 5A), which causes the data from logic high to logic low. The problem of longer transition times occurs.

In addition, as shown in (c) of FIG. 5A, a large amount of current flows through the ground terminal at once, resulting in a high noise generation rate.

Accordingly, an object of the present invention is to solve the above problems, and an object of the present invention is to limit the data output signal of a high level to an internal power supply voltage which is lower than a certain potential by an external power supply voltage, thereby speeding up the data transition speed and increasing the ground stage. It is to provide a data output buffer to remove the noise generated in the.

In order to achieve the above object, the data output buffer according to the present invention comprises: data register means for selectively transferring a data signal transitioned according to an address change;

First pull-up means for pulling up an output terminal potential to a first power supply voltage and pull-down means for pulling down the output terminal potential to a ground potential;

Respectively connected between the register means, the first pull-up means and the pull-down means to control the operation of the first pull-up and pull-down means in accordance with the data signal value transmitted through the raster means. First pull-up control means and pull-down control means for outputting a control signal, respectively;

A second pull-up connected to the output terminal in parallel with the first pull-up means to pull up the output terminal potential with a second power supply voltage, and selectively perform a pull-up operation with the first pull-up means; Means;

And second pull-up control means for comparing the second power supply voltage with the output terminal potential and controlling whether the second pull-up means is activated according to the comparison value.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram of a data output buffer according to the present invention. The data signal shifted according to an address change (in the case of the same figure, the complementary signal / data is used to indicate that the phase is opposite to the actual data signal). Data register means (10) for selectively transmitting; A first pull-up means 40 for pulling up the output terminal dout potential to an external power supply voltage Vext and a pull-down means 50 for pulling down the output terminal dout potential to the ground potential Vss; )and; Control signals pu and pd for controlling the operation of the first pull-up and pull-down means 40 and 50 according to the data signal value / data2 transmitted through the data raster means 10. First pull-up control means and pull-down control means 20 and 30 for outputting, respectively; It is connected to the output terminal (dout) in parallel with the first pull-up means 40 to pull-up the output terminal (dout) potential up to the internal power supply voltage (Vint) generated by the voltage drop. Second pull-up means (45) for selectively performing a pull-up operation with the first pull-up means (40); The second pull-up control means 25 compares the internal power supply voltage Vint with the output terminal potential and controls whether the second pull-up means 45 is activated according to the comparison value. It is composed.

3 is a detailed circuit diagram of FIG. 2, wherein the data register means 10 includes an inverter I1 for inverting a clock signal c1 generated by a cascade signal / cas; The clock signal c1 is applied to the gate terminal of the NMOS transistor unit, and the output potential of the inverter I1 is applied to the gate terminal of the PMOS transistor unit, thereby performing a complementary turn-on operation of the input data signal (/ data). A transfer transistor MT1 for transmitting () to node N1; Two inverters (I2, I3) connected in series to receive the potential of the node (N1) and delay them for a predetermined time; The output potential of the inverter I1 is applied to the gate terminal of the NMOS transistor portion, and the clock signal c1 is applied to the gate terminal of the PMOS transistor portion to selectively output the output signal of the inverter I3 by a turn-on operation. And a transfer transistor MT2 that feeds back to the node N1.

In addition, the first pull-up means 40 and the second pull-up means 45 are all composed of PMOS transistors MP1 and MP2, and the pull-down means 50 are connected to the NMOS transistor MN1. It is composed.

In addition, the first pull-up control means 20 includes an inverter I4 for inverting the potential of the node N1; NAND gate that receives and NAND-combines the clock signal c2 generated by combining / cas, / ras, / we, / oe signals and the output signal of the inverter I4 to enable the entire operation during the read operation ( NAND1); An inverter I5 connected to an output terminal of the NAND gate NAND1; NMOS transistors MN2 and MN3 having an output signal of the NAND gate NAND1 and an output signal of the inverter I5 applied to respective gate ends, and a source end of which is commonly connected to ground; NMOS transistors MN4 and MN5 connected to drain terminals of the NMOS transistors MN2 and MN3, respectively, the gate terminals of which are commonly connected to a power supply voltage Vcc applying terminal; It is connected between an external power supply voltage Vext applying terminal and drain terminals N3 and N2 of the NMOS transistors MN4 and MN5, and potentials of the nodes N2 and N3 are connected to each gate terminal in a cross-coupled structure. PMOS transistors MP3 and MP4; The output terminal transitions to logic high when the potential of the node N2 is input to one input terminal, and the output terminal dout becomes higher than the internal power voltage Vint generated by the voltage drop of the external power supply voltage Vext. A NOR gate NOR1 configured to NOR logically combine two signals (a potential signal of N2 and a det signal) by receiving the potential detection signal det through the other input terminal; An output signal of the NOR gate NOR1 is applied to each gate terminal, and is connected in series between an external power supply voltage Vext and a ground terminal Vss to generate a pull-up control signal pu as an output node. It consists of a PMOS transistor MP5 and an NMOS transistor MN6.

The pull-down control means (30) includes two inverters (I6, I7) connected in series for a simple delay of the clock signal (c2) input to the first pull-up control means (20); A NAND gate NAND2 for NAND logical combination of the inverter I7 output signal and the data signal / data2 transmitted via the data register means 10; An inverter I8 for inverting an output signal of the NAND gate NAND2; NMOS transistors MN7 and MN8 having an output signal of the NAND gate NAND2 and an output signal of the inverter I8 applied to respective gate terminals, and a source terminal of which is commonly connected to ground; NMOS transistors MN9 and MN10 which are connected to drain terminals of the NMOS transistors MN7 and MN8 and whose gate terminals are commonly connected to a power supply voltage Vcc applying terminal; It is connected between an external power supply voltage Vext applying terminal and drain terminals N5 and N4 of the NMOS transistors MN9 and MN10, and potentials of the nodes N4 and N5 are connected to each gate terminal in a cross-coupled structure. PMOS transistors MP6 and MP7; A potential of the node N4 is applied to each gate terminal, and a PMOS transistor connected in series between an external power supply voltage Vext and a ground terminal Vss to generate a pull-down control signal pd to an output node. And an NMOS transistor MN11.

Finally, the second pull-up control means 25 is enabled by the output signal det_en of the NOR gate NOR1 constituting the first pull-up control means 20, and the output stage ( a comparator (1) for applying a potential to the input signal on one side and the internal power supply potential (Vint) to the other input signal as a reference voltage to compare the two signals (dout, Vint); A pull-up control part 5 generating a signal pui for controlling only one of the first and second pull-up means 40, 45 to be activated according to the potential of the output terminal N6 of the comparator 10; It consists of.

The comparison unit 1 is made of a differential amplifier of a current mirror structure, and its detailed configuration will be omitted since it is well known.

The pull-up control unit 5 sets the signal pui_con of the node N3 in the first pull-up control unit 20 as one input signal, and the signal pui_con of the node N3 is set as one input signal. The signal transmitted through a simple delay consisting of a plurality of inverters and capacitors (in the figure, shown by I9 and I10 and C1 and C2) is a two-input signal, and an output terminal N6 signal of the comparator 1 A NAND gate (NAND3) for receiving the input as three input signals and NAND combining them; An inverter I11 for inverting an output signal of the NAND gate NAND3; Inverter I12 which inverts the output signal det of the inverter I11 and applies the output signal pui to the gate terminal of the PMOS transistor MP2 constituting the second pull-up means 45. It is composed.

As described above, the inverter I11 output signal det of the pull-up control unit 5 is applied as an input signal of one side of the NOR gate NOR1 constituting the first pull-up control unit 20.

Hereinafter, the operation of the present invention having the above configuration will be described with reference to the following drawings.

FIG. 4B illustrates an operation timing diagram of the data output buffer shown in FIG. 3. FIG. 5B shows data when both clock signals c1 and c2 are enabled in the data output buffer shown in FIG. 3. The simulation result diagram is shown with varying.

As shown in FIG. 4B, once the data signal data transitions from low to high (that is, the complementary data signal / data transitions from high to low), the first pull-up control means 20 In the initial state, the pui_con signal of the node N3 becomes high. Since the det signal is low and the pui signal is high in the initial state, the det_en signal goes high and the pu signal goes low.

However, since the det_en signal becomes an enable signal of the comparator 1 constituting the second pull-up control means 25, the comparator 1 operates by the det_en signal transitioned to high. To start. The det_en signal having the high potential level turns on the next NMOS transistor MN6 to generate a pull-up control signal pu as a low-level signal, and accordingly the first pull-up means 40. Turn on the PMOS transistor MP1. Thereafter, the output dout potential starts to rise high.

At this time, the NAND gate NAND3 constituting the pull-up control unit 5 has a high level pui_con signal, so that the two input signals are high, so that the NAND gate NAND3 is at the potential level of the output terminal N6 of the comparison unit 1. The output signal is determined accordingly, which is low when the potential of the output terminal N6 of the comparator 1 is high, and high when the potential of the output terminal N6 is low.

Here, since the comparator 1 in the second pull-up control means 25 is made of a differential amplifier with a current-mirror structure, its operation characteristics are as follows. That is, when the final output terminal (dout) potential as one input signal is lower than the internal power supply voltage (Vint) which becomes the other reference comparison potential, a low signal is output to the output N6, and the final output terminal (dout) potential Transitions the output signal from low to high when the power supply voltage becomes higher than the internal power supply voltage Vint. Thereafter, the output signal det of the inverter I11 in the pull-up control section 5 transitions to high as shown in FIG. 4B, which outputs a low as a pui signal via the rear inverter I12. do.

The second pull-up means 45 is enabled by the low level pui signal applied to supply the internal power supply voltage Vint to its output terminal dout.

At the same time, the det signal transitioned to the high level is input to one input terminal of the NOA gate NOR1 constituting the first pull-up control means 20, and outputs a low signal as its output signal. The rear PMOS transistor MP5 is turned on and the NMOS transistor MN6 is turned off to output high as a pull-up control signal pu.

The high level pull-up control signal pu disables the first pull-up means 40, and at the same time, the high level det signal causes the subsequent det_en signal to transition to the low level.

In addition, since the operation of the comparator 1 in the second pull-up control means 25 whose operation is controlled according to the det_en signal is disabled, the potential of the output dout potential and the internal power supply voltage Vint. The current consumption after the comparison can be prevented.

After that, when the data transitions to the low level again, the pui_con signal outputted through the node N3 in the first pull-up control means 20 transitions to low, and receives and outputs this signal pui_con. The det signal and pui signal of the second pull-up control means 25 are reset.

By the operation as described above, the present invention outputs high-level data, and primarily the internal power supply voltage Vint and the output terminal potential dout generated by the external power supply voltage Vext dropping inside the device. After comparison, the operation of the first pull-up means 40 which applies an external power supply voltage Vext to the output terminal and performs a pull-up operation when the output dout potential becomes equal to or greater than the internal power supply voltage Vint. At the same time, the internal power supply voltage Vint is applied to the output terminal to operate the second pull-up means 45 which performs the pull-up operation, thereby limiting the potential level of the data output to the high level. .

As can be seen from the comparison of the simulation results shown in FIGS. 5A and 5B, the output value of the high level data outputs a lower value of about 2.9V in FIG. 5B compared to about 3.6V of FIG. 5A, and each signal waveform The ground terminal potential shown at the lower end of FIG. 5B also shows a lower potential and outputs a uniform value.

As described above, according to the data output buffer according to the present invention, by limiting the output potential of high-level data to the internal power supply voltage, a very excellent effect of speeding up the transition speed when data transitions from a high level to a low level is obtained. have.

In addition, it is possible to limit the flow of a large amount of current at the same time to the ground terminal, it is possible to reduce the noise generation rate, thereby improving the yield has a very excellent effect.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the scope of the claims You will have to look.

1 is a block diagram showing a conventional data output buffer

2 is a block diagram of a data output buffer according to the present invention.

3 is a detailed circuit diagram of FIG.

4 is an operation timing comparison diagram of the data output buffer shown in FIGS. 1 and 2.

5 is a comparison of simulation results of the data output buffer shown in FIGS. 1 and 2.

<Explanation of symbols for main parts of drawing>

10: data register means 20, 25: pull-up control means

30: pull-down control means 40, 45: pull-up means

50: pull-down means

Claims (5)

Data register means (10) for selectively transferring a data signal transitioned according to an address change; First pull-up means (40) for pulling up an output terminal potential to a first power supply voltage and pull-down means (50) for pulling down the output terminal potential to a ground potential; Connected between the register means, the first pull-up means and the pull-down means, respectively, the operation of the first pull-up means and the pull-down means in accordance with a data signal value transmitted through the data register means; A first pull-up control means 20 and a pull-down control means 30 respectively outputting control signals for controlling the control means; A second pull connected to the output terminal in parallel with the first pull-up means to pull up the output terminal potential with a second power supply voltage, and selectively perform a pull-up operation with the first pull-up means; Up-up means 45; And a second pull-up control means 25 for comparing the second power supply voltage with the output terminal potential and controlling whether the second pull-up means is activated according to the comparison value. buffer. The method of claim 1, The first power supply voltage is an external power supply voltage Vext. And the second power supply voltage is an internal power supply voltage (Vint) in which the first power supply voltage drops to a constant potential level. The method of claim 1, The first and second pull-up means, Data output buffer, characterized in that each consisting of a PMOS transistor (MP1, MP2). The method of claim 1, The second pull-up control means, Enable is determined by an operation control signal of the first pull-up means, an output potential is applied as one input signal, and the second power potential is applied as the other input signal as a reference comparison potential to compare the two signals. A comparator 1 to make; And a pull-up control section (5) for controlling only one of the first and second pull-up means to be activated according to the output signal of the comparing section. The method of claim 4, wherein The comparing unit (1) is a data output buffer, characterized in that consisting of a differential amplifier of the current-mirror structure.