KR20000038822A - 박막트랜지스터 및 그 제조방법 - Google Patents
박막트랜지스터 및 그 제조방법 Download PDFInfo
- Publication number
- KR20000038822A KR20000038822A KR1019980053948A KR19980053948A KR20000038822A KR 20000038822 A KR20000038822 A KR 20000038822A KR 1019980053948 A KR1019980053948 A KR 1019980053948A KR 19980053948 A KR19980053948 A KR 19980053948A KR 20000038822 A KR20000038822 A KR 20000038822A
- Authority
- KR
- South Korea
- Prior art keywords
- gate insulating
- forming
- active layer
- thin film
- insulating film
- Prior art date
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 75
- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 239000010408 film Substances 0.000 claims abstract description 70
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000009413 insulation Methods 0.000 claims abstract 8
- 239000000463 material Substances 0.000 claims description 31
- 238000005530 etching Methods 0.000 claims description 20
- 239000012535 impurity Substances 0.000 claims description 18
- 238000002161 passivation Methods 0.000 claims description 5
- 230000001681 protective effect Effects 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims 2
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 80
- 229910021417 amorphous silicon Inorganic materials 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 238000000151 deposition Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000011856 silicon-based particle Substances 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
Claims (18)
- 절연기판과,상기 절연기판 상에 소오스영역, 드레인영역 및 채널영역을 구비하여 형성된 활성층과,상기 채널영역 상에 내부공간이 위치하도록 형성된 게이트절연막과,상기 채널영역 상부의 상기 게이트절연막 상에 형성된 게이트전극을 포함하는 박막트랜지스터.
- 청구항 1에 있어서,상기 내부공간의 측면은 경사지게 형성된 박막트랜지스터.
- 청구항 1에 있어서,상기 게이트절연막이 상기 활성층 전면을 덮도록 형성된 박막트랜지스터.
- 청구항 1에 있어서,상기 게이트절연막이 상기 공간부만을 덮도록 형성된 박막트랜지스터.
- 청구항 3 또는, 청구항 4에 있어서,상기 게이트전극은 상기 공간부에 중첩되도록 형성된 박막트랜지스터.
- 청구항 3에 있어서,상기 게이트전극 및 상기 게이트절연막을 덮는 보호막과,상기 보호막과 상기 게이트절연막에 상기 소오스영역과 드레인영역을 노출시키도록 형성된 콘택홀과,상기 노출된 소오스영역에 연결된 소오스전극과 상기 노출된 드레인영역에 연결된 드레인전극을 더 포함하는 박막트랜지스터.상기 게이트절연막이 상기 활성층 전면을 덮도록 형성된 박막트랜지스터.
- 청구항 4에 있어서,상기 게이트절연막 하단에 접촉하는 상기 활성층 부분은 상기 소오스영역 및 드레인영역보다 고저항을 가지는 고저항영역이 형성된 박막트랜지스터.
- 청구항 7에 있어서,상기 고저항영역은 오프셋영역인 박막트랜지스터.
- 청구항 7에 있어서,상기 고저항영역은 엘디디영역인 박막트랜지스터.
- 청구항 8에 있어서,상기 게이트전극, 상기 게이트절연막 및 상기 활성층을 덮는 보호막과,상기 보호막에 상기 소오스영역과 드레인영역을 노출시키도록 형성된 콘택홀과,상기 노출된 소오스영역에 연결된 소오스전극과 상기 노출된 드레인영역에 연결된 드레인전극을 더 포함하는 박막트랜지스터.
- 절연기판 상에 활성층을 형성하는 단계와,상기 활성층 상에 내부공간이 위치하는 게이트절연막 및 상기 게이트절연막 상에 위치하는 게이트전극을 형성하는 단계와,상기 활성층을 포함하는 기판의 노출된 전면에 불순물 도핑공정을 진행하여 상기 활성층에 소오스영역과 드레인영역을 형성하는 단계를 포함하는 박막트랜지스터 제조방법.
- 청구항 11에 있어서,상기 내부공간은 측면을 경사지게 형성하는 박막트랜지스터 제조방법.
- 청구항 11에 있어서,상기 내부공간, 게이트절연막 및 게이트전극을 형성하는 방법은,상기 활성층 상에 공간 형성용 물질층을 형성하는 단계와,상기 공간 형성용 물질층을 포함하는 기판의 노출된 전면을 덮는 게이트절연막을 형성하는 단계와,상기 게이트절연막에 상기 공간 형성용 물질층의 일부를 노출시키는 에칭홀을 형성하는 단계와,상기 에칭홀에 의하여 노출된 상기 공간 형성용 물질층을 에천트를 사용하여 제거하여 상기 활성층 상에 상기 게이트절연막으로 둘러싸는 내부공간을 형성하는 단계와,상기 게이트절연막 상에 게이트전극을 형성하는 단계를 포함하는 박막트랜지스터 제조방법.
- 청구항 13에 있어서,상기 게이트절연막이 상기 내부공간을 둘러싸는 부분만 남도록 상기 게이트절연막을 사진식각하는 단계를 더 포함하는 박막트랜지스터 제조방법.
- 청구항 14에 있어서,상기 불순물 도핑공정시, 불순물 주입에너지를 조절하여 상기 남겨진 게이트절연막 하단의 활성층 부분에 상기 소오스영역 및 드레인영역보다 고저항을 가지는 고저항영역을 함께 형성하는 박막트랜지스터 제조방법.
- 청구항 13에 있어서,상기 에칭홀을 형성하는 공정시, 상기 활성층의 소오스영역과 드레인영역이 될부분을 노출시키는 콘택홀을 함께 형성하는 박막트랜지스터 제조방법.
- 청구항 11에 있어서,상기 내부공간, 게이트절연막 및 게이트전극을 형성하는 방법은,상기 활성층 상에 공간 형성용 물질층을 형성하는 단계와,상기 공간 형성용 물질층을 포함하는 기판의 노출된 전면을 덮는 게이트절연막을 형성하는 단계와,상기 게이트절연막을 상기 공간 형성용 물질층을 덮는 부분만이 남겨지되, 상기 공간 형성용 물질층의 일부를 노출시키는 에칭홀이 형성되도록 선택적으로 식각하는 단계와,상기 에칭홀에 의하여 노출된 상기 공간 형성용 물질층을 에천트를 사용하여 제거하여 상기 활성층 상에 상기 게이트절연막으로 둘러싸는 내부공간을 형성하는 단계와,상기 게이트절연막 상에 게이트전극을 형성하는 단계를 포함하는 박막트랜지스터 제조방법.
- 청구항 17에 있어서,상기 불순물 도핑공정시, 불순물 주입에너지를 조절하여 상기 남겨진 게이트절연막 하단의 활성층 부분에 상기 소오스영역 및 드레인영역보다 고저항을 가지는 고저항영역을 함께 형성하는 박막트랜지스터 제조방법.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019980053948A KR100282233B1 (ko) | 1998-12-09 | 1998-12-09 | 박막트랜지스터 및 그 제조방법 |
US09/457,389 US6188108B1 (en) | 1998-12-09 | 1999-12-09 | Thin film transistor and a fabricating method thereof |
US09/604,393 US6316294B1 (en) | 1998-12-09 | 2000-06-27 | Thin film transistor and a fabricating method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019980053948A KR100282233B1 (ko) | 1998-12-09 | 1998-12-09 | 박막트랜지스터 및 그 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20000038822A true KR20000038822A (ko) | 2000-07-05 |
KR100282233B1 KR100282233B1 (ko) | 2001-02-15 |
Family
ID=19562036
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019980053948A KR100282233B1 (ko) | 1998-12-09 | 1998-12-09 | 박막트랜지스터 및 그 제조방법 |
Country Status (2)
Country | Link |
---|---|
US (2) | US6188108B1 (ko) |
KR (1) | KR100282233B1 (ko) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3538084B2 (ja) * | 1999-09-17 | 2004-06-14 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
KR100778835B1 (ko) * | 2000-12-28 | 2007-11-22 | 엘지.필립스 엘시디 주식회사 | 액정표시장치의 제조방법 |
KR100776505B1 (ko) * | 2000-12-30 | 2007-11-16 | 엘지.필립스 엘시디 주식회사 | 액정표시장치의 화소전극 제조 방법 |
TW502453B (en) * | 2001-09-06 | 2002-09-11 | Winbond Electronics Corp | MOSFET and the manufacturing method thereof |
JP4649896B2 (ja) * | 2004-07-09 | 2011-03-16 | 日本電気株式会社 | 半導体装置及びその製造方法、並びにこの半導体装置を備えた表示装置 |
CN101354507B (zh) * | 2007-07-26 | 2010-10-06 | 北京京东方光电科技有限公司 | 薄膜晶体管液晶显示器阵列基板结构及其制造方法 |
KR101860859B1 (ko) | 2011-06-13 | 2018-05-25 | 삼성디스플레이 주식회사 | 박막트랜지스터의 제조 방법, 상기 방법에 의해 제조된 박막트랜지스터, 유기발광표시장치의 제조방법, 및 상기 방법에 의해 제조된 유기발광표시장치 |
CN110571226B (zh) | 2019-09-05 | 2021-03-16 | 深圳市华星光电半导体显示技术有限公司 | 一种显示面板及其制备方法 |
CN110600517B (zh) | 2019-09-16 | 2021-06-01 | 深圳市华星光电半导体显示技术有限公司 | 一种显示面板及其制备方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02109341A (ja) * | 1988-10-19 | 1990-04-23 | Fuji Xerox Co Ltd | 薄膜トランジスタの製造方法 |
JP3548237B2 (ja) * | 1994-08-29 | 2004-07-28 | シャープ株式会社 | 薄膜トランジスタ |
EP0844670B1 (en) * | 1996-06-06 | 2004-01-02 | Seiko Epson Corporation | Method for manufacturing thin film transistor, liquid crystal display and electronic device both produced by the method |
US6075257A (en) * | 1996-12-23 | 2000-06-13 | Samsung Electronics Co., Ltd. | Thin film transistor substrate for a liquid crystal display having a silicide prevention insulating layer in the electrode structure |
-
1998
- 1998-12-09 KR KR1019980053948A patent/KR100282233B1/ko not_active IP Right Cessation
-
1999
- 1999-12-09 US US09/457,389 patent/US6188108B1/en not_active Expired - Lifetime
-
2000
- 2000-06-27 US US09/604,393 patent/US6316294B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US6188108B1 (en) | 2001-02-13 |
US6316294B1 (en) | 2001-11-13 |
KR100282233B1 (ko) | 2001-02-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5569935A (en) | Semiconductor device and process for fabricating the same | |
US6627487B2 (en) | Semiconductor device and manufacturing method thereof | |
JP3713232B2 (ja) | 結晶質シリコン活性層を含む薄膜トランジスタの製造方法 | |
KR100402522B1 (ko) | 반도체장치 제작방법 | |
TWI322446B (en) | Mask for polycrystallization and method of manufacturing thin film transistor using polycrystallization mask | |
US7309625B2 (en) | Method for fabricating metal oxide semiconductor with lightly doped drain | |
US6861300B2 (en) | Fabricating method of polysilicon thin film transistor having a space and a plurality of channels | |
KR100282233B1 (ko) | 박막트랜지스터 및 그 제조방법 | |
US6562667B1 (en) | TFT for LCD device and fabrication method thereof | |
US20050130357A1 (en) | Method for manufacturing a thin film transistor using poly silicon | |
US7026201B2 (en) | Method for forming polycrystalline silicon thin film transistor | |
US20050037550A1 (en) | Thin film transistor using polysilicon and a method for manufacturing the same | |
KR20000074451A (ko) | 박막 트랜지스터와 액정표시장치 및 그 제조방법 | |
KR100452444B1 (ko) | 다결정 실리콘 박막트랜지스터 제조방법 | |
JP2000068515A (ja) | 薄膜半導体装置の製造方法 | |
JP2000077353A (ja) | 半導体装置の作製方法 | |
KR100751315B1 (ko) | 박막 트랜지스터, 박막 트랜지스터 제조 방법 및 이를구비한 평판 디스플레이 소자 | |
KR100397876B1 (ko) | 박막트랜지스터와 그 제조방법 | |
KR100615202B1 (ko) | 박막 트랜지스터, 박막 트랜지스터를 제조하는 방법 및이를 구비한 평판 디스플레이 소자 | |
JPH0831765A (ja) | 薄膜トランジスタの製造方法 | |
JPH09237898A (ja) | 多結晶半導体tft、その製造方法、及びtft基板 | |
JP2000068525A (ja) | 半導体装置およびアクティブマトリクス型表示装置 | |
KR20040012207A (ko) | 박막 트랜지스터 제조 방법 | |
JP2002093709A (ja) | 薄膜トランジスタ及びその作製方法 | |
JP2003059942A (ja) | 薄膜トランジスタの製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
N231 | Notification of change of applicant | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20120928 Year of fee payment: 13 |
|
FPAY | Annual fee payment |
Payment date: 20130930 Year of fee payment: 14 |
|
FPAY | Annual fee payment |
Payment date: 20141021 Year of fee payment: 15 |
|
FPAY | Annual fee payment |
Payment date: 20151028 Year of fee payment: 16 |
|
FPAY | Annual fee payment |
Payment date: 20161012 Year of fee payment: 17 |
|
FPAY | Annual fee payment |
Payment date: 20171016 Year of fee payment: 18 |
|
FPAY | Annual fee payment |
Payment date: 20181015 Year of fee payment: 19 |
|
EXPY | Expiration of term |