KR20000030963A - Fabrication method of mml semiconductor device - Google Patents
Fabrication method of mml semiconductor device Download PDFInfo
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- KR20000030963A KR20000030963A KR1019980044651A KR19980044651A KR20000030963A KR 20000030963 A KR20000030963 A KR 20000030963A KR 1019980044651 A KR1019980044651 A KR 1019980044651A KR 19980044651 A KR19980044651 A KR 19980044651A KR 20000030963 A KR20000030963 A KR 20000030963A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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Abstract
Description
본 발명은 MML반도체소자에 관한 것으로서, 특히, 로직영역의 트랜지스터를 개방시켜 실리사이드층을 형성한 후 디램영역 및 로직영역에 형성된 제1콘택홀을 이용하여 하부금속배선을 형성하고, 다시 인터폴리산화막을 적층하여 디램영역 및 로직영역에 제2콘택홀을 형성하여 그 내부에 상부금속배선을 적층하므로 로직영역의 실리사이드층의 손상을 방지하고 콘택홀을 다수에 걸쳐 형성하므로 금속배선의 형성을 용이하도록 하는 MML반도체소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MML semiconductor device, and more particularly, to form a silicide layer by opening a transistor in a logic region, and then forming a lower metal wiring by using a first contact hole formed in a DRAM region and a logic region, and again, an interpoly oxide layer. To form a second contact hole in the DRAM area and the logic area to stack the upper metal wiring therein, thereby preventing damage to the silicide layer of the logic area and forming a plurality of contact holes to facilitate the formation of the metal wire. It relates to a MML semiconductor device manufacturing method.
일반적으로, 메모리(Memory)와 로직(Logic)이 단일칩에 형성되는 복합반도체(MML: Merged Memory Logic)가 최근에 들어 많은 관심을 보이면서 점차적으로 많이 사용하는 추세에 있으며, 이 MML반도체장치는 로직과 메모리를 한 칩에서 단일한 공정으로 제조하는 것이 가능하므로 특별한 설계의 변경 없이도 기존 칩들에 비하여 고속으로 동작하고, 저전력으로 사용하는 것이 가능한 장점을 지닌다.In general, a mixed semiconductor (MML: Merged Memory Logic), in which memory and logic are formed on a single chip, has been increasingly used in recent years, and this MML semiconductor device has been increasingly used. Since it is possible to manufacture a single process in one chip and memory, it has the advantage that it can operate at a higher speed and use at lower power than existing chips without any special design change.
그 반면에, 메모리제품의 제조공정과 로직제품의 제조공정이 한 칩에서 동시에 제조되므로 단위칩의 크기가 커지며, 이에 따라 제조공정을 진행하기에 많은 어려움을 요하는 단점도 지니고 있을 뿐만 아니라 메모리에서의 트랜지스터는 높은 전류 구동력을 요하는 것보다 오히려 누설전류를 방지하는 것에 비중을 두고 있으나 로직제품은 높은 전류구동능력을 요구하는 등 양자의 특성을 모두 갖추어서 한칩으로 제조하여야 한다.On the other hand, since the manufacturing process of the memory product and the manufacturing process of the logic product are manufactured at the same time at the same time, the size of the unit chip is increased, and thus, not only has a disadvantage that requires a lot of difficulty to proceed with the manufacturing process, Transistors have more emphasis on preventing leakage current than requiring high current driving force, but logic products must be manufactured on one chip with both characteristics such as high current driving capability.
이와 같이, 종래에는 반도체기판에서 메모리영역과 로직영역에 필드산화막과 트랜지스터의 게이트전극을 동시에 형성하여 게이트전극의 측면부분에 스페이서막을 적층하고, 다시 활성영역에 이온을 주입하여 소오스/드레인을 형성한 후 그 공정 후에 메모리영역의 필드산화막 상에 커패시터(Capacitor)를 800℃에 이르는 고온 공정으로 형성하였으며, 연속하여 로직영역의 트랜지스터와 메모리영역의 트랜지스터 및 커패시터 상에 산화막으로 된 절연층 및 금속배선층을 다층으로 적층하여 이후 공정을 진행하게 된다.As described above, in the semiconductor substrate, a field oxide film and a gate electrode of a transistor are simultaneously formed in a memory region and a logic region, a spacer film is stacked on a side portion of the gate electrode, and ions are implanted into an active region to form a source / drain. After the process, a capacitor was formed on the field oxide film of the memory region by a high temperature process of 800 ° C., and the insulating layer and the metal wiring layer of the oxide film were formed on the transistor of the logic region and the transistor and capacitor of the memory region. Lamination is carried out in a multilayer process.
그런데, 상기한 바와 같이, 메모리영역의 트랜지스터는 누설전류방지에 비중을 두는 반면에 로직영역의 트랜지스터의 경우에는 높은 전류구동능력을 가지는 것에 비중을 두게 되는 것으로서, 종래에는 로직영역 및 메모리영역의 트랜지스터를 모두 형성한 후에 메모리영역에서 고온(800℃정도)의 커패시터를 제조하는 공정을 진행하므로 로직영역에서 이미 제조된 트랜지스터에, 특히, 트랜지스터의 소오스/드레인영역 및 활성영역에 형성되는 실리사이드층에 중대한 영향을 가하여 로직영역의 트랜지스터의 전류구동능력을 저하시켜 소자의 성능저하시키는 문제점을 지니고 있었다.By the way, as described above, the transistors in the memory region place emphasis on the prevention of leakage current, while the transistors in the logic region place emphasis on having a high current driving capability. After the formation of all, the process of manufacturing a high temperature capacitor (about 800 ℃) in the memory region is performed, which is important for transistors already manufactured in the logic region, particularly for silicide layers formed in the source / drain and active regions of the transistor. In this case, the current driving ability of the transistor in the logic region is lowered, thereby degrading the performance of the device.
또한, 메모리역할을 하는 디램(DRAM)영역은 트랜지스터와 커패시터가 형성되어지고, 로직(Logic)영역은 트랜지스터만이 형성되므로 양자를 한 칩에 형성하여 절연막을 적층하게 되면 전적으로 높이가 높아질 뿐만 아니라 디램영역의 커패시터 높이로 인하여 그 후에 진행되는 콘택을 형성하는 공정이 2㎛정도의 High Aspect Ratio로 인하여 상당한 Deep Contact이 형성되어지므로 정확한 콘택을 형성하지 못하는 문제점을 지니고 있었다.In addition, since a transistor and a capacitor are formed in a DRAM region, which serves as a memory, and only a transistor is formed in a logic region, only a transistor is formed on a chip to stack an insulating layer, thereby increasing the height entirely. Due to the capacitor height in the region, the subsequent process of forming a contact has a problem in that it cannot form an accurate contact because a considerable deep contact is formed due to a high aspect ratio of about 2 μm.
본 발명의 목적은 로직영역의 트랜지스터를 개방시켜 실리사이드층을 형성한 후 디램영역 및 로직영역에 형성된 제1콘택홀을 이용하여 하부금속배선을 형성하고, 다시 인터폴리산화막을 적층하여 디램영역 및 로직영역에 제2콘택홀을 형성하여 그 내부에 상부금속배선을 적층하므로 로직영역의 실리사이드층의 손상을 방지하고 콘택홀을 다수에 걸쳐 형성하므로 금속배선의 형성을 용이하도록 하는 것이 목적이다.An object of the present invention is to form a silicide layer by opening a transistor in a logic region, and then to form a lower metal wiring by using a first contact hole formed in a DRAM region and a logic region, and again to deposit an interpoly oxide layer to form a DRAM region and a logic. Since the second contact hole is formed in the region and the upper metal wiring is stacked therein, it is an object to prevent damage of the silicide layer of the logic region and to facilitate the formation of the metal wiring since the contact hole is formed over a plurality of regions.
도 1 내지 도 14는 본 발명의 일실시예에 따른 MML반도체소자 제조방법을 순차적으로 보인 도면이다.1 to 14 are views sequentially showing a method for manufacturing an MML semiconductor device according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10 : 반도체기판 15 : 필드산화막10: semiconductor substrate 15: field oxide film
20 : 디램게이트전극 25 : 로직게이트전극20: DRAM gate electrode 25: logic gate electrode
30 : 커패시터 35 : 절연막30 capacitor 35 insulation film
40 : 실리사이드층 45 : 제1인터폴리산화막40: silicide layer 45: first interpoly oxide film
48 : 로직영역만을 덮는 감광막48: photosensitive film covering only logic region
50 : 제1감광막 55 : 제1콘택부위50: first photosensitive film 55: first contact portion
60 : 하부금속배선층 65 : 제2감광막60: lower metal wiring layer 65: second photosensitive film
70 : 하부금속배선 75 : 제2인터폴리산화막70: lower metal wiring 75: second interpoly oxide film
80 : 제3감광막 85 : 제2콘택부위80: third photosensitive film 85: second contact portion
90 : 상부금속배선층 95 : 제4감광막90: upper metal wiring layer 95: fourth photosensitive film
100 : 상부금속배선100: upper metal wiring
이러한 목적은 디램영역에 디램게이트전극 및 커패시터를 형성하고, 로직영역에는 로직게이트전극을 형성한 후에 전 영역에 절연막을 적층한 단계와; 상기 절연막중에서 로직영역의 부분을 제거하여 로직게이트전극을 개방시킨 후에 소오스/드레인영역에 실리사이드층을 형성하는 단계와; 상기 디램영역 및 로직영역의 전면에 일정 두께로 제1인터폴리산화막을 적층하는 단계와; 상기 단계 후에 로직영역의 제1인터폴리산화막의 상부면에 감광막을 적층하고 디램영역의 제1인터폴리산화막을 식각하여 로직영역의 제1인터폴리산화막의 높이와 같도록 형성하는 단계와; 상기 제1인터폴리산화막 상에 디램영역 및 로직영역으로 제1콘택부위를 갖는 제1감광막을 적층한 후에 식각으로 디램게이트전극 및 로직게이트전극의 실리사이드층으로 개방되는 제1콘택홀을 형성하는 단계와; 상기 제1콘택홀에 하부금속층을 적층한 후 제2감광막으로 식각을 하여 하부금속배선을 형성하는 단계와; 상기 결과물의 전 영역에 제2인터폴리산화막을 적층한 후 그 위에 디램영역과 로직영역의 하부금속배선의 위치에 제2콘택부위를 갖는 제3감광막을 적층하는 단계와; 상기 제2콘택부위를 통하여 하부의 제2인터폴리산화막을 식각하여 제2콘택홀을 형성하는 단계와; 상기 디램콘택홀 및 제2로직콘택홀을 통하여 상부금속배선층을 적층한 후 식각으로 상기 하부금속배선에 연결되는 상부금속배선을 형성하는 단계로 이루어진 것을 특징으로 하는 MML반도체소자 제조방법을 제공함으로써 달성된다.The purpose of the present invention is to form a DRAM gate electrode and a capacitor in the DRAM region, and a logic gate electrode in the logic region, and then, depositing an insulating film over the entire region; Removing a portion of the logic region from the insulating film to open the logic gate electrode, and then forming a silicide layer in the source / drain region; Stacking a first interpoly oxide film on the entire surface of the DRAM region and the logic region with a predetermined thickness; After the step of laminating a photoresist film on the upper surface of the first interpoly oxide film of the logic region and etching the first interpoly oxide film of the DRAM region to form the same height as the first interpoly oxide film of the logic region; Stacking a first photoresist film having a first contact portion as a DRAM region and a logic region on the first interpoly oxide layer, and forming a first contact hole that is opened to the silicide layer of the DRAM gate electrode and the logic gate electrode by etching; Wow; Stacking a lower metal layer on the first contact hole and etching the second photoresist to form a lower metal wiring; Stacking a second interpoly oxide film over the entire region of the resultant, and then laminating a third photoresist film having a second contact portion at a position of a DRAM region and a lower metal wiring of the logic region thereon; Etching a lower second interpoly oxide layer through the second contact portion to form a second contact hole; It is achieved by providing an MML semiconductor device manufacturing method comprising the step of forming an upper metal wiring layer connected to the lower metal wiring by etching after laminating an upper metal wiring layer through the DRAM contact hole and the second logic contact hole. do.
그리고, 상기 절연막을 식각하여 로직게이트전극을 노출하기 위하여 건식식각을 이용하도록 하고, 상기 로직게이트전극에 형성되는 실리사이드층은 Ti(티타늄)혹은 Co(코발트)중에 어느 하나를 선택하여 사용하도록 하며, 상기 제2인터폴리산화막은 증착된 후에 상부면을 화학기계적연마법(CMP; Chemical Mechanical Polishing)으로 평탄화시키며, 상기 감광막을 제1인터폴리산화막 상에 적층하여 디램영역의 단차를 줄여 로직영역의 단차와 동일하게 형성하기 위하여 습식식각(Wet Etch) 혹은 건식식각(Dry Etch)을 이용하도록 하는 MML반도체소자 제조방법을 제공함으로써 달성된다.In addition, dry etching is used to expose the logic gate electrode by etching the insulating layer, and the silicide layer formed on the logic gate electrode is selected from Ti (titanium) or Co (cobalt). After the second interpoly oxide film is deposited, the upper surface is planarized by chemical mechanical polishing (CMP), and the photoresist film is stacked on the first interpoly oxide film to reduce the step of the DRAM area to reduce the level of the logic area. It is achieved by providing a method for manufacturing an MML semiconductor device using wet etching or dry etching to form the same as.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1은 디램영역(a)에 디램게이트전극(20) 및 커패시터(30)를 형성하고, 로직영역(b)에는 로직게이트전극(25)을 형성한 후에 전 영역에 절연막(35)을 적층한 상태를 도시하고 있다.1 shows a DRAM gate electrode 20 and a capacitor 30 formed in a DRAM region a, and a logic gate electrode 25 formed in a logic region b, and then an insulating film 35 is stacked on all regions. The state is shown.
도 2는 상기 절연막(35) 가운데에서 로직영역(b)의 부분을 습식식각 혹은 건식식각으로 제거하여 로직게이트전극(25)을 개방시킨 후에 소오스/드레인영역에 실리사이드층(40)을 형성하는 상태를 도시하고 있으며, 이 실리사이드층(40)은 TiSi2혹은 CoSi2층으로 형성하도록 한다.2 is a state in which the silicide layer 40 is formed in the source / drain region after opening the logic gate electrode 25 by removing a portion of the logic region b by wet etching or dry etching in the middle of the insulating layer 35. The silicide layer 40 is formed of a TiSi 2 or CoSi 2 layer.
그리고, 도 3은 상기 디램영역(a) 및 로직영역(b)의 전면에 일정 두께로 제1인터폴리산화막(45)을 적층하는 상태를 도시하고 있다.3 illustrates a state in which the first interpoly oxide film 45 is stacked on the entire surface of the DRAM region a and the logic region b with a predetermined thickness.
도 4는 상기 로직영역(b)의 제1인터폴리산화막(45)상에 감광막(48)을 적층한 상태를 도시하고 있다.FIG. 4 illustrates a state in which a photosensitive film 48 is stacked on the first interpoly oxide film 45 of the logic region b.
그리고, 도 5는 상기 단계 후에 디램영역(a) 및 로직영역(b)에 제1콘택부위(55)를 갖도록 감광막(50)을 노출시킨 상태를 도시하고 있다.FIG. 5 illustrates a state in which the photosensitive film 50 is exposed to have the first contact portion 55 in the DRAM region a and the logic region b after the step.
도 6은 상기 제1감광막(50)의 제1콘택부위(55)를 통하여 제1인터폴리산화막(45) 및 절연막(35)을 식각하여 디램게이트전극(20) 및 로직게이트전극(25)의 실리사이드층으로 개방되는 제1콘택홀(47)을 형성하는 상태를 도시하고 있다.6 illustrates the etching of the first interpoly oxide layer 45 and the insulating layer 35 through the first contact portion 55 of the first photoresist layer 50 to form the DRAM gate electrode 20 and the logic gate electrode 25. The state of forming the first contact hole 47 opening to the silicide layer is shown.
도 7은 상기 제1콘택홀(47)에 하부금속배선층(60)을 적층한 상태를 도시하고 있다.FIG. 7 illustrates a state in which the lower metal wiring layer 60 is stacked in the first contact hole 47.
도 8은 상기 하부금속배선층(60)상에 제2감광막(65)을 적층한 상태를 도시하고 있다.FIG. 8 illustrates a state in which a second photosensitive film 65 is stacked on the lower metal wiring layer 60.
도 9는 상기 제2감광막(65)을 이용하여 하부금속배선층(60)에서 불필요한 부분을 식각하여 하부금속배선(70)을 형성하는 상태를 도시하고 있다.FIG. 9 illustrates a state in which an unnecessary portion of the lower metal wiring layer 60 is etched using the second photosensitive film 65 to form the lower metal wiring 70.
도 10은 상기 결과물의 전면에 제2인터폴리산화막(75)을 적층하여 하부금속배선(70)이 형성된 위치에 제2콘택부위(85)를 갖는 제3감광막(80)을 형성한 상태를 도시하고 있다.FIG. 10 illustrates a state in which a third photoresist film 80 having a second contact portion 85 is formed at a position where the second interpoly oxide film 75 is stacked on the entire surface of the resultant product to form a lower metal wiring 70. Doing.
도 11은 상기 제3감광막(80)의 제2콘택부위(85)를 통하여 제2인터폴리산화막(75)을 식각하여 하부금속배선(70)이 노출되는 제2콘택홀(77)을 형성한 상태를 도시하고 있다.FIG. 11 illustrates a second contact hole 77 through which the lower metal interconnection 70 is exposed by etching the second interpoly oxide film 75 through the second contact portion 85 of the third photoresist film 80. The state is shown.
도 12는 상기 제2인터폴리산화막(75)의 제2콘택홀(77)에 함입되는 상부금속배선층(90)을 적층한 상태를 도시하고 있다.FIG. 12 illustrates a state in which the upper metal wiring layer 90 embedded in the second contact hole 77 of the second interpoly oxide film 75 is stacked.
도 13은 상기 상부금속배선층(90)에서 불필요한 부분을 제거하기 위한 제4감광막(95)을 적층한 상태를 도시하고 있다.FIG. 13 illustrates a state in which a fourth photosensitive film 95 is stacked to remove unnecessary portions of the upper metal wiring layer 90.
도 14는 상기 제4감광막(95)으로 불필요한 상부금속배선층(90)을 식각하여 하부금속배선(70)과 연결되는 상부금속배선(100)을 형성한 상태를 도시하고 있다.FIG. 14 illustrates a state in which the upper metal wiring layer 90 connected to the lower metal wiring 70 is formed by etching the unnecessary upper metal wiring layer 90 with the fourth photosensitive film 95.
상기한 바와 같이 본 발명에 따른 MML반도체소자제조방법을 이용하게 되면, 디램영역에 고온 공정으로 커패시터를 형성한 후 디램영역 및 로직영역에 적층되어 있는 절연막을 식각하여서 로직영역의 트랜지스터를 개방시켜 실리사이드층을 형성하므로 디램영역의 커패시터 고온 열공정으로 인한 로직영역의 실리사이드층의 비저항 감소 및 손상을 방지할 수 있다.As described above, when the MML semiconductor device manufacturing method according to the present invention is used, a capacitor is formed in a DRAM region by a high temperature process, and then an insulating film stacked in the DRAM region and the logic region is etched to open the transistor in the logic region to open the silicide. Since the layer is formed, the resistivity decrease and damage of the silicide layer of the logic region due to the high temperature thermal process of the capacitor of the DRAM region can be prevented.
또한, 감광막을 이용하여 디램영역 및 로직영역의 제1인터폴리산화막에 제1콘택홀을 형성하여 하부금속배선을 1단계로 형성하고, 다시 상기 결과물에 제2인터폴리산화막을 적층하여 디램영역 및 로직영역에 제2콘택홀을 형성한 후 상부금속배선을 상기 하부금속배선에 연결하므로 제2단계로 분리하여 제1,제2인터폴리산화막의 제1,제2콘택홀을 형성한 후에 금속배선을 적층하므로 식각공정시 활성영역의 데미지(Damage)를 최소화하고 상,하부금속배선층의 갭필링(Gap Filling)을 향상시키도록 하는 매우 유용하고 효과적인 발명이다.In addition, a first contact hole is formed in the first interpoly oxide film of the DRAM region and the logic region by using a photoresist film to form a lower metal wiring in one step, and the second interpoly oxide film is laminated on the resultant, and thus the DRAM region and After the second contact hole is formed in the logic region, the upper metal wiring is connected to the lower metal wiring, so the metal wiring is separated after forming the first and second contact holes of the first and second interpoly oxide layers. Since the lamination process is a very useful and effective invention to minimize the damage (damage) of the active region during the etching process and to improve the gap filling (gap filling) of the upper and lower metal wiring layer.
Claims (6)
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| KR100386455B1 (en) * | 2001-06-30 | 2003-06-02 | 주식회사 하이닉스반도체 | Method for fabricating a merged semiconductor memory device |
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