KR20000016849A - 반도체장치 - Google Patents
반도체장치 Download PDFInfo
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- KR20000016849A KR20000016849A KR1019990012041A KR19990012041A KR20000016849A KR 20000016849 A KR20000016849 A KR 20000016849A KR 1019990012041 A KR1019990012041 A KR 1019990012041A KR 19990012041 A KR19990012041 A KR 19990012041A KR 20000016849 A KR20000016849 A KR 20000016849A
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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Abstract
Description
Claims (6)
- 칩에 형성된 배선과, 그 배선에 대하여 층간막을 개재하여 배치되며, 본딩 와이어를 접합하는 패드가 콘택트를 통하여 접속된 반도체 장치로서,상기 패드의 주변부에 상기 콘택트를 형성함과 동시에, 상기 패드의 중앙부에 상기 와이어를 접합하는 영역에 대응하는 수의 콘택트를 형성한 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서,상기 패드는 사각형상으로 형성되는 것으로서,상기 콘택트를 적어도 패드의 4귀퉁이와 중앙부에 조밀하게 배치한 것을 특징으로 하는 반도체 장치.
- 제1항 또는 제2항에 있어서,상기 콘택트를 패드의 주변부와 중앙부에 환상 그리고 등간격으로 배치한 것을 특징으로 하는 반도체 장치.
- 제1항 또는 제2항에 있어서,상기 콘택트를 패드의 주변부와 중앙부에 환상 그리고 띠형상으로 연속하여 배치한 것을 특징으로 하는 반도체 장치.
- 제l항 내지 제4항 중 어느 한 항에 있어서,상기 패드의 주변부에 배치되는 콘택트를 상기 패드의 변부를 따라서 배치한 것을 특징으로 하는 반도체 장치.
- 제l항 내지 제5항 중 어느 한 항에 있어서,중앙부에 배치되는 콘택트의 수를 그 수와 패드의 박리 불량도의 상관 관계와, 그 수와 패드·와이어 간 접합 강도의 상관 관계에 의거하여 결정한 것을 특징으로 하는 반도체 장치.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP98-223342 | 1998-08-06 | ||
JP22334298A JP3898350B2 (ja) | 1998-08-06 | 1998-08-06 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
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KR20000016849A true KR20000016849A (ko) | 2000-03-25 |
KR100321594B1 KR100321594B1 (ko) | 2002-03-18 |
Family
ID=16796668
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1019990012041A KR100321594B1 (ko) | 1998-08-06 | 1999-04-07 | 반도체 장치 |
Country Status (4)
Country | Link |
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US (1) | US5986346A (ko) |
JP (1) | JP3898350B2 (ko) |
KR (1) | KR100321594B1 (ko) |
TW (1) | TW410451B (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8164195B2 (en) | 2008-10-10 | 2012-04-24 | Hynix Semiconductor, Inc. | Pad structure of semiconductor integrated circuit apparatus |
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US6140710A (en) * | 1999-05-05 | 2000-10-31 | Lucent Technologies Inc. | Power and ground and signal layout for higher density integrated circuit connections with flip-chip bonding |
KR100608608B1 (ko) * | 2000-06-23 | 2006-08-09 | 삼성전자주식회사 | 혼합형 본딩패드 구조를 갖는 반도체 칩 패키지 및 그제조방법 |
US6465895B1 (en) * | 2001-04-05 | 2002-10-15 | Samsung Electronics Co., Ltd. | Bonding pad structures for semiconductor devices and fabrication methods thereof |
JP4801296B2 (ja) * | 2001-09-07 | 2011-10-26 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
US6703710B1 (en) * | 2002-08-15 | 2004-03-09 | National Semiconductor Corporation | Dual damascene metal trace with reduced RF impedance resulting from the skin effect |
US6864581B1 (en) | 2002-08-15 | 2005-03-08 | National Semiconductor Corporation | Etched metal trace with reduced RF impendance resulting from the skin effect |
US6853079B1 (en) | 2002-08-15 | 2005-02-08 | National Semiconductor Corporation | Conductive trace with reduced RF impedance resulting from the skin effect |
US6740956B1 (en) | 2002-08-15 | 2004-05-25 | National Semiconductor Corporation | Metal trace with reduced RF impedance resulting from the skin effect |
JP4627621B2 (ja) * | 2002-10-18 | 2011-02-09 | パナソニック株式会社 | 半導体集積回路 |
JP4517843B2 (ja) | 2004-12-10 | 2010-08-04 | エルピーダメモリ株式会社 | 半導体装置 |
JP4646789B2 (ja) * | 2005-12-02 | 2011-03-09 | パナソニック株式会社 | 半導体装置 |
US8579494B2 (en) * | 2008-08-22 | 2013-11-12 | Sara Lee Tm Holdings, Llc | System and method for dough extrusion |
JP5041088B2 (ja) * | 2011-04-15 | 2012-10-03 | 富士通セミコンダクター株式会社 | 半導体装置 |
JP2016129161A (ja) * | 2013-04-24 | 2016-07-14 | パナソニック株式会社 | 半導体装置 |
US9984987B2 (en) | 2016-08-05 | 2018-05-29 | Nanya Technology Corporation | Semiconductor structure and manufacturing method thereof |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US5175609A (en) * | 1991-04-10 | 1992-12-29 | International Business Machines Corporation | Structure and method for corrosion and stress-resistant interconnecting metallurgy |
US5248903A (en) * | 1992-09-18 | 1993-09-28 | Lsi Logic Corporation | Composite bond pads for semiconductor devices |
US5367195A (en) * | 1993-01-08 | 1994-11-22 | International Business Machines Corporation | Structure and method for a superbarrier to prevent diffusion between a noble and a non-noble metal |
JP3432284B2 (ja) * | 1994-07-04 | 2003-08-04 | 三菱電機株式会社 | 半導体装置 |
JPH08213422A (ja) * | 1995-02-07 | 1996-08-20 | Mitsubishi Electric Corp | 半導体装置およびそのボンディングパッド構造 |
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1998
- 1998-08-06 JP JP22334298A patent/JP3898350B2/ja not_active Expired - Lifetime
-
1999
- 1999-03-15 TW TW088103984A patent/TW410451B/zh not_active IP Right Cessation
- 1999-03-22 US US09/273,472 patent/US5986346A/en not_active Expired - Lifetime
- 1999-04-07 KR KR1019990012041A patent/KR100321594B1/ko not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8164195B2 (en) | 2008-10-10 | 2012-04-24 | Hynix Semiconductor, Inc. | Pad structure of semiconductor integrated circuit apparatus |
Also Published As
Publication number | Publication date |
---|---|
US5986346A (en) | 1999-11-16 |
TW410451B (en) | 2000-11-01 |
JP3898350B2 (ja) | 2007-03-28 |
KR100321594B1 (ko) | 2002-03-18 |
JP2000058583A (ja) | 2000-02-25 |
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