KR20000015399A - Method for forming a contact of a semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a contact of a semiconductor device is provided, which can decrease a contact resistor. CONSTITUTION: Method for forming a contact of a semiconductor device comprises the steps of: forming first and second contact pads to be electrically connected to a semiconductor substrate (100); successively forming a second insulating film and a conductive film at a frond surface of the semiconductor substrate (100); etching the conductive film using a bit line forming mask and forming a bitline (115); patterning a second insulating film using the bit line forming mask; forming a third insulating film; forming a third insulating film at the front surface of the semiconductor substrate (100) and a fourth insulating film; successively etching the fourth and third insulating film to form a contact hole using a contact forming mask; and cleaning the contact hole. Thereby, it is possible to decrease the contact resistor.

Description

METHOD OF FORMING CONTACT FOR SEMICONDUCTOR DEVICE

The present invention relates to a semiconductor device, and more particularly, to a contact forming method of a semiconductor memory device.

1A to 1C are flowcharts sequentially illustrating processes of a method of forming a contact of a conventional semiconductor device, and are cross-sectional views taken along a direction parallel to a word line, and FIGS. 2A to 2C are processes of a method of forming a contact of a conventional semiconductor device. And a cross-sectional view taken in parallel with a bit line.

1A to 2A, in the method of forming a contact of a conventional semiconductor device, first, shallow trench isolation 12 is formed in a semiconductor substrate 10 to define an active region and an inactive region. A polysilicon film 13, a silicide film 14, and a mask nitride film 15 are sequentially formed on the semiconductor substrate 10 with a gate oxide film (not shown) interposed therebetween.

The mask nitride film 15, the silicide film 14, and the polysilicon film 13 are sequentially etched using a gate electrode forming mask to form the gate electrode 16 as shown in FIG. 2A. A nitride film is formed on the semiconductor substrate 10 including the gate electrode 16. The insulating film spacers 17 are formed on both sidewalls of the gate electrode 16 by etching the nitride film by an etch back process.

Next, source / drain regions are formed by implanting impurity ions into the semiconductor substrate 10 on both sides of the gate electrode 16 (not shown). Then, the semiconductor including the gate electrode 16 is formed. The first oxide film 18 for interlayer insulation is formed on the substrate 10.

The pad forming contact hole is formed by etching the first oxide film 18 on both sides of the gate electrode 16 until the surface of the semiconductor substrate 10 is exposed using the pad forming mask. By filling the contact hole with a conductive material, a storage node contact pad 20 and a bit line contact pad 21 electrically connected to the semiconductor substrate 10 are formed. A second oxide layer 22 is formed on the first oxide layer 18 including the contact pads 20 and 21.

A bit line contact hole is formed by etching the second oxide film 22 until the surface of the bit line contact pad 21 is exposed using a mask for forming a bit line contact hole. (Not shown) A bit line forming polysilicon layer 23 and a silicide layer 24 are sequentially formed on the second oxide layer 22 including bit line contact holes. As shown in FIG. 2B, the bit line 25 is formed by sequentially etching the silicide layer 24 and the polysilicon layer 23 using a bit line forming mask.

2B and 3B, a third oxide film 26 is formed on the entire surface of the semiconductor substrate 10.

Next, the contact hole 28 is formed by etching the third oxide layer 26 until the surface of the storage node contact pad 20 is exposed using a contact hole forming mask. Finally, the cleaning process of the contact hole 28 is performed. In this case, as shown in FIGS. 1C and 2C, the contact hole bottom diameter 30 is small. By filling the contact hole with a polysilicon layer, a storage node contact, that is, a buried contact (BC) electrically connected to the storage node contact pad 20 is formed. (Not shown)

As described above, the buried contact resistance connecting the capacitor and the active region of the cell becomes a problem due to the decrease in contact size due to the high integration of the device. If the BC resistance is above a certain value, it causes problems in reading or writing the data in the cell correctly.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems, and an object thereof is to provide a method for forming a contact of a semiconductor device which can reduce a contact resistance of a contact lower portion.

1A to 1C are sequential flowcharts illustrating processes of a method for forming a contact of a conventional semiconductor device, and are sectional views taken along a direction parallel to a word line;

2A to 2C are flowcharts sequentially showing processes of a method for forming a contact of a semiconductor device according to the related art, and are sectional views taken along a direction parallel to a bit line;

3A to 3D are flowcharts sequentially illustrating processes of a method for forming a contact of a semiconductor device according to an embodiment of the present invention, which is a cross-sectional view taken along a direction parallel to a word line; And

4A through 4D are flowcharts sequentially illustrating processes of a method for forming a contact of a semiconductor device according to an exemplary embodiment of the present invention, and are cross-sectional views cut in parallel with bit lines.

* Explanation of symbols for the main parts of the drawings

10, 100: semiconductor substrate 12, 102: device isolation film

16, 106: gate electrode 20, 110: storage node contact pad

21, 111: bit line contact pad 25, 115: bit line

28, 120: storage node contact hole

(Configuration)

According to the present invention for achieving the above object, a contact forming method of a semiconductor device, the first and second contact pads are formed through the first insulating film formed on the semiconductor substrate on which the element is formed and electrically connected to the semiconductor substrate; Making a step; Sequentially forming a second insulating film and a conductive film on the entire surface of the semiconductor substrate; Etching the conductive layer using a bit line forming mask to form a bit line; Patterning a second insulating film using the bit line forming mask; Forming a third insulating film along surfaces of the structures formed on the semiconductor substrate; Forming a fourth insulating film having an etch selectivity with the third insulating film on an entire surface of the semiconductor substrate; Forming contact holes by sequentially etching the fourth and third insulating layers using a contact hole forming mask; The contact hole may be cleaned, but the cleaning hole includes a step of forming a lower diameter of the contact hole.

(Action)

3B and 4B, a method of forming a contact of a novel semiconductor device according to an embodiment of the present invention includes a first insulating layer formed on a front surface of a semiconductor substrate including first and second contact pads formed through a first insulating layer. And a conductive film are formed in sequence. After the bit lines are formed by etching the conductive film using the bit line forming mask, the second insulating film is patterned using the mask. A third insulating film and a fourth insulating film having an etching selectivity are sequentially formed on the third insulating film formed along the surfaces of the structures formed on the semiconductor substrate. The contact holes are formed by sequentially etching the fourth and third insulating films using the contact hole forming mask. The contact hole lower diameter is large when cleaning the contact hole. According to the method of forming a contact of the semiconductor device, a multilayer insulating film having a different wet etch rate is formed to rapidly etch the insulating film under the contact having a high etch rate during the cleaning process, thereby increasing the contact bottom diameter, thereby reducing the contact resistance. You can.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 3A to 3D and 4A to 4D.

3A to 3D are flowcharts sequentially illustrating processes of a method for forming a contact of a semiconductor device according to an embodiment of the present invention, which are cross-sectional views taken along a direction parallel to a word line, and FIGS. 4A to 4D are embodiments of the present invention. FIG. 1 is a flowchart illustrating processes of a method for forming a contact of a semiconductor device according to an embodiment of the present invention. FIG.

3A to 4A, in the method for forming a contact of a semiconductor device of the present invention, first, shallow trench isolation 102 is formed in the semiconductor substrate 100 to define an active region and an inactive region. A gate silicon film 102, a silicide film 104, and a mask nitride film 105 are sequentially formed on the semiconductor substrate 100 with a gate oxide film (not illustrated) interposed therebetween. Next, the mask nitride film 105, the silicide film 104, and the polysilicon film 103 are sequentially etched using a gate electrode forming mask to form a gate electrode 106 as shown in FIG. 4A.

A nitride film is formed on the semiconductor substrate 100 including the gate electrode 106. The insulating film spacers 107 are formed on both sidewalls of the gate electrode 106 by etching the nitride film by an etch back process. Thereafter, a first oxide film 108 is formed on the entire surface of the semiconductor substrate 100. The first oxide film 108 is flatly etched by a chemical mechanical polishing (CMP) process. The pad forming contact hole is formed by etching the first oxide layer 108 on both sides of the gate electrode 106 until the surface of the semiconductor substrate 100 is exposed using the pad forming mask.

After removing the pad forming mask, a polysilicon layer is formed on the first oxide layer 108 including the contact hole to fill the contact hole. Next, the storage node contact pads 110 and the bit line contact pads 111 are formed by being etched flatly in a CMP process so as to be parallel to the first oxide layer 108. In this case, a short circuit between the gate electrode forming conductive layers 103 and 104 and the contact pads 110 and 111 may be prevented by the mask nitride layer 105 and the insulating layer spacer 107.

A second oxide layer 112 is formed on the first oxide layer 108 including the storage node contact pad 110 and the bit line contact pad 111. Next, a bit line contact hole is formed by etching the second oxide film 112 until the surface of the bit line contact pad 111 is exposed using a mask for forming a bit line contact hole. city)

The polysilicon layer 113 and the silicide layer 114 are sequentially formed on the second oxide layer 112 including the bit line contact hole. Thereafter, the silicide layer 114 and the polysilicon layer 113 are sequentially etched using a bit line forming mask to form the bit line 115 as illustrated in FIG. 3B. Next, the second oxide film 112 is patterned by etching the second oxide film 112 using the bit line forming mask. The second oxide film 112 is a film for preventing a short circuit between the bit line 115 and the contact pads 110 and 111.

3B and 4B, after removing the bit line forming mask, a third oxide film 117 is formed along the surfaces of the structures formed on the semiconductor substrate 100. Since the third oxide layer 117 is formed on both sidewalls and the upper surface of the bit line 115, the third oxide layer 117 is also used as a layer for insulating the storage node contact and the bit line formed in a subsequent process. Next, a fourth oxide film 118 is formed on the entire surface of the semiconductor substrate 100. Here, the third oxide film 117 is an oxide film having a higher wet etching rate than the fourth oxide film 118.

3C to 4C, the fourth oxide layer 118 and the third oxide layer 117 are sequentially dry-etched until the surface of the storage node contact pad 110 is exposed using a contact hole forming mask. As a result, the storage node contact hole 120 is formed. Next, after removing the contact hole forming mask, a cleaning process of the storage node contact hole 120 is performed. At this time, the contact hole bottom becomes large as shown in FIGS. 3D and 4D without changing the contact hole top diameter according to the characteristics of the oxide films having different wet etch rates. Accordingly, the present invention is to reduce the overall contact resistance by increasing the contact surface area of the lower surface of the contact hole contacting the storage node contact pad 110.

The storage node contact hole 120 is filled with a polysilicon layer to form a storage node contact electrically connected to the storage node contact pad 110. (Not illustrated) Finally, the fourth oxide layer 118 is formed. The storage node is formed by forming a conductive film pattern electrically connected to the storage node contact on the substrate. (Not shown)

According to the present invention, a multilayer insulating film having a different wet etch rate is formed to rapidly etch an insulating film under a contact having a high etch rate during a cleaning process, thereby increasing a contact lower diameter, thereby reducing contact resistance.

Claims (3)

Forming first and second contact pads through the first insulating film formed on the semiconductor substrate on which the device is formed and electrically connected to the semiconductor substrate; Sequentially forming a second insulating film and a conductive film on the entire surface of the semiconductor substrate; Etching the conductive layer using a bit line forming mask to form a bit line; Patterning a second insulating film using the bit line forming mask; Forming a third insulating film along surfaces of the structures formed on the semiconductor substrate; Forming a fourth insulating film having an etch selectivity with the third insulating film on an entire surface of the semiconductor substrate; Forming contact holes by sequentially etching the fourth and third insulating layers using a contact hole forming mask; Cleaning the contact hole, wherein the contact hole lower diameter is formed to be large during cleaning. The method of claim 1, And the third insulating film is formed of a film having a faster wet etching rate than that of the fourth insulating film. The method of claim 1, And the third insulating layer serves to prevent a short circuit between the bit line and a storage node formed in a subsequent process.