KR100624917B1 - Method for manufacturing of Semiconductor device - Google Patents

Method for manufacturing of Semiconductor device Download PDF

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KR100624917B1
KR100624917B1 KR1020000040650A KR20000040650A KR100624917B1 KR 100624917 B1 KR100624917 B1 KR 100624917B1 KR 1020000040650 A KR1020000040650 A KR 1020000040650A KR 20000040650 A KR20000040650 A KR 20000040650A KR 100624917 B1 KR100624917 B1 KR 100624917B1
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South Korea
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insulating film
forming
interlayer insulating
plug
film
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KR1020000040650A
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Korean (ko)
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KR20020007002A (en
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권영우
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Abstract

본 발명은 스토리지 노드 저항을 감소시키기 위한 반도체 소자의 제조 방법에 관한 것으로, 반도체 기판상에 플러그 형성공정을 통해 제 1 플러그를 형성하는 단계; 상기 제 1 플러그를 포함한 전면에 불순물 이온이 첨가된 제 1 층간절연막을 형성하는 단계; 상기 제 1 플러그상에 열처리를 통해 상기 불순물 이온을 도핑하는 단계: 상기 제 1 플러그 사이의 제 1 층간절연막상에 비트라인을 형성하는 단계; 상기 제 1 층간절연막상에 제 2 층간절연막을 형성하는 단계; 상기 제 2 층간절연막, 제 1 층간절연막을 상기 제 1 플러그의 일정부분이 드러나도록 선택적으로 제거하여 콘택홀을 형성하는 단계: 그리고 상기 콘택홀 내부에 제 2 플러그를 형성하는 단계를 포함하여 형성함을 특징으로 한다.The present invention relates to a method of manufacturing a semiconductor device for reducing storage node resistance, the method comprising: forming a first plug on a semiconductor substrate through a plug forming process; Forming a first interlayer insulating film having impurity ions added to the entire surface including the first plug; Doping the impurity ions through a heat treatment on the first plug: forming a bit line on a first interlayer insulating film between the first plugs; Forming a second interlayer insulating film on the first interlayer insulating film; Forming a contact hole by selectively removing the second interlayer insulating film and the first interlayer insulating film to expose a portion of the first plug; and forming a second plug inside the contact hole. It is characterized by.

콘택저항, PSGContact Resistance, PSG

Description

반도체 소자의 제조 방법{Method for manufacturing of Semiconductor device}Method for manufacturing a semiconductor device

도 1a 내지 1c는 종래의 기술에 따른 반도체 소자의 제조 방법을 나타낸 공정단면도1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the related art.

도 2a 내지 2e는 본 발명에 의한 반도체 소자의 제조 방법을 나타낸 공정단면도2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

도면의 주요 부분에 대한 부호 설명Explanation of symbols for the main parts of drawings

201 : 반도체기판 202 : 소자격리막201: semiconductor substrate 202: device isolation film

203 : 게이트절연막 204 : 게이트203: gate insulating film 204: gate

205 : 제 1 층간절연막 206 : 제 1 절연막205: first interlayer insulating film 206: first insulating film

207 : 제 1 폴리플러그 208 : 제 2 층간절연막207: first polyplug 208: second interlayer insulating film

209 : 비트라인 210 : 제 2 절연막209: bit line 210: second insulating film

211 : 제 3 층간절연막 212 : 포토레지스트 패턴211: third interlayer insulating film 212: photoresist pattern

213 : 콘택홀 213a : 제 2 폴리플러그213: contact hole 213a: second poly plug

본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 콘택 저항 개선을 위한 반도체 소자의 제조 방법에 관한 것이다. The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for improving contact resistance.

이하, 첨부된 도면을 참고하여 종래의 기술에 따른 반도체 소자의 제조 방법에 대하여 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the related art will be described with reference to the accompanying drawings.

도 1a 내지 1c는 종래의 기술에 따른 반도체 소자의 제조 방법을 나타낸 공정단면도이다.1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the related art.

도 1a에 도시한 바와 같이, 반도체 기판(101)에 일정간격으로 STI(Shallow Trench Isolation)구조를 갖는 소자격리막(102)을 형성한 후, 상기 소자격리막(102)이 형성된 반도체 기판(101)상에 게이트절연막(103)을 형성하고, 상기 게이트절연막(103)상에 게이트(104)를 형성한다.As shown in FIG. 1A, after the device isolation film 102 having the shallow trench isolation (STI) structure is formed on the semiconductor substrate 101 at a predetermined interval, the device isolation film 102 is formed on the semiconductor substrate 101. A gate insulating film 103 is formed on the gate, and a gate 104 is formed on the gate insulating film 103.

이어, 상기 게이트(104)상에 제 1 층간절연막(105), 제 1 절연막(106)을 차례대로 형성한 후, 콘택홀(부호없음) 형성을 위해 게이트(104)의 일정부분이 드러나도록 상기 제 1 절연막(106) 및 제 1 층간절연막(105)을 선택적으로 제거한다.Subsequently, the first interlayer insulating film 105 and the first insulating film 106 are sequentially formed on the gate 104, and then a portion of the gate 104 is exposed to form a contact hole (unsigned). The first insulating film 106 and the first interlayer insulating film 105 are selectively removed.

그 후, 전면에 폴리실리콘을 형성하고, CMP공정을 통해 평탄화시켜 콘택홀 내부에 셀 콘택을 위한 제 1 폴리플러그(107)를 형성한다.Thereafter, polysilicon is formed on the entire surface and planarized through a CMP process to form a first polyplug 107 for cell contact inside the contact hole.

도 1b에 도시한 바와 같이, 상기 제 1 폴리플러그(107) 및 제 1 절연막(106)상에 제 2 층간절연막(108)을 형성한 후, 상기 제 1 폴리플러그(107)사이의 제 2 층간절연막(108)상에 비트라인 형성공정을 진행하여 비트라인(109)을 형성한다.As shown in FIG. 1B, after the second interlayer insulating film 108 is formed on the first polyplug 107 and the first insulating film 106, a second interlayer between the first polyplug 107 is formed. The bit line forming process is performed on the insulating film 108 to form the bit line 109.

이어, 상기 비트라인(109)을 포함하여 제 2 층간절연막(108)상에 비트라인(109)을 감싸도록 질화막으로 제 2 절연막(110)을 형성한다. Subsequently, the second insulating layer 110 is formed of a nitride layer on the second interlayer insulating layer 108 including the bit line 109 so as to surround the bit line 109.                         

도 1c에 도시한 바와 같이, 상기 제 2 절연막(110)상에 제 3 층간절연막(111)을 형성하고, 상기 제 1 폴리플러그(107)와 연결되도록 하기 위한 콘택홀(부호없음) 형성을 위해 상기 제 1 폴리플러그(107)의 일정부분이 드러나도록 상기 제 3 층간절연막(111), 제 2 절연막(110), 제 2 층간절연막(108)을 선택적으로 제거하여 콘택홀을 형성한다.As shown in FIG. 1C, to form a third interlayer insulating film 111 on the second insulating film 110 and to form a contact hole (unsigned) to be connected to the first poly plug 107. The contact hole is formed by selectively removing the third interlayer insulating film 111, the second insulating film 110, and the second interlayer insulating film 108 so that a predetermined portion of the first poly plug 107 is exposed.

이어, 상기 제 3 층간절연막(111), 제 2 절연막(110), 제 2 층간절연막(108)의 측벽에 비트라인(109)과 부팅(butting)방지를 위한 질화막측벽(112)을 형성한다.Next, the bit line 109 and the nitride film side wall 112 for preventing booting are formed on sidewalls of the third interlayer insulating film 111, the second insulating film 110, and the second interlayer insulating film 108.

이어, 상기 콘택홀을 포함한 전면에 폴리실리콘을 형성한 후 CMP공정을 통해 평탄화시켜 콘택홀 내부에 스토리지 노드 콘택을 위한 제 2 폴리플러그(113)를 형성한다.Subsequently, polysilicon is formed on the entire surface including the contact hole and then planarized through a CMP process to form a second poly plug 113 for storage node contact inside the contact hole.

그러나 상기와 같은 종래의 반도체 소자의 제조 방법에 있어서, 제 2 폴리플러그를 형성하는 과정에서 공정 마진 감소로 인해 제 1 폴리플러그와 스토리지 노드 콘택 간에 홀 사이즈가 작아져 접촉 면적이 감소하게 되므로 셀 노드 콘택 저항이 증가하게 된다.However, in the conventional method of manufacturing a semiconductor device as described above, since the process margin is reduced in the process of forming the second polyplug, the hole size is reduced between the first polyplug and the storage node contact, thereby reducing the contact area. The contact resistance is increased.

따라서, 콘택저항의 증가는 P검(Probe Test) 및 F/T(Final Test)에서 라이트 명령 신호 후 라스 인에이블 신호가 디스에이블 될때까지의 시간(Write to precharge Lead Time) 즉, "T"(rRWL)를 증가시켜 수율이 낮아진다.Therefore, the increase in contact resistance is the time from the write command signal to the disable enable signal (Prite Test) and the F / T (Final Test) until the erase enable signal is disabled (ie, " T " The yield is lowered by increasing rRWL).

본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 콘택 저항을 개선하기 위한 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a method for manufacturing a semiconductor device for improving contact resistance.

상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 제조 방법은 반도체 기판상에 플러그 형성공정을 통해 제 1 플러그를 형성하는 단계와, 상기 제 1 플러그를 포함한 전면에 불순물 이온이 첨가된 제 1 층간절연막을 형성하는 단계와, 상기 제 1 플러그상에 열처리를 통해 상기 불순물 이온을 도핑하는 단계와, 상기 제 1 플러그 사이의 제 1 층간절연막상에 비트라인을 형성하는 단계와, 상기 제 1 층간절연막상에 제 2 층간절연막을 형성하는 단계와, 상기 제 2 층간절연막, 제 1 층간절연막을 상기 제 1 플러그의 일정부분이 드러나도록 선택적으로 제거하여 콘택홀을 형성하는 단계와, 그리고 상기 콘택홀 내부에 제 2 플러그를 형성하는 단계를 포함하여 형성함을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a first plug on a semiconductor substrate through a plug forming process; Forming a first interlayer insulating film, doping the impurity ions through heat treatment on the first plug, forming a bit line on the first interlayer insulating film between the first plugs, and Forming a second interlayer insulating film on the interlayer insulating film, selectively removing the second interlayer insulating film and the first interlayer insulating film to expose a portion of the first plug, and forming a contact hole; And forming a second plug in the hole.

이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 제조 방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 2e는 본 발명에 의한 반도체 소자의 제조 방법을 나타낸 공정 단면도이다.2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

도 2a에 도시한 바와 같이, 반도체 기판(201)에 일정간격으로 트렌치를 형성하고 상기 트렌치내에 절연막을 형성하는 STI(Shallow Trench Isolation) 구조를 갖는 소자격리막(202)을 형성한 후, 상기 소자격리막(202)이 형성된 반도체 기판(201)상에 게이트절연막(203)을 형성하고, 상기 게이트절연막(203)상에 게이트(204)를 형성한다.As shown in FIG. 2A, a device isolation film 202 having a shallow trench isolation (STI) structure is formed in the semiconductor substrate 201 at predetermined intervals and an insulating film is formed in the trench. A gate insulating film 203 is formed on the semiconductor substrate 201 where the 202 is formed, and a gate 204 is formed on the gate insulating film 203.

이어, 상기 게이트(204)상에 제 1 층간절연막(205), 제 1 절연막(206)을 차 례대로 형성한 후, 콘택홀 형성을 위해 게이트(204)의 일정부분이 드러나도록 상기 제 1 절연막(206) 및 제 1 층간절연막(205)을 선택적으로 제거하여 제 1 콘택홀(도면 부호 없음)을 형성한다.Subsequently, a first interlayer insulating film 205 and a first insulating film 206 are sequentially formed on the gate 204, and then the first insulating film is exposed to expose a portion of the gate 204 to form a contact hole. 206 and the first interlayer insulating film 205 are selectively removed to form a first contact hole (not shown).

상기 제 1 콘택홀을 포함한 전면에 폴리실리콘을 형성한 후, CMP(Chemical Mechanical Polishing)공정을 통해 평탄화시켜 제 1 콘택홀 내부에 셀 콘택(cell contact)을 위한 제 1 폴리플러그(207)를 형성한다.After the polysilicon is formed on the entire surface including the first contact hole, the polysilicon is flattened through a chemical mechanical polishing (CMP) process to form a first poly plug 207 for cell contact inside the first contact hole. do.

도 2b에 도시한 바와 같이, 상기 제 1 폴리플러그(207) 및 제 1 절연막(206) 상에 제 2 층간절연막(208)을 형성한다.As shown in FIG. 2B, a second interlayer insulating film 208 is formed on the first polyplug 207 and the first insulating film 206.

이 때, 상기 제 2 층간절연막(208)은 P+(Phosphorus)가 가미되어 있는 PSG(Phosphor Silicate Glass)로 형성하고, 이후의 열처리(annealing) 과정을 통해 불순물 이온(P+)을 상기 제 1 폴리플러그(207)상에 도핑(doping)한다.In this case, the second interlayer insulating layer 208 is formed of PSG (Phosphor Silicate Glass) added with P + (Phosphorus), and impurity ions (P +) are formed through the annealing process. Doping on 207.

이어, 비트라인 형성공정을 통해 상기 제 1 폴리플러그(207) 사이의 제 2 층간절연막(208)상에 비트라인(209)을 형성한다.Next, a bit line 209 is formed on the second interlayer insulating layer 208 between the first polyplugs 207 through a bit line forming process.

도 2c에 도시한 바와 같이, 상기 비트라인(209)을 감싸면서 제 2 층간절연막(208)상에 질화막을 도포하여 버퍼용 제 2 절연막(210)을 형성한다.As illustrated in FIG. 2C, a nitride film is coated on the second interlayer insulating film 208 while surrounding the bit line 209 to form a second insulating film 210 for a buffer.

도 2d에 도시한 바와 같이, 상기 제 2 절연막(210)상에 제 3 층간절연막(211)을 형성하고, 상기 제 3 층간절연막(211)상에 포토레지스트를 도포한 후 노광 및 현상 공정을 통해 패터닝하여 콘택홀 형성을 위한 포토레지스트 패턴(212)을 형성한다.As shown in FIG. 2D, a third interlayer insulating film 211 is formed on the second insulating film 210, a photoresist is applied on the third interlayer insulating film 211, and then exposed and developed. Patterning is performed to form a photoresist pattern 212 for forming contact holes.

상기 포토레지스트 패턴(212)을 마스크로 하여 상기 제 1 폴리플러그(207) 표면이 일정부분 드러나도록 제 3 층간절연막(211), 제 2 절연막(210), 제 2 층간절연막(208)을 선택적으로 제거하여 제 2 콘택홀(213)을 형성한다.The third interlayer insulating film 211, the second insulating film 210, and the second interlayer insulating film 208 may be selectively selected so that the surface of the first poly plug 207 is partially exposed using the photoresist pattern 212 as a mask. To form a second contact hole 213.

이 때, 제 2 층간절연막(208)은 일반 산화막보다 식각률이 빠른 PSG로 형성되었기 때문에, 상기 제 3 층간절연막(211)보다 상기 제 2 층간절연막(208)이 더 많이 식각이 되어 상기 제 1 폴리플러그(207)와 접촉할 콘택부위 즉, 스토리지 노드 콘택 홀(storage node contact hole)의 크기가 커진다. At this time, since the second interlayer insulating film 208 is formed of PSG having an etching rate faster than that of the general oxide film, the second interlayer insulating film 208 is etched more than the third interlayer insulating film 211, so that the first poly The size of the contact portion to be contacted with the plug 207, that is, the storage node contact hole, is increased.

도 2e에 도시한 바와 같이, 상기 포토레지스트 패턴(212)을 제거하고, 상기 제 2 콘택홀(213)을 포함한 전면에 폴리실리콘을 형성한 후, CMP공정등을 통해 평탄화시켜 제 2 콘택홀(213) 내부에 스토리즈 노드 콘택을 위한 제 2 폴리플러그(213a)를 형성한다.As shown in FIG. 2E, the photoresist pattern 212 is removed, polysilicon is formed on the entire surface including the second contact hole 213, and then planarized through a CMP process or the like to form a second contact hole ( 213 forms a second polyplug 213a for story node contacts.

이로써, 셀 콘택을 위한 제 1 폴리플러그(207)와 스토리즈 노드 콘택을 위한 제 2 폴리플러그(213a)간의 접촉면적은 증가하게 되어 콘택 저항이 감소하게 되고, 또한 상기 제 1 폴리플러그(207)상에 도핑된 불순물이온(P+)에 의해서 콘택 저항이 감소한다.As a result, the contact area between the first polyplug 207 for cell contact and the second polyplug 213a for story node contact is increased to decrease the contact resistance, and also to increase the contact resistance on the first polyplug 207. The contact resistance is reduced by impurity ions (P +) doped.

이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 제조 방법에 있어서 다음과 같은 효과가 있다.As described above, the method of manufacturing a semiconductor device according to the present invention has the following effects.

첫째, 스토리지 노드 콘택 저항을 감소시켜 P검(Probe Test) 및 F/T(Final Test) 결과, 라이트 명령 신호 후 라스 인에이블 신호가 디스에이블 될때까지의 시간(Write to precharge Lead Time) 즉, "T"(rRWL)를 개선하여 수율이 향상시킬 수 있다. cFirst, by reducing the storage node contact resistance, the time from the Probe Test and Final Test (F / T) results to the write to precharge lead time after the write command signal is disabled. Yield can be improved by improving T ″ (rRWL). c

둘째, 고집적의 디지인 룰로 인한 공정 마진 감소로 공정 단계의 증가를 방 지할 수 있다. 즉, 노드 콘택 형성 후 질화막측벽 형성 및 식각 공정등의 추가적인 공정은 스킵해도 공정 마진에는 별 문제가 없기 때문이다.Second, process margins can be prevented from decreasing process margins due to high-density design rules. That is, even if the additional steps such as the formation of the nitride film side wall and the etching process are skipped after the node contact is formed, there is no problem in the process margin.

Claims (4)

반도체 기판상에 플러그 형성공정을 통해 제 1 플러그를 형성하는 단계;Forming a first plug on the semiconductor substrate through a plug forming process; 상기 제 1 플러그를 포함한 전면에 인(P) 이온이 첨가된 PSG막을 형성하는 단계;Forming a PSG film containing phosphorus (P) ions on the entire surface including the first plug; 열처리를 통해 상기 PSG막에 첨가된 인 이온을 상기 제 1 플러그에 도핑하는 단계:Doping the first plug with phosphorus ions added to the PSG film through a heat treatment: 상기 제 1 플러그 사이의 PSG막상에 비트라인을 형성하는 단계;Forming a bit line on the PSG film between the first plugs; 상기 PSG막상에 층간절연막을 형성하는 단계;Forming an interlayer insulating film on the PSG film; 상기 층간절연막 및상기 PSG막을 상기 제 1 플러그의 일정부분이 드러나도록 선택적으로 제거하여 콘택홀을 형성하는 단계: 그리고Selectively removing the interlayer dielectric layer and the PSG layer to expose a portion of the first plug to form a contact hole; and 상기 콘택홀 내부에 제 2 플러그를 형성하는 단계를 포함하여 형성함을 특징으로 하는 반도체 소자의 제조 방법.And forming a second plug in the contact hole. 삭제delete 제 1 항에 있어서,The method of claim 1, 상기 층간절연막은 상기 비트라인을 포함한 PSG막상에 질화막을 더 형성한 후 상기 질화막상에 형성함을 특징으로 하는 반도체 소자의 제조 방법.And the interlayer insulating film is further formed on the nitride film after forming a nitride film on the PSG film including the bit line. 제 1 항에 있어서,The method of claim 1, 상기 층간절연막은 상기 PSG막보다 식각률이 낮은 물질로 형성함을 특징으로 하는 반도체 소자의 제조 방법.The interlayer dielectric layer is formed of a material having a lower etching rate than the PSG layer.
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