KR940002731B1 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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KR940002731B1
KR940002731B1 KR1019890006143A KR890006143A KR940002731B1 KR 940002731 B1 KR940002731 B1 KR 940002731B1 KR 1019890006143 A KR1019890006143 A KR 1019890006143A KR 890006143 A KR890006143 A KR 890006143A KR 940002731 B1 KR940002731 B1 KR 940002731B1
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South Korea
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interlayer insulating
film
etching
insulating film
contact hole
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KR1019890006143A
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Korean (ko)
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KR900019150A (en
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박승갑
김병준
이수천
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삼성전자 주식회사
김광호
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

The semiconductor device manufacturing method includes the steps of: separately forming an interlayer insulating layer into a first interlayer insulating layer and second interlayer insulating layer; etching the first and second interlayer insulating layers to previously form a contact hole; etching the contact hole of the first and second interlayer insulating layer in different etching rates; etching a thermal oxide layer; selectively forming tungsten layers in the contact hole; and coating an aluminum layer on the tungsten layer, thereby reducing contact resistance.

Description

반도체 장치의 제조방법Manufacturing Method of Semiconductor Device

제1도는 반도체 장치의 접촉구에 알루미늄을 도포하는 종래의 공정 순서도.1 is a conventional process flowchart for applying aluminum to a contact hole of a semiconductor device.

제2도는 본 발명의 반도체 장치의 제조방법에 있어서의 접속구의 접촉저항을 감소시키기 위한 공정의 개략도.2 is a schematic diagram of a step for reducing contact resistance of a connection port in a method of manufacturing a semiconductor device of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 불순물 도핑영역 2 : 열산화막1 impurity doped region 2 thermal oxide film

3,31,32 : 층간 절연막 4 : 접속구3,31,32: interlayer insulation film 4: connection port

5 : 알루미늄막 6,7 : 텅스텐 막5: aluminum film 6,7: tungsten film

본 발명은 반도체 장치의 제조방법에 관한 것으로서, 더욱 상세하게는, 반도체장치의 좁은 접촉구에서 불순물 도우핑영역과 접촉구 사이의 접촉면적을 증가시켜 접촉 저항을 감소시키고, 접촉구를 텅스텐막으로 매몰시켜 단차 피복성을 증가시킬 수 있는 반도체 장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to increase contact area between an impurity doping region and a contact hole in a narrow contact hole of a semiconductor device, thereby reducing contact resistance, and making the contact hole a tungsten film. It relates to a method for manufacturing a semiconductor device that can be buried to increase the step coverage.

반도체 제조공정에 있어, 반도체 소자가 고집적화 되어감에 따라, 반도체 장치의 접촉구의 직경이 감소하게 되고, 또한 접촉구의 면적은 접촉구의 직경의 제곱에 비례하기 때문에 접촉구의 직경이 감소하면 접촉구의 면적도 감소하여 접촉구와 불순물 도우링 영역사이의 접촉 면적이 좁아져 접촉저항이 증가하게 된다. 더우기, 접촉구의 직경대 단차의 비가 증가하게 되어, 알루미늄의 단차 피복성도 저하되는 문제점이 있었다.In the semiconductor manufacturing process, as semiconductor elements become highly integrated, the diameter of the contact holes of the semiconductor device decreases, and since the contact hole area is proportional to the square of the diameter of the contact hole, the contact hole area decreases as the diameter of the contact hole decreases. As a result, the contact area between the contact hole and the impurity doring region is narrowed, thereby increasing the contact resistance. Moreover, there was a problem that the ratio of the diameter to the step height of the contact hole was increased, thereby reducing the step coverage of aluminum.

제1도는 반도체 장치의 접촉구에 알루미늄을 도포하는 종래의 방법의 공정도로서, 기판위에 불순물 도우핑영역(1)을 형성하고, 그 위에 열산화막(2), 층간 절연막(3)을 형성한 후 열산화막(2)와 층간 절연막(3)을 식각하여 접촉구(4)를 형성하며, 최종적으로, 알루미늄막(5)을 도포하여 알루미늄 배선을 형성한다.1 is a process diagram of a conventional method for applying aluminum to a contact hole of a semiconductor device, in which an impurity doped region 1 is formed on a substrate, and then a thermal oxide film 2 and an interlayer insulating film 3 are formed thereon. The thermal oxidation film 2 and the interlayer insulating film 3 are etched to form contact holes 4, and finally, the aluminum film 5 is coated to form aluminum wiring.

상기와 같은 방법으로 알루미늄영역(5)을 도포하여 알루미늄 배선을 형성하는 경우에는, 접촉구가 좁기 때문에 접촉면적도 작아 접촉 저항이 증가하게 되고, 접촉저항의 증가는 소자의 신뢰성이 저하되는 원인이 되었다.In the case of forming the aluminum wiring by applying the aluminum region 5 in the above-described manner, the contact area is small, so the contact area is small and the contact resistance is increased. It became.

본 발명은 상기한 바와 같은 종래 기술의 문제점을 해결하기 위해 안출한 것으로, 본 발명의 목적은 좁은 접촉구에서 불순물 도우핑 영역과 접촉구 사이의 접촉면적을 증가시켜 접촉저항을 감소시키고, 접촉구에 텅스텐막을 선택적으로 매몰시켜 단차 피복성을 증가시킨 반도체 장치의 제조 방법을 제공함에 있다.The present invention has been made to solve the problems of the prior art as described above, an object of the present invention is to increase the contact area between the impurity doped region and the contact in a narrow contact to reduce the contact resistance, The invention provides a method for manufacturing a semiconductor device in which a tungsten film is selectively buried to increase step coverage.

상기 목적을 달성하기 위하여 본 발명은, 불순물 도우핑영역상에 형성된 열산화막 및 층간 절연막을 식각하여 접촉구를 형성하고, 그위에 알루미늄막을 도포하여 알루미늄 배선을 형성하는 반도체 장치의 제조방법에 있어서, 상기 층간 절연막을, 서로 다른 식각비를 갖는 재질로 된 제1층간 절연막과 제2층간 절연막으로 분리 형성하고, 이들 제1 및 제2층간 절연막을 사진식각하여 접촉구를 예비 형성하는 공정과, 상기 접촉구에 제1식각용액을 투여하여 제1 및 제2층간 절연막의 접촉구를 상이한 식각비로 식각시키는 공정과, 상기 접촉구 내에 제2식각용액을 투여하여 열산화막을 식각시키는 공정과, 상기 접촉구 내에 텅스텐막을 순차적으로 형성하는 공정과, 알루미늄막을 상기 텅스텐막상에 도포시켜 알루미늄 배선을 완성하는 공정으로 이루어지는 것을 특징으로 하는 반도체 장치의 제조방법을 제공한다.In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device in which a thermal oxide film and an interlayer insulating film formed on an impurity doped region are etched to form a contact hole, and an aluminum film is coated thereon to form an aluminum wiring. Separating the interlayer insulating film into a first interlayer insulating film and a second interlayer insulating film made of materials having different etching ratios, and preliminarily forming a contact hole by photo-etching the first and second interlayer insulating films; Administering a first etching solution to the contact hole to etch the contact holes of the first and second interlayer insulating films at different etching ratios, and administering a second etching solution into the contact hole to etch the thermal oxide film; A step of sequentially forming a tungsten film in the sphere and a step of applying an aluminum film on the tungsten film to complete the aluminum wiring. It provides a method for manufacturing a semiconductor device, characterized in that.

이하, 본 발명의 실시예를 첨부된 도면에 따라 더욱 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

제2도는 본 발명의 반도체 장치의 제조방법에 있어서 알루미늄을 도포하는 공정의 개략도로서, 식각비가 서로 다른 층간 절연막을 사용하여 좁은 접촉구에서 불순물 도우핑영역과 실제로 접촉하는 접촉 면적을 넓게 하여줌으로써 접촉저항을 감소시키고 텅스텐막을 접촉구에 매몰시켜 단차 피복성을 증가시키는 공정의 순서도이다.FIG. 2 is a schematic view of a process of applying aluminum in the method of manufacturing a semiconductor device of the present invention, by using an interlayer insulating film having different etching ratios to make contact with an impurity doped region wide in a narrow contact hole. It is a flowchart of a process of reducing resistance and embedding a tungsten film in a contact hole to increase the step coverage.

기판위에 형성된 불순물 도우핑영역(1)위에 열산화막(2)을 형성하고, 그 위에 인산규산유리(phosposilicate glass, PSG)등으로 만들어진 제1층간 절연막(31)을 도포한 후, 붕규산연산유리(borophosposilicate glass, BPSG)등으로 만들어진 제2층간 절연막(32)을 순차적으로 도포한다. 이때, 제1층간 절연막(31)은 7 : 1 완충불산용액에 대해 식각비가 큰 절연막이고, 제2층간 절연막(32)은 식각비가 적은 절연막이다.After forming a thermal oxide film 2 on the impurity doping region 1 formed on the substrate, applying a first interlayer insulating film 31 made of phosphosilicate glass (PSG) or the like thereon, and then The second interlayer insulating film 32 made of borophosposilicate glass (BPSG) or the like is sequentially applied. At this time, the first interlayer insulating film 31 is an insulating film having a large etching ratio with respect to 7: 1 buffered hydrofluoric acid solution, and the second interlayer insulating film 32 is an insulating film having a small etching ratio.

한편 제2c도에서 접촉구(4) 밑의 열산화막(2)의 식각은 100 : 1 불화암모늄 용액을 사용하여 행한다.Meanwhile, in FIG. 2C, the thermal oxide film 2 under the contact hole 4 is etched using a 100: 1 ammonium fluoride solution.

상기와 같이, 층간 절연막(31,32)을 형성한 후 사진식각공정을 거쳐 제2a도와 같이 접촉구(4)를 형성하고, 7 : 1 완충불산으로 층간 절연막(31,32)을 식각하면 완충 불산용액에 대해 식각비가 큰 제1층간 절연막(31)이 식각비가 작은 제2층간 절연막(32)보다 더 많이 식각되어 제2b도에 나타낸 바와 같이 불순물 도우핑영역(1)과 접촉구(4) 사이의 접촉부분이 넓게 형성될 수 있게 된다.As described above, after the interlayer insulating films 31 and 32 are formed, the contact holes 4 are formed through the photolithography process as shown in FIG. 2A, and when the interlayer insulating films 31 and 32 are etched with 7: 1 buffered hydrofluoric acid, they are buffered. The first interlayer insulating film 31 having a large etch ratio with respect to the hydrofluoric acid solution is more etched than the second interlayer insulating film 32 having a small etch ratio, so that the impurity doped region 1 and the contact hole 4 are shown in FIG. The contact portion between them can be formed wide.

그 다음에, 제2d와 e도에 나타낸 바와 같이 하부가 넓게 형성된 접촉구(4) 내에, 1차로 기상도포법 등으로 텅스텐을 선택적으로 도포하여 제1선택 텅스텐(6)을 형성하고, 층간 절연막(31),(32)이 벌어지는 것을 방지하기 위해 좁은 접속구(4)에 2차로 텅스텐막을 기상도포법 등으로 선택적으로 도포함으로써 제2선택 텅스텐막(7)을 형성한다.Next, as shown in FIGS. 2D and e, firstly, tungsten 6 is selectively applied by selectively applying tungsten by vapor phase coating or the like in the contact hole 4 having a wide bottom, and an interlayer insulating film. The second selective tungsten film 7 is formed by selectively applying a tungsten film to the narrow connection port 4 secondly by vapor phase coating or the like in order to prevent the gaps between (31) and (32).

이때, 제1 과 2선택 텅스텐막(6), (7)을 도포함에 있어서의 화학반응 과정은 다음과 같다.At this time, the chemical reaction process in applying the first and second selective tungsten films 6 and 7 is as follows.

Figure kpo00002
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최종적으로, 제2f도와 같이 알루미늄막(5)을 도포하여 배선을 형성한다.Finally, the aluminum film 5 is applied as shown in FIG. 2f to form wiring.

이상에서 설명한 바와 같이, 본 발명에 의하면, 특정 식각용액에 대한 식각비가 서로 다른 층간 절연막을 사용하여, 좁은 접촉구에서 불순물 도우핑영역과 접촉구 사이의 접촉면적을 넓혀줌으로써, 접촉저항을 감소시킬 수 있으며, 동시에 텅스텐막으로 접촉구를 매몰시킨 후, 그 위에 알루미늄막을 배선함으로서, 알루미늄 배선의 단자 피복성을 증가시키는 효과를 얻을 수 있다.As described above, according to the present invention, by using an interlayer insulating film having different etching ratios for a specific etching solution, the contact resistance can be reduced by increasing the contact area between the impurity doping region and the contact hole in a narrow contact hole. At the same time, after the contact hole is buried with a tungsten film and the aluminum film is wired thereon, the effect of increasing the terminal coverage of the aluminum wiring can be obtained.

Claims (1)

불순물 도우핑 영역상에 형성된 열산화막 및 층간 절연막을 식각하여 접촉구를 형성하고, 그 위에 알루미늄막을 도포하여 알루미늄 배선을 형성하는 반도체 장치의 제조방법에 있어서, 상기 층간 절연막(3)을, 서로 다른 식각비를 갖는 재질로 제1층간 절연막(31)과 이 제1층간 절연막 보다 완충 불산용액에 대하여 식각비가 큰 제2층간 절연막(32)으로 분리 형성하고, 가) 이들 제1 및 제2층간 절연막(31)과 (32)를 사진 식각하여 접촉구(4)를 예비 형성하는 공정과, 나) 상기 접촉구(4)에 7 : 1 완충불산용액을 투여하여 제1 및 제2층간 절연막(31), (32)의 접촉구를 상이한 식각비로 식각시키는 공정과, 다) 상기 접촉구(4)내에 불화암모늄용액을 투여하여 열산화막(2)을 식각시키는 공정과, 라) 상기 접촉구(4)내에 텅스텐막(6,7)을 기상도포법으로 순차적으로 선택형성하는 공정과, 마) 알루미늄막(5)을 상기 텅스텐막(7)상에 도포시켜 알루미늄 배선을 완성하는 공정으로 이루어지는 것을 특징으로 하는 반도체 장치의 제조방법.A method of manufacturing a semiconductor device in which a thermal oxide film and an interlayer insulating film formed on an impurity doped region are etched to form a contact hole, and an aluminum film is coated thereon to form aluminum wiring, wherein the interlayer insulating film 3 is different from each other. A material having an etching ratio is formed by separating the first interlayer insulating film 31 and the second interlayer insulating film 32 having a larger etching ratio with respect to the buffered hydrofluoric acid solution than the first interlayer insulating film, and a) these first and second interlayer insulating films. Photo-etching (31) and (32) to preform the contact holes (4), and b) administering a 1: 1 buffered hydrofluoric acid solution to the contact holes (4) to form the first and second interlayer insulating films (31). And (3) etching the contact holes of (32) with different etching ratios, (c) etching the thermal oxide film (2) by administering an ammonium fluoride solution into the contact holes (4), and d) the contact holes (4). ) Selective formation of tungsten films (6,7) sequentially by vapor phase coating The step of e) The manufacturing method of a semiconductor device containing aluminum film 5, characterized in that comprising a step of finish to the aluminum wiring applied on the tungsten film 7.
KR1019890006143A 1989-05-08 1989-05-08 Manufacturing method of semiconductor device KR940002731B1 (en)

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